JPH03144778A - Image memory device - Google Patents

Abstract

PURPOSE:To improve a memory access speed by constituting the image memory device of plural image memory blocks and plural address registers and executing memory accesses in parallel. CONSTITUTION:One word to be the reading or writing unit of data consists of picture block information [(m X n X p) bits] constituted of picture elements [(p) bits/picture element, (p) is an integer >=1] of (m) lines and (n) rows and arranged on one of plural different image blocks 31 to 34 capable of independent ly accessing adjacent picture blocks. The image memory blocks 31 to 34 are provided with four independent address registers 21 to 24, and only when an access request is generated from an image arithmetic unit 1 to each image memory block, the image memory block latches a signal on an address bus. Thereby, access to the succeeding necessary picture block information in the other image memory block during the access of the picture block information in the address of one picture memory block. Consequently, memory access can rapidly be attained.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention generates figures from coordinate data, etc., performs conversion and analysis processing such as restoration, enhancement, recognition, etc. on images obtained from cameras, etc. Or even if it is related to an image memory device used in an image processing device that displays these figures/images on a display device, this is a conventional technique and a method for configuring an image memory device of a conventional image processing device! Friend analogy (engineering) Graphic control VLSI (ACR
TC) Architecture”, Kouhiro Katsura et al., Information Processing Society of Japan Research Report Volume 1. 85. No. 53, CA-60
5 (December 1985), Figure 5(a) is a diagram showing the configuration method of this conventional image memory device. In , a block (1 word), which is the unit of access by the image processing device to the image memory device, represents which pixel information is stored.One block (1 word) of the image memory device is arranged horizontally. Although it corresponds to n (=4) pixels and one word consists of 1xp (=32) bits, it is also common to allocate horizontal blocks to consecutive addresses in the image memory device.
When configuring this image memory device, it is necessary to use dynamic RAM with a high degree of integration.
The hardware configuration of the image processing device that performs figure generation and image processing (conversion and analysis) is shown in Figure 5 (b). It is composed of an image memory block 39 for storing information, and an image processing unit l!J<,
The pixel positions at which straight lines, arcs, etc. should be written are calculated one after another and written into the image memory block 39. In image processing, the image processing device 1 reads the block data in the image memory block 39, processes it, and then writes it back into the image memory block 39. Image calculation device
When accessing the image memory block 39, the image processing unit 1 outputs the block address of the image memory block 39 via the address bus L. Block information is exchanged via the data bus.

Problems to be Solved by the Invention However, with the above configuration (Part 1 Dynamic R
Since the AM cycle time (the time interval between reading and writing data at a specific address and reading and writing data at the next different address) is longer than the processing time of the image processing device, it has the following problems: In generation and processing, it is almost always the case that the pixel at position 1 is adjacent to the currently processed pixel position that is accessed continuously, but if the pixel happens to be in the left or right direction, the information will not be stored as long as it does not cross a word boundary. Therefore, it is necessary to provide a one-word buffer in the image processing unit (i.e., pixels that exist in the same word). When the data crosses a word boundary vertically, diagonally, or even horizontally, if they are allocated in words with different block addresses, the effect of the buffer described above is It is necessary to wait for a predetermined cycle time to elapse from the start time before starting to access the currently required block data.8 Especially when the image processing device 1 is very fast (see Access is the performance bottleneck of the entire image processing device.The present invention takes this into account, and aims to provide an image memory device that enables high-speed image data access. On C, block information (1 word power <, which is the unit of data read or write), consisting of m60 columns (rrcn is an integer of 1 or more) of pixels (p bits/pixel, p is an integer of 1 or more) The present invention is also effective in an image memory device in which adjacent blocks are arranged in different image memory blocks of a plurality of independently accessible image memory blocks. While accessing partition information to an address in an image memory block, the next necessary partition information access to another image memory block is started, thereby substantially speeding up memory access. Embodiment FIG. 1 is a diagram illustrating an image memory device in a first embodiment of the present invention, and FIG. 1(a) shows the correspondence between image information and the image memory device that stores it. Fig. 5(b) is a block diagram of an image processing device equipped with the image memory device of the present invention.
Image processing device similar to 21 to 24 are address bus
Reference numerals 31 to 34 denote image memory blocks for storing images.The operation of the image processing apparatus of this embodiment configured as described above will be described below. One word (m (=2) as shown in Figure 1(a))
It is block information consisting of pixels in rows n (=2) columns, and 41 pixels are p (=8) bits, so 2i1 word is mX
rlXp(=32) bits Here, the first image memory block #A, 31 in FIG. 1(b) is
In the same way, the second image memory block # & 32 stores the section information of even rows and odd columns of the image information of one screen in a), and the third image memory block # & 32 stores the section information of even rows and odd columns.
C, 33 stores block information of odd rows and even columns, and fourth image memory block #D, 34 stores block information of odd rows and odd columns.
1 to 34 have four independent address registers 21 to 2.
4 is provided, and latches the address bus signal only when there is an access request from the image processing device 1 to each image memory block. L Let us specifically explain the operation of this embodiment using straight line drawing as an example. When the coordinates (x, y) are (pixel column number pixel row number), for example, (3, 2)
When drawing a straight line connecting coordinates (13,6) from , (3,2), (4,2), (5,3), (6,3
)(7,4), (8,4), (9,4), (10
゜5), (11,5), (12,6), (13,
6) There is a heavy need to access each pixel of 6).When converted to the block number containing these pixels, [1, 1],
[2,1], [2,1], [3,1] [3,2]
, [4,2, [4,2], [5゜2],
[5,2], [6,3], [6,3]
Tonamo Tadari, [X, Yl is [block row number]
block line number]. The image processing device 1 has at least a number of buffers for temporarily storing image information of a section.Therefore, it is not necessary to access the same section continuously.Therefore, the actual access to the image memory device GEL[1, 1], [2,
1], [3,1], [3,2], [4,2], [
5, 2], [6, 3] Tonamo The image memory block numbers storing these sections are #ku #0 #ku #B, #A, #&#C
Therefore, the same image memory block number is never consecutive L\ Therefore, image memory block #D,
By the time access of the first block data [1゜l] to image memory block #α 33 is completed, it is possible to start accessing the next block data [2゜1] to image memory block #α 33. Rope board If the image processing device l consecutively stores the necessary block information in different image memory blocks j! It is possible to transfer the block data that is already being accessed while reading it, and send the next block address to the address register of another image memory block. At this point, the images can be transferred one after another to the image processing device l via the data bus, so-called interleaved transfer.As described above, according to this embodiment, by providing four independently accessible image memory blocks, , it is possible to simultaneously access the memory and substantially shorten the memory access time. Figure M3 is a diagram illustrating an image memory device according to a second embodiment of the present invention; Figure 3(a) is an illustration of the correspondence between image information and the image memory device that stores it, and Figure 3(b) is a diagram showing the countries in which the image processing apparatus equipped with the image memory device of the present invention is constructed. 1 is an image processing device similar to that shown in FIG. 1; 25 and 26 are address buses; 35 and 36 are image memory blocks for storing images; and the image processing device of this embodiment configured as described above. The operation will be explained below.The I word 1 user which is the unit of access to the image memory blocks 35 and 36 is the same as in Fig. 1, but the operation is the same as in Fig. 3 (Fig.
The first image memory block #A135 in b) is
), and the second image memory block # & 36 stores the block information of even rows and even columns and the block information of odd rows and odd columns of the image information of one screen. These two image memory blocks 35 and 36 have two independent address registers 25.
, 26 are provided, and the address bus signal is latched only when there is an access request from the image processing unit l to each image memory block. As an example, to specifically explain the operation of this embodiment, the coordinates (3°2) to (1
3, 6), the actual image memory device access block numbers [1, 1], [2, 1,
[3,1], [3,2] [4,2], [5,2
], [6, 3] (Top In this embodiment, image memory block numbers #A, #&#A,#&#A,#&
#B, and the same image memory block number is rarely consecutive.1 This is especially true when there are many horizontal and vertical lines such as ruled lines in general documents, or when drawing by dividing area drawing into horizontal or vertical lines. Although there are many trends
Therefore, the interleaved transfer similar to the first embodiment works effectively, but as described above, according to the present embodiment, by providing only two independently accessible image memory blocks, the first embodiment can be improved. 4 is a diagram illustrating an image memory device according to a third embodiment of the present invention. FIG. 4(a) is a diagram illustrating the correspondence between image information and an image memory device that stores it. FIG. 4(b) is an image processing device equipped with the image memory device of the present invention. In Figure 4, even the member countries of
l is an image processing device 27 and 28 are address registers similar to those shown in FIG. 1; 37. and 38 are image memory blocks for storing images; The operation will be explained below, but one word (above) is the unit of access to the image memory blocks 37 and 38 (the same as in Fig. 1).
The first image memory block 37 in b) is the same as the first image memory block 37 in FIG.
Even though the second image memory block 38 stores the even-numbered column section information of the screen image information, and the second image memory block 38 stores the odd-numbered column section information, these two image memory blocks 37 and 38 have two independent blocks. Address registers 27 and 28 are provided, and address bus signals are latched only when there is an access request from the image processing device l to each image memory block. Let us specifically explain the operation of this embodiment by taking straight line drawing as an example (from 3°2> to coordinates (1
3, 6), the actual image memory device access block numbers [1, 1], [2, 1],
[3,1], [3,2], [4,2], [5
,2], [6,3]C friend In this embodiment, the image memory block numbers #&#A, #B, #&#
A, #&#A, and the same image memory block numbers are rarely consecutive.Especially in the case of area transfer that performs drawing processing in units of horizontal lines, fill, and area fill as well as underline drawing. ,%
Therefore, the same interleaved transfer as in the first embodiment works effectively, but as described above, according to this embodiment, two independently accessible image memory blocks are provided, each with an even number column and an odd number column. By storing the partition information, it is possible to simultaneously access the memory with a smaller amount of hardware compared to the second embodiment, and without compromising parallelism much compared to the second embodiment, which substantially reduces the memory access time. In the above embodiments, p=s was explained, but it goes without saying that p=1 may be used for black-and-white binary figures. According to the authors, by configuring an image memory device with multiple image memory blocks and address registers and performing memory access in parallel, it is possible to substantially improve memory access speed, and the practical effect is significant.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of an image memory device according to a first embodiment of the present invention. FIG. 2 shows an explanation of the operation of an image memory device according to an embodiment of the present invention. FIG. 3 shows a structure of an image memory device according to a second embodiment of the present invention. Configuration of the image memory device @ Figure 4 shows the configuration of the image memory device according to the third embodiment of the present invention. Figure 5 shows the configuration of the conventional image memory device in various countries. 21-28...
-Address Regisuku 31-39... Image memory block.

Claims (3)

[Claims] (1) An image processing device that performs image processing such as figure generation, image conversion, and image analysis;
m × of a block consisting of pixels (p bits/pixel, p is an integer of 1 or more) in rows and n columns (m and n are both integers of 1 or more)
A data bus capable of transferring image information consisting of n×p bits at a time, an address bus that conveys block address information output by the image processing device, and a block connected to the data bus in even-numbered rows and even-numbered columns. If the block address information outputted from the first image memory block storing image information and the image processing device corresponds to the block in the even-numbered row and even-numbered column, the signal on the address bus is latched and the a first address register that supplies address signals to one image memory block; a second image memory block that is connected to the data bus and stores image information of blocks in even-numbered rows and odd-numbered columns; If the block address information output from the arithmetic unit corresponds to a block in an even-numbered row and an odd-numbered column, a second image memory block latches the signal on the address bus and supplies an address signal to the second image memory block. a third image memory block that is connected to the data bus and stores image information of the block in the odd row and even column; and a third image memory block that is connected to the data bus and stores image information of the block in the odd row and even column; a third address register that latches the signal on the address bus and supplies an address signal to the third image memory block; a fourth image memory block storing image information of the eye compartment;
When the block address information output from the image processing device corresponds to a block in an odd row and an odd column, the signal on the address bus is latched and an address signal is supplied to the fourth image memory block. An image memory device comprising a fourth address register and a plurality of image memory blocks independently and simultaneously accessing memory. (2) an image processing device that performs image processing such as figure generation, image conversion, and image analysis;
m × of a block consisting of pixels (p bits/pixel, p is an integer of 1 or more) in rows and n columns (m and n are both integers of 1 or more)
A data bus capable of transferring image information consisting of n×p bits at a time, an address bus that conveys block address information output from the image processing device, and even-numbered rows, even-numbered columns, and odd-numbered rows and odd-numbered When the first image memory block that stores image information of a block in a column and the block address information output from the image processing device correspond to a block in an even-numbered row and an even-numbered column or an odd-numbered row and an odd-numbered column. , a first address register that latches a signal on the address bus and supplies an address signal to the first image memory block; If the block address information output from the second image memory block that stores the image information of the block and the image processing device corresponds to the block in the even-numbered row and odd-numbered column or the odd-numbered row and even-numbered column, the address and a second address register that latches signals on the bus and supplies address signals to the second image memory block, and is characterized in that a plurality of image memory blocks access memory independently and simultaneously. image memory device. (3) an image processing device that performs image processing such as figure generation, image conversion, and image analysis;
m × of a block consisting of pixels (p bits/pixel, p is an integer of 1 or more) in rows and n columns (m and n are both integers of 1 or more)
a data bus capable of transferring image information consisting of n×p bits at a time, an address bus that conveys block address information output by the image processing device, and image information of blocks in even-numbered columns connected to the data bus. If the block address information output from the image processing device corresponds to a block in an even-numbered column, the signal on the address bus is latched and the block is stored in the first image memory block. a first address register that supplies address signals to the blocks; a second image memory block that is connected to the data bus and stores image information of blocks in odd-numbered columns; a second address register that latches the signal on the address bus and supplies an address signal to the second image memory block when the block address information corresponds to a block in an odd-numbered column; An image memory device characterized in that a plurality of image memory blocks independently and simultaneously access memory.