JPH05113768A - Frame memory circuit - Google Patents

Abstract

PURPOSE:To display a large picture at high speed by dividing a display into upper and lower ones and using a 2-port memory for image effectively as a frame memory to be applied to a display device which requires display information on these displays at the same time. CONSTITUTION:In random access, data is divided into upper and lower ones, and the upper and lower data are swapped to an address one address different (determined by a random access address) from memory blocks 8-1 and 8-2 which constitute a frame memory 8 comprising two port memories according to which of the data for upper and lower displays is used by a data transformer circuit 2, or they are stored as they are. In display access, data for upper and lower displays output from the memory blocks 8-1 and 8-2 is divided correctly by clock signals CLK2 and CLK3 from a display timing control circuit 4, held in a latch circuit 11, and sent to a data input/output port 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame memory circuit having a frame memory for storing display information of a display device which displays a screen by vertically dividing the screen into two parts.

[0002]

2. Description of the Related Art In a recent flat display device such as a liquid crystal display, a plasma display, an EL (electroluminescence) display and the like, most of the display information interfaces are performed in 8-bit or 16-bit parallel, and the bit serial of the conventional CRT display. Interface is different.

Moreover, in this type of flat display device, as shown in FIG. 7, the display screen is often divided into upper and lower parts, and upper side data and lower side data are input and displayed in many cases. Such control becomes necessary for a large screen display.

Conventionally, as shown in FIG. 8A, a frame memory for storing display information to be displayed on a screen divided into two as shown in FIG. 7 has a frame memory itself for upper screen and lower screen. For two, or as shown in FIG.
As shown in (b), the upper screen data nU and the lower screen data nL (n = 0, 1, 2, ...) Are alternately stored at consecutive addresses.

[0005]

As described above, the display of a recent flat display device, that is, a display device in which a display screen is vertically divided into two and horizontal parallel data is simultaneously input and displayed for each of the upper and lower screens. Conventionally, a frame memory for storing information has a configuration in which the frame memory itself is divided into two for an upper screen and a lower screen (referred to as a first frame memory configuration), or data for an upper screen and a lower screen. A configuration has been adopted in which data is alternately stored at consecutive addresses (referred to as a second frame memory configuration).

However, the conventional frame memory having the above structure has the following problems. First, in the above first frame memory configuration, in order to perform high-speed drawing, a 2-port DRAM (2-port dynamic RAM such as TC524256 manufactured by Toshiba) is used and a wider bit width configuration is adopted. However, there is a problem in that a memory element larger than the memory capacity actually required is required, which is wasteful and the mounting area is wide. Further, in the above first frame memory configuration, when SRAM (static RAM) or DRAM is used, there is a problem that high speed drawing cannot be performed.
On the other hand, in the above second frame memory configuration, 2 port R
There is a problem that AM cannot be used and therefore high speed drawing cannot be performed.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a frame memory for an image as a frame memory which is applied to a display device in which a display screen is vertically divided into two and each display information is required. It is an object of the present invention to provide a frame memory circuit that can effectively use a port memory and can display a large screen at high speed.

[0008]

According to the present invention, a display screen is divided into upper and lower parts, and each of the upper and lower parts is
A frame memory with a 2-port memory for storing display information of a display device for simultaneously inputting and displaying horizontal parallel data such as 8 and 16 bits, and a bit width of an interface of the display device or a bit width of an integral multiple thereof. And a random access address is allocated to two memory blocks of the frame memory, and at least the least significant bit of the address of each memory block is independent. A read / write address conversion circuit for controlling the least significant bit depending on whether the position on the screen to be accessed is on the upper side or the lower side,
When connecting the random access data to the two memory blocks of the frame memory, the data width is divided into two, and the data divided into two by the data width is swapped depending on whether the access position on the screen is the upper side or the lower side, or A read / write data conversion circuit that is connected without swapping, a display address generation circuit that scans a screen divided into two, and an address multiplexer that switches between the read / write address and the display address and outputs to the memory block of the frame memory. , The upper and lower screen data output simultaneously from the output data port of the frame memory is divided into two by the data width, and swapped or not swapped according to the least significant bit of the display address, the upper screen data output port and the lower screen Display data conversion times for passing to the output data output port In which characterized in that a and.

[0009]

In the above construction, the image 2-port memory consisting of two memory blocks is used as the frame memory for the display device which is divided into upper and lower parts and the display data is inputted simultaneously.

The read / write address conversion circuit uses the CP
Addresses for random access from U and the like are distributed to two memory blocks of the frame memory, and the least significant bit of the address of each memory block is controlled depending on whether the position on the screen to be accessed is the upper side or the lower side. Also, lead /
The write data conversion circuit divides the data width of the random access data from the CPU or the like into upper and lower parts and divides the upper and lower parts of the divided data into two depending on whether the position on the screen to be accessed is the upper side or the lower side. Replace (swap) or leave as is and connect to two memory blocks. Therefore, at the same address of the two memory blocks of the frame memory, the horizontal parallel data for the upper screen (display data) and the horizontal parallel data for the lower screen (display data) having the same relative position as this data are
The memory blocks are switched (stored) for each address.

In the display access to the frame memory, the same display address is used to output the upper screen display data and the lower screen display whose relative position is the same from the output data port of the frame memory (of the two memory blocks). Data and are output at the same time. At this time, which memory block of the frame memory the upper screen display data and the lower screen display data are output is, as is clear from the control at the time of random access, that is, the least significant bit of the display address. Determined by Therefore,
The display data conversion circuit divides the upper and lower screen data output from the frame memory at the same time into two, and replaces (swap) the upper and lower parts of the divided data with the least significant bit of the display address. Correctly deliver the screen display data to the upper screen data output port and the lower screen display data to the lower screen data output port.

In this way, the frame memory is composed of two memory blocks using a two-port memory chip,
At the time of random access from the CPU or the like, the data for random access is divided into upper and lower parts, divided into two memory blocks, and stored simultaneously.
High-speed drawing is possible. At this time, the divided data is divided into two by one in the two memory blocks of the frame memory.
Depending on whether it is upper screen data or lower screen data at different addresses, the upper and lower positions are swapped or stored as they are. Therefore, the same address of two memory blocks has the same address for the upper screen. The data and the data for the lower screen having the same relative position as this data are stored by switching the memory block for each address.

However, at the time of display access, the data for the upper and lower screens, which are simultaneously output from the two memory blocks, are divided into two, and are correctly divided into the upper screen and the lower screen according to the least significant bit of the display address and displayed. Since it is sent to the device, there is no problem even if the data for the upper screen and the data for the lower screen whose relative position is the same as this data are stored by switching the memory block for each address,
It is possible to maximize the high speed of the 2-port memory.

[0014]

1 is a block diagram showing the structure of a frame memory circuit according to an embodiment of the present invention. The frame circuit of FIG. 1 is applied to, for example, a large-screen liquid crystal display device in which a display screen is vertically divided into two and each display information is required at the same time.

In FIG. 1, reference numeral 1 denotes a processor bus (hereinafter referred to as a CPU bus) of a processor (CPU) such as a microprocessor (not shown) which is drawn in (the frame memory of) the present frame memory circuit.

Reference numeral 2 is a data conversion circuit connected to a data bus of, for example, a 32-bit width in the CPU bus 1. The data conversion circuit 2 divides the data bus in the CPU bus 1 into two by the data bit width, and the data bus divided into two is swapped or not swapped according to an instruction from the address conversion circuit 3 described below. , Is connected to a frame memory 8 described later.

Reference numeral 3 is an address conversion circuit connected to the address bus in the CPU bus 1. Address conversion circuit 3
Determines whether to access the upper side or the lower side of the display screen based on the information (random access address) of the address bus in the CPU bus 1.
It is configured to output the determination signal. Further, the address conversion circuit 3 doubles the random access address, and controls whether to add "0" or "1" to the least significant bit or not when the upper side is accessed and the lower side is accessed. It is configured to be possible.

Reference numeral 4 denotes a display timing control circuit for generating timing necessary for a liquid crystal display device (not shown) and its interface, and 5 scans a half portion of the display screen according to a timing signal from the display timing control circuit 4. It is a display address generation circuit.

6 is an address multiplexer (MUX) for selecting either the address from the address conversion circuit 3 or the display address generation circuit 5 in accordance with the random access or the display access, and 7 is the address selected by the address multiplexer 6. Are divided into rows and columns (col) and multiplexed, and the frame memory 8
Output to the address multiplexer (row / col
MUX).

Reference numeral 8 is a frame memory composed of a 2-port memory for storing display information of the display device. The frame memory 8 has two memory blocks 8-1, 8 corresponding to half the data bus width of the CPU bus 1.
Divided into -2. Each memory block 8-1, 8-2 is composed of several 2-port memory chips (2-port DRAM chips)
It is composed by. These memory blocks 8-1, 8-2
A different address is input to each.

Reference numeral 9 is a memory timing generation circuit. The memory timing generation circuit 9 performs generation of signals such as RAS, CAS, DT / OE required for the frame memory 8, generation of row / column address switching signals, display / random access switching signals, and refresh control. To do.

Reference numeral 10 is a data input / output port composed of a latch circuit. The data input / output port 10 holds the parallel data for the display device for the time required for the interface in synchronization with the clock CLK1 from the display timing control circuit 4.

Reference numeral 11 is a latch circuit. Latch circuit 11
Receives the display data output from the frame memory 8 with the latch clock CLK2 or CLK3 from the display timing control circuit 4 and passes it to the data input / output port 10.

In this embodiment, the output data of the frame memory 8 is controlled by controlling the output order of the display data by the combination of the display timing control circuit 4, the memory timing generation circuit 9, the frame memory 8 and the latch circuit 11 described above. A data conversion circuit for swapping or inputting to the latch circuit 11 without swapping is configured.

FIG. 2 shows a state in which the address of the frame memory 8 is assigned to a position on the screen of the liquid crystal display device not shown in FIG. 1, that is, the relationship between the screen image stored in the frame memory 8 and the address. Is an example in which the screen size is 1152 dots in the horizontal direction and 900 lines in the vertical direction.

Here, as shown in FIG. 2, the display device divides the screen into upper and lower parts, and horizontally inputs 8 dots for each screen (upper and lower screens), for a total of 16 dots at the same time. The screen shall be simultaneously scanned and displayed. The upper screen shows 0U (Upper
), 1U, 2U, etc., addresses are assigned in 8-bit units, and 0L (Lower
), 1L, 2L, ... and assign an address in 8-bit units.

FIG. 3 is a view of a CPU (not shown) that reads / writes the frame memory 8 when there is a relationship between the screen image and the address of the frame memory 8 as shown in FIG. The relationship between the address and the display position is shown.

From the CPU, as shown in FIG. 3, the entire display screen has continuous addresses from the upper left to the lower right. However, the data width of the CPU is 32 bits.

FIG. 4 shows the relationship between the address and data of the 2-port memory chip (2-port DRAM chip) itself and the display position when the frame memory 8 is formed of a 2-port memory as shown in FIG. It is a thing.

As shown in FIG. 4A, the memory chip used in this embodiment has the same 32-bit width as the data width of the CPU (data width of the data bus of the CPU bus 1), but one word 16 bits of the upper screen and 16 bits of the lower screen are included in (in 32 bits), and 16-bit data positions are alternately stored in units of 1 word address (4 byte address). .. FIG. 4B shows a data image of the serial output port in the state of FIG. FIG. 5 is a diagram for explaining the operation when the CPU makes a read / write access (random access) to the frame memory 8 via the CPU bus 1.

Next, the operation at the time of random access in the frame circuit of FIG. 1 will be described with reference to FIGS. Information in the address bus in the CPU bus 1 (random access address) is used to access the upper half of the display screen (here, as shown in FIGS. 2, 3 and 5, if the address is less than 144 × 450). Whether or not to access the lower half (here, as shown in FIG. 2, FIG. 3, and FIG. 5 where the address is 144 × 450 or more) is determined, and the determination signal indicating the determination result is converted into data. The address is output to the circuit 2 and the following addresses are output to the memory blocks 8-1 and 8-2 of the frame memory 8.

First, when the access position of the CPU is within the upper half of the display screen (less than 144 × 450 addresses), the address conversion circuit 3 sets [address / 4 for the memory block 8-1 of the frame memory 8]. ] × 2 address is given, and [address / 4] × 2 + 1 address is given to the memory block 8-2. At this time, the data conversion circuit 2 does not swap the data according to the determination signal output from the address conversion circuit 3 and indicating the access to the upper screen. Therefore C
The PU will access the hatched portion in FIG.

Next, when the access position of the CPU is within the lower half of the display screen (addresses of 144 × 450 or more), the address conversion circuit 3 instructs the memory block 8-1 of the frame memory 8 to [address / 4] × 2 + 1 address,
[Address / 4] × 2 addresses are given to the memory block 8-2. At this time, the data conversion circuit 2 swaps the 32-bit data on the data bus of the CPU bus 1 in units of 16 bits in accordance with the determination signal output from the address conversion circuit 3 and indicating the access to the lower screen, and the upper 16 bits. To the memory block 8-2 and the lower 16 bits are connected to the memory block 8-1. Therefore, the CPU is shown in FIG.
You will access the shaded area. As described above, the positional relationship between the memory chip address and data and the display screen as shown in FIG. 4 is realized.

Next, the operation at the time of display access in the frame circuit of FIG. 1 will be described with reference to FIG. Note that FIG. 6 is a diagram for explaining a case where display data is serially read from the memory blocks 8-1 and 8-2 of FIG. 1 and output to the display device.

First, the display timing of the display device is generated by the display timing control circuit 4, and the display address is generated by the display address generation circuit 5.
The memory timing generation circuit 9 switches the address multiplexer (MUX) 6 at the load timing to the shift register of the serial output port of the frame memory 8 to display the display address generated by the display address generation circuit 5 in the frame memory. Connect to 8. In the case of display, the same address (display address) is input to the memory blocks 8-1 and 8-2 of the frame memory 8.

From the serial output ports of the memory blocks 8-1 and 8-2, the upper side (display data for the upper side screen) 1
6 bits and 16 bits of the lower side (display data for the lower side screen) are simultaneously output, and the relationship between the memory blocks 8-1 and 8-2 and the upper side and the lower side is switched in shift clock units.

Under the timing control of the display timing control circuit 4, the memory timing generation circuit 9 enables the serial output enable SOE0, SOE of the memory block 8-1.
In addition to outputting 1, the serial output enable SOE2 and SOE3 of the memory block 8-2 are output, and the memory output is controlled so that the order is the same as the serial latch data of FIG. Further, the display timing control circuit 4 controls the two latch circuits 11 by the latch clocks CLK2 and CLK3, and the memory block 8-of the frame memory 8-
The serial latch data as shown in FIG. 6 from 1, 8-2 are distributed to the upper 8 bits nU and the lower 8 bits nL corresponding to the same nU, and are latched alternately by the two latch circuits 11. Then, the display timing control circuit 4 transfers the content of the latch circuit 11 to the data input / output port 10 by the clock CLK1 and outputs it to the display device.

The display timing control circuit 4 sends data nU, nL from the data input / output port 10 to the display device.
Is output, the next upper and lower 8 bits (n + 1) U,
(N + 1) L is clocked twice (latch clock CLK
2, CLK3).

The output data control from the frame memory 8 to the display device is not limited to the above embodiment. For example, all 16 bits (8 bits x 2) output from the memory block 8-1 and 16 bits (8 bits x 2) output from the memory block 8-2, 32 bits in total, are input, and the upper 16 Bit and bottom 1
It is also possible to select 6 bits and simultaneously latch them to the data input / output port 10.

In the above embodiment, the display device is a liquid crystal display device.
It is similarly applicable to flat display devices such as plasma displays and EL displays.

[0041]

As described in detail above, according to the present invention,
The image 2-port memory can be used as a frame memory for a display device which is divided into upper and lower parts and inputs display data at the same time. Therefore, read / write access (random access) and display access can be simultaneously performed. Therefore, the display information can be drawn at high speed. Moreover, since the display data port of the two-port memory can output data at high speed, it is possible to configure the display device to have an appropriate bit width, thereby eliminating waste of memory and reducing the mounting space. Can be made smaller.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a frame memory circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between screen images and addresses stored in a frame memory 8 of FIG.

FIG. 3 is a diagram showing a relationship between an address and a display position when viewed from a CPU that reads / writes the frame memory 8 in FIG.

FIG. 4 is a diagram showing a relationship between an address and data of a 2-port memory chip itself constituting the frame memory 8 of FIG. 1 and a display position.

5 is a diagram for explaining an operation at the time of read / write access (random access) in the frame memory circuit of FIG.

6 is a diagram for explaining an operation at the time of display access in the frame memory circuit of FIG.

FIG. 7 is a diagram for explaining a method in which a display screen is vertically divided into two, and upper data and lower data are simultaneously input and displayed.

FIG. 8 is a diagram showing a conventional frame memory configuration for storing display information displayed on a screen divided into two.

[Explanation of symbols]

1 ... CPU bus, 2 ... Data conversion circuit (read / write data conversion circuit), 3 ... Address conversion circuit (read / write address conversion circuit), 4 ... Display timing control circuit, 5 ... Display address generation circuit, 6 ... Address Multiplexer (MUX), 7 ... Address multiplexer (ro
w / col MUX), 8 ... Frame memory, 8-1, 8
-2 ... memory block, 9 ... memory timing generation circuit,
10 ... Data input / output port, 11 ... Latch circuit.

Claims (1)

[Claims] 1. A frame memory circuit applied to a display device in which a display screen is vertically divided into two, and horizontal parallel data is simultaneously input and displayed for each of the upper and lower screens, and display information of the display device is stored. A frame memory with a 2-port memory for the purpose of being composed of two memory blocks having a bit width of the interface of the display device or an integer multiple thereof, and at least the least significant bit of the address of each memory block is independent. The frame memory and the random access address
A read / write address conversion circuit that distributes the data to one memory block and controls the least significant bit of the address of each memory block depending on whether the position on the screen to access is on the upper side or the lower side, and the random access data for the two memory blocks. A read / write data conversion circuit that divides the data width into two when connecting to, and connects the data divided into two with or without swapping depending on whether the position on the screen to be accessed is on the upper side or the lower side. A display address generating circuit for scanning the divided screen, a read / write address output by the read / write address converting circuit, and a display address output by the display address generating circuit for switching the frame. Address multiplexer that outputs to memory block of memory The upper and lower screen data output simultaneously from the output data port of the frame memory is divided into two by the data width and swapped or not swapped according to the least significant bit of the display address. A frame data memory circuit comprising: a display data conversion circuit for delivering the data to a screen data output port.