JPS636681A - Image memory control device - Google Patents

Abstract

PURPOSE:To improve the writing efficiency of data by writing drawn data in al addresses of one picture element in one data writing cycle. CONSTITUTION:Address data for writing drawn data in an image memory 111 are outputted from a microprocessor 12. The lower 8 bits of the address data specify row addresses and the upper 8 bits specify line addresses. The line address data and row address data are applied to the memory 111 through an address switching circuit 14. The circuit 14 supplies the address data to the memory 111 as they are in the 1st writing mode, and in the 2nd writing mode, changes the value of a prescribed bit in the row address data. Consequently, all the row addresses in one picture element on a reference screen can be specified only in one data writing cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an image memory control device that controls writing of drawing data to an image memory.

(Prior Art) In image communication systems such as Videotex systems, in recent years, efforts have been made to increase pixel density in order to improve screen quality. For example, in the Videotex system, a high-density screen is being considered that has twice the pixel density of an existing screen (hereinafter referred to as a standard screen) in both column and row directions.

By the way, when considering the coexistence of such a high-density screen and the above-mentioned standard screen, an image display device that can display both screens is required.

Data writing in such an image display device is
This will be explained with reference to the figures. FIG. 12 shows the screen configuration of the Videotex system. In the figure, dl and d2 are pixels (logical pixels) of the high-density screen and the standard screen, respectively. In the illustrated case, the size X2 of the pixel d2 in the column and row directions. Y2 is the size X1.Y2 of the pixel d1 in the column direction and the row direction. Y
It is twice l.

The pixel d1 of the high-density screen defined by Yl and Xl is
Usually set to physical pixel size. Therefore, when writing data to the high-density screen d1, it is sufficient to write the sent logical pixel data as is into the image memory. On the other hand, when writing data to a standard screen, the size of pixel d2 in the column direction x 1 is twice the size of that of a high-density screen, so first, the drawing data sent is doubled in the column direction. It is necessary to Next, the microprocessor writes the enlarged drawing data into two physical pixels in the horizontal line above each pixel. Finally, the drawing data enlarged by the microprocessor is written into two physical pixels in the lower horizontal line.

However, with this data writing method, compared to writing drawing data using a device dedicated to standard screens, the data transfer processing in the microprocessor is doubled, and data enlargement processing is also required. This takes more time than writing data using a dedicated device. As a result, when the drawing data is sent at a high speed, the writing speed of the drawing data is slower than the transfer speed of the drawing data, and real-time data writing cannot be performed.

(Problems to be Solved by the Invention) As stated above, in image display devices capable of displaying a high-density screen and a standard screen, conventionally, compared to devices dedicated to the standard screen, data writing for the standard screen has been performed more frequently. There was a problem that it took a long time.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image memory control device that can quickly write data for a standard screen even if the image display device is capable of displaying a high-density screen and a standard screen.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides an image memory that can access a plurality of column addresses in one data writing cycle, and an image memory that can access a plurality of column addresses in one data writing cycle. A means is provided for updating all column addresses within one pixel in a cycle.

(Function) According to the above configuration, one
Since drawing data can be written to all addresses within a pixel, data writing efficiency can be improved.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of one embodiment.

In the figure, 11 is a memory circuit. The image memory 111 constituting this memory circuit 11 is a dynamic RAM that has a so-called page mode function that allows column addresses to be accessed multiple times in one data write cycle.
It is. Further, this image memory 111 is a dual port memory having a 110 port for writing drawing data and a serial port for reading drawing data for image display.

Drawing data DO~ to be written into this image memory 111
D3 is output from the microprocessor 12. These drawing data DO to D3 are used when writing data for a high-density screen (
(hereinafter referred to as the first write mode) is applied to the image memory 111 as is, and when writing data for the standard screen (hereinafter referred to as the second write mode), the data conversion circuit 111
3 and then applied to the image memory 111.

Address data WAO-WA15 for writing the drawing data into the image memory 111 is provided by the microprocessor 1.
Output from 2. This address data WAO~WA1
The lower 8 bits of 5 specify the column address, and the higher 8 bits specify the row address. Row address data WA8~
WA15 and column address data WAO-WA7 are applied to image memory 111 via address switching circuit 14. In the first write mode, the address switching circuit 14 supplies the address data as is to the image memory 111, and in the second write mode, as will be described in detail later, changes the value of a predetermined bit of the column address data WAO to WA7. By doing this, all column addresses within one pixel on a single screen are specified in one data write cycle.

Note that 15 is a timing generation circuit that generates various timing signals for data writing.

Further, 16 is a display timing generation circuit that generates various timing signals for reading drawing data from the image memory 111 for image display.

Here, the configuration and operation of FIG. 1 will be explained in more detail with reference to FIGS. 2 to 11.

First, the operation of the address switching circuit 14 will be explained.

In terms of display configuration, the image memory 111 has 512 dots in both horizontal and vertical directions, as shown in FIG. Here, if 4 bits of physical pixels are associated with a horizontal address, 128 addresses are required in the horizontal direction.

Now assume that column addresses are taken in the horizontal direction and row addresses are taken in the vertical direction. As mentioned above, since the row address data is 8 bits, 256 row addresses are specified in units of 2 lines. Furthermore, since the column address data is also 8 bits, 256 column addresses within 2 lines are specified.

Here, the horizontal coordinates of the first line and the second line are equal 2
Looking at the two column addresses, the column address on the second line is the column address on the first line plus 128. Therefore, by setting rOJ to the most significant bit of column address data, the column address of the first line can be specified, and by setting [1], the column address of the second line can be specified. This results in 1
After writing the drawing data to a predetermined column address of the line, the most significant bit WA of the column address data WAO-WA7
By setting "1" to 7, the same drawing data can be written to the column address of the second line having the same horizontal coordinate.

Further, by changing the least significant bit WAO of the column address data WA, O to WA7, two consecutive column addresses in the horizontal direction can be specified. In other words, W
If you set "○" in AO, you can specify an even number address and "
1”, you can specify an odd address. Thereby, by setting "1" to the least significant bit after writing drawing data to an even address, the same drawing data can be written to consecutive odd addresses in the horizontal direction.

From the above, bit W of column address data WAO to WA7
By switching the combination of values of AO and WA7, four column addresses can be specified as shown in FIG.

Now, if we consider the high-density screen and the standard screen as shown in FIG. Row address data WA8 to WA15 for specifying the address as a row is output. On the other hand, in the first write mode, column address data WAO-WA7 specifying a column address for each pixel on a high-density screen is output.

On the other hand, the column address data W in the second write mode
The AO-WA 7 outputs one predetermined column address among the four column addresses included in one pixel of the standard screen, for example, one specifying an even-numbered address of the upper line. Such column address data WAO-WA
The address switching circuit 14 shown in FIG.
Column address data WAO~W specifying two column addresses
Output A7. This can be explained as follows according to FIG. Bits WA7 and WAO of column address data ~VAO~WA7 output from microprocessor 12 are supplied to OR circuits 141 and 142, respectively. Each OR circuit 141 and 142 further receives a signal AC from the pulse generation circuit 151 of the write timing generation circuit 15.
HG1. ACHG2 is supplied. In the first write mode, the signal ACHGI.

Both ACHG2 are always 0. Therefore, in this case, bit WA7. The WAO data passes through OR circuits 141 and 142 as is, and is sent to address buffer 1.
43. On the other hand, in the second write mode, the signals ACH01°AC)-IG2 are switched as shown in the table.

This signal ACHG1. As the value of ACHG2 changes, the output values of OR circuits 141 and 142 change, and four column addresses corresponding to one logical pixel are designated.

The above address data WA○ to WA7 and WA-W
Al 5 passes through address buffers 143 and 144 in accordance with gate signals cOLW and ROWW output from pulse generation circuit 151, respectively, and is stored in image memory 1.
given to 11.

Next, data writing operations for the high-density screen and the standard screen will be explained with reference to FIGS. 4 and 5, respectively.

In the first write mode, as shown in FIG.
HG1. ACHG2 is always O. Further, the column address strobe signal CA SW is output only once.

Therefore, in this case, one
Data is written only once.

In the second write mode, as shown in FIG. 5, the column address strobe signal CA
SW is output 4 times. The signal ACHG1 becomes 1 at the first and third output timings of the column address strobe signal CASW, and at the 012th and fourth output timings. - On the other hand, the signal ΔCHG2 becomes 0 at the first and second output timings, and 1 at the third and last output timings. Therefore, in one data write cycle, four column addresses corresponding to one logical pixel on the standard screen are written as follows: 1st line even address → 2nd line even address → 1st line odd address → 2nd line Specified in order of odd addresses.

Note that the pulse generation circuit 151 receives the various signals RA mentioned above.
S W , CA S W , ROW W , G
OL M.

ACHG1, ACHG2, and write pulses ~1 are generated according to the basic clock CP, a mode designation signal supplied from the microprocessor 12, and a write signal WR. Signal WMOD
When 1 and WMOD2 are both O, the first write mode is designated, and when both are 1, the second write mode is designated. Signal WMOD1 is O, WMOD2
When is 1, as shown in FIG. 6, a mode (hereinafter referred to as (referred to as the third mode) is set. In other words, in this embodiment, in addition to the second write mode in which data is written in both horizontal and vertical directions, a third mode in which data is written only in the vertical direction can be set as the standard screen write mode. It looks like this. These two modes are as described above.
11 in page mode.

In this case, pulse generation circuit 151 provides wait signal WAIT to microprocessor 12 to extend the data write cycle period over that of the first write mode.

Next, the operation of the data conversion circuit 13 will be set.

4-bit drawing data Do-D3 outputted from the microprocessor 12 is given to a data selector 131 and a data buffer 132.

The data selector 131 selects when the signal AC)-IG2 is O
When , the lower 2 bits of input data are D○.

Dl respectively output Y1. Y2 is selected, and when it is 1, the upper 2 bits are output respectively as Y1. Select as Y2. Output Y1 is a 4-bit input data buffer 13.
The output Y2 is given as the lower two bits of Y3, and the output Y2 is given as the upper two bits of data. Therefore, as shown in FIG. 8, when the signal ACHG2 is O, the lower 2 bits of the drawing data are converted to 4-bit data, and when it is 1,
The upper 2 bits are expanded to 4 bits of data.

This converted drawing data is the mode designation signal WM
When ODI is 1, that is, in the second write mode, the data is applied to the image memory 111 through the data buffer 133. - On the other hand, if the signal WMOD1 is ○, that is,
In the case of write mode 1.3, the drawing data output from the microprocessor 12 is stored in the data buffer 132.
It is applied to the image memory 111 through the.

Although the main parts of one embodiment of the present invention have been described above, FIG. 1 also shows a configuration for reading drawing data from the image memory 111 for image display. Therefore, this reading configuration will be briefly explained below. Address data RAO to RΔ15 for this readout is generated by the display timing generation circuit 16 and applied to the address selector 112 of the memory circuit 11. This address selector 11
2 is the write address data W according to the switching signal REF output from the display timing generation circuit 16.
AO to WA15 and read address data RA
Either one of the O-RAs 15 is given to the image memory 111. Also, an address strobe signal RASR for loading the address data RAO to RA15 into the image memory 111.

CASR is also generated by the display timing generation circuit 16 and provided to the memory control l signal selector 152. This selector 152 also outputs the write address strobe signals RAS~V, CASli and the successive write address strobe signals RASR, CASR in accordance with the switching signal REF.
Either one of them is given to the image memory 111. The drawing data read from the address specified by the address data RASR and CASR for successive printing is processed by the load pulse L output from the display timing generation circuit 16.
D is loaded into the parallel/serial conversion circuit 113. This data is parallel data for several pixels on a high-density screen, and is converted into serial data for each pixel in accordance with the basic clock CP.

Here, the relationship between data writing to the image memory 111 and data reading from this memory 111 will be explained.

For example, the image memory 111 is connected to a RAM boat consisting of a memory cell array of 256 pits (64 words x 4 bits) and 256 . When configured with a dynamic RAM having a serial port consisting of a word x 4 bit data register, 256 words x 4 bits of data are transferred from a 64 word x 4 bit memory cell array to the data register as shown in Figure 8. Due to the operation called data transfer cycle, data transfer processing only needs to be performed once every two horizontal scans for display. Therefore, when data transfer processing is performed once, the time until the next data transfer cycle can be spent on refreshing and writing. The relationship between the display period and the write cycle is shown in FIG. 9, but it can be set anywhere other than the write cycle and refresh period. Therefore, setting the write cycle period is very easy.

The drawing data transferred to the 256 word x 4 bit data register as described above is read out in 4 bits in parallel according to the lock SC as shown in FIG. This readout output is loaded into the parallel/serial conversion circuit 113 according to the load pulse LD, and this circuit 1
13, one bit at a time is serially read out in accordance with the basic clock CP.

As described above, in this embodiment, an image memory 111 that can be accessed in page mode is provided, and a column address is accessed four times in one data write cycle. Specifically, the upper and lower even addresses are accessed in the first two access timings, and the upper and lower odd addresses are accessed in the latter two access timings.

With this configuration, it is possible to write data for one logical pixel on the standard screen in one data writing cycle, so as is clear from FIG. You can write drawing data with Therefore, even if the data transfer speed increases, real-time data writing can be performed.

Further, in this embodiment, in order to write data for one pixel, the microprocessor 12 writes four pixels corresponding to one logical pixel.
It is only necessary to output one of the two column addresses. Therefore, according to this embodiment, the address generation process in the microprocessor 12 can be reduced to 1/4 of the conventional one.

In addition, in the above explanation, the case where 4 physical pixel dots correspond to one column address was explained, but when 1 physical pixel dot corresponds to one column address, 1 bit corresponds to 4 dots. Since it is sufficient to write data to four addresses, the data conversion circuit 13 described above is unnecessary.

Furthermore, although a memory with a built-in data register has been described as the image memory 111, a register capable of storing display drawing data for the page mode access time in each data write cycle may be connected to the memory.

Also, updating column address data is not an OR circuit, but
It may also be done using an F-Sifluous OR circuit.

Furthermore, the present invention can be applied to data writing in systems other than systems in which the number of logical pixels on a high-density screen within one logical pixel on a standard screen is two in either the horizontal or vertical direction. Of course.

[Effects of the Invention] According to the present invention, in an image memory 1i11@ device that is used for a plurality of screens having different pixel sizes, it is possible to improve the data writing efficiency for screens having large pixel sizes.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG.
11 are diagrams for explaining the operation of FIG. 1, and FIG. 12 is a diagram for explaining the conventional problem. 11...Memory times, 12...Microprocessor. 13...Data expansion circuit, 14...Address switching circuit, 15...Write timing generation circuit, 111...
...Image memory. Applicant's representative Patent attorney Takehiko Suzubi Woodworking direction diagram 2. Figure 3 (+l second mode (WMQD=1) (2) first mode
．． Third mode (WMOD=O) Fig. 7 ゛llll Fig. 8

Claims (2)

[Claims] (1) An image memory whose column address can be accessed multiple times in one data write cycle, and a second pixel unit that includes a plurality of first pixels in each of the row and column directions. a row address generating means for generating row address data for writing drawing data; and generating column address data for the first pixel located at a predetermined position on the second pixel for each second pixel. By switching the values of the lower and upper predetermined bits of the column address data output from the column address generating means in each data write cycle, the corresponding second pixel is generated in the data write cycle. address data switching means that generates all column address data corresponding to the column address data; a drawing data generating means that generates drawing data; An image memory control device comprising address data and data writing means for writing to an address designated by the column address data output from the address data switching means. (2) An image memory whose column address can be accessed multiple times in one data write cycle, and a second pixel unit that includes a plurality of first pixels in the row direction and column direction, respectively, to the image memory. a row address generating means for generating row address data for writing drawing data; and generating column address data for the first pixel located at a predetermined position on the second pixel for each second pixel. By switching the values of the lower and upper predetermined bits of the column address data output from the column address generating means in each data write cycle, the corresponding second pixel is generated in the data write cycle. address data switching means for generating all the column address data corresponding to the first pixel; a drawing data generating means for generating drawing data for the first pixel; and drawing data output from the drawing data generating means for the second pixel. a drawing data converting means for converting the drawing data for the second pixel output from the drawing data converting means into the row address data output from the row address generating means and the address data. An image memory control device comprising data writing means for writing to an address specified by column address data output from the means.