JPS60124764A - Direct memory access controller - Google Patents

Abstract

PURPOSE:To attain a program by connecting plural registers to the input side of a full adder, feeding back its output and generating a read address of a picture data so as to attain high speed transfer of a picture data. CONSTITUTION:A base address register 2 and an address offset register 9 or the like are connected to a 3-input full adder 3 at column synchronism, that is, at read or write of a picture in lateral direction, a base address register 2 and an addess off-set register 9, etc. are connected and respective data are inputted from them. Moreover, data is inputted respectively from the register 2 and a WIDTH register 7 at line synchronism, that is, at longitudinal read or write of a picture data. The output is fed back in this case and stored newly to the register 2, data from each register or the like are added to the full adder 3 to generate the real address of the picture data. Moreover, the data is set programmably to the register 7, the transfer of picture data is quickened and also made programmable.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a direct memory access control device in an image memory device or the like.

BACKGROUND ART In recent years, image processing systems have been proposed or provided that digitize image data read by an image league or the like, store it in a semiconductor memory or magnetic memory, and display or print it out as needed. There is.

One of the features of this type of system is that the images are stored digitally, so they can be processed electronically.
One advantage is that partial extraction, rewriting, and positional movement can be performed relatively freely.

However, in such a system, although software has a high degree of freedom in executing the above-mentioned processing, it has the disadvantage that the data transfer speed is slow. In other words, software processing means data transfer by a program, and depending on the program, any complicated form of data transfer can be executed. However, in this software processing, it is necessary to process the program code in the CPU for 7 hours, and it is necessary to take the data into the CPU once and then transfer it to the destination. Data transfer takes time. Therefore, it is not practical in image processing systems that have high resolution, a large number of pixels, and a large amount of data.

For this reason, with regard to data transfer between external memory and signal input/output devices, so-called direct memory access (hereinafter referred to as DMA) control methods and devices that directly exchange data without going through the CPU have been developed. Many have been proposed or provided in the past.

SUMMARY OF THE INVENTION An object of the present invention is to provide a DMA control device that can speed up the transfer of image data and is programmable.

On the input side of the ya-fusa full adder, there is a first register that specifies a predetermined storage area width of the image data area of the memory that stores image data, and the relationship between the area width and the area width set in this first register. A second register that specifies a specific address of a specific image area to be processed is connected to a set of memory addresses to be processed, and the output of the full adder is fed back to the input side of the second register, and the By adding an offset address to the other input side of the full adder to generate a real address of image data, it is possible to perform image editing processing at high speed and with a large degree of freedom.

Amatsuta mawashi An embodiment of the present invention will be described below.

FIG. 1 shows the configuration of an image editing processing system to which the present invention is applied. In this image editing processing system,
Image data read by Image League can be transferred in four directions: a) from the Image League interface to the image memory; b) from the image memory to the printer interface; c) between the image memory and the image display device or keyboard; d) within the image memory. data transfer is performed. a) is image data input, b) is image printing, C) is image display, and d) is data transfer for image editing.

FIG. 2 shows a memory map of the image memory, where W indicates the width of the memory plane. The column count of the image data area IM is the number of columns included in one line corresponding to the pixel columns in the horizontal direction of the image. The line count of the image data area IM is the number of lines mentioned above, and corresponds to the length of the image in the vertical direction. The base address is the address of the most advanced data in the image data area IWI.

Figure 3 shows the image editing D that transfers the image data mentioned above.
This shows the configuration of the MA circuit, and the circuit in Figure 3 is the first MA circuit.
This corresponds to the DMA circuit and image memory shown in the figure.

Image Memo January is composed of a large-capacity memory array such as a dynamic RAM, and has a data width in units of nibble, byte, word, etc. that can be accessed by an ordinary microprocessor. The base address register 2 holds the address of the most advanced data among the image data stored in the image memory 1, that is, the base address shown in FIG. Every time a transfer is completed, data in the WIDTH register, which will be described later, is added. Therefore, the address data held by the base address register 2 changes every time one line of data transfer is completed.

The base address register 2 has two input ports, and each port can be switched. A base address is programmably set in this base address register 2 by a CPU (not shown), so that a plurality of images can be stored in the image memory.

At the time of column synchronization, that is, when reading or writing image data in the horizontal direction, the three-person Kaful Agoo 3 adds the respective data of the base address register 2, the column counter 6, which will be described later, and the address offset register 9, and performs DMA processing.
Generate real address data for In addition, during line synchronization, that is, when reading or writing image data in the vertical direction, the three-person Kaful Agoo 3 adds the respective data of the base address register 2 and the WIDTH register 7, and transfers this added data to the base address register 2. hold it. Each of the three input ports of the three-person Kafuru Agoo 3 can be independently enabled or disabled.

The address bus buffer 4 switches whether or not to output the real address data from the three-person Kafuru Agu 3 to the address bus 14. The column count register 5 holds column count data that defines the width of image data on the image memory 1. The column counter 6 counts the address offset, which is the difference between the column count data and the column count for every 7 dressings.

It is preferable that the column counter 6 has an internal comparator and has a function of comparing the count value and the set value and stopping counting when they become equal.

WIDTH defines the memory plane width of the image memory, indicated by W in FIG. This WIDT
Memory plane width data is programmably set in the H-renostuff by the CPU.

In this way, since the memory plane width can be arbitrarily set by the CPU, memory can be used effectively.

The multiplexer 8 selects the data of the column counter 6 during column synchronization, and selects the data of the WIDTH register 7 during line synchronization, and inputs the data to the full adder 3, respectively. As shown in FIG. 4, the address offset entreno star 9 holds an offset address that is the address difference between a transfer source and a transfer destination when data is transferred within the image memory 1.

The P/S controller 10 converts parallel data into serial data. The S/P transistor 11 converts serial data into parallel data. data latch 1
2 is parallel data from the S/P shift register 11, which is latched at the time of shifting the desired image, and further stored in the image memory 1.
This data is output to data bus 15 for transfer to. The shift clock generator 13 is connected to the P/S shift register 10. A timing pulse is given to the S/P shift register 11 and data latch 12. P/' mentioned above
S shift register 10. S/P shift register 11. Data latch 12 and shift clock generator-1
3 constitutes a data shifter 16.

A method of addressing image data in the above-mentioned DMA control device will be explained with reference to the memory map shown in FIG.

Scanning of line L1 is started from the base address set in base address register 2 by CPU, and when addressing of column count is completed, scanning of line L1 is started from the base address set in base address register 2 by CPU.
Move on to the second scan. In this case, the base address of line L2 is determined by adding the memory plane width W held in the WIDTH register 7 to the address of the end data of line L1, and scanning of line L2 is started. Thereafter, line L3. L4... is scanned.

Now, the data in the base address register 2 is input to the three-person Kafuru Agu 3. The data of the multiplexer 8 and the address offset register 9 are further input to the three-person Kafuru Agoo 3.

Then, the output of the three-person Kafuru Agu 3 is output to the address bus 14 connected to the image memory 1 via the address bus buffer 74, and is also output to the base address register 2.
The signal is input via the feedback line 13.

The purpose of providing this feedback line 13 is that, as mentioned above, the data in the WIDTH register 7 is added to the data in the base address register 2 at the time of line synchronization, that is, every time data transfer of one line is completed, and this added value is used as the base address register. The purpose is to reset the address register 2.

This process corresponds to generating addresses of lines vertically one line below the base address on the memory plane shown in FIG. 2.

FIG. 5 shows a time chart when image data is transferred within the image memory 1.

The line synchronization signal is a pulse that is output to synchronize data transfer every time a line of image data on the memory plane is scanned. Otherwise, the printer interface outputs the respective outputs in the DMA circuit.

A select signal 8a is input to the multiplexer 8 in response to this line synchronization signal, and the multiplexer t81. tWI
DTH and select the data WIDTH of E;l'7 and input it to the 3 person Kaful Agu 3. Furthermore, the strobe signal 2a is input to the base address register 2, and the base address (N), which is the data of the base address register 2 at this time, is input to the three-person kuffle Agu 3, and the three-person kuffle Agu 3 receives this base address (N). ) and WIDTH
The data Wr D T H of the register 7 is added, and the base address (N+1) which is the result of this addition is output.

This base address (N+1> is output to the address bus 14 via the address bus buffer 74, and
It is set in the base address register 2 via the feedback loop 13.

Furthermore, a strobe signal 6a is input to the column counter 6 in response to this line synchronization signal, and the column count data held in the column count register 5 is set in the column counter 6. This column counter 6 gives a horizontal address offset value from the base address shown in FIG.
It is incremented each time a word) is accessed. That is, in FIG. 4, the column synchronization signal that is generated every time one byte of data is transferred in response to the line synchronization signal is used as a tally for the column counter 6, and when one byte of data transfer is completed, the column counter 6 only counts 1. will be added. At this time, the multiplexer 8 outputs the data of the column counter 6, and
adds the total input address from the base address register 2 and the column count (n) from the column counter 6. Here, n indicates that it corresponds to the n-th data from the left end of the image data in FIG. The added value of this base address and the column count (,) is the real address of the image data on the image memory 1.

The three-person Kaful Agoo 3 adds the result of the addition of this base address and column count (n) to the address bus buffer 4.
is output to the address bus 14 via the base address register 2 via the feedback loop 13.
Set to .

As described above, one of the transfer destination and transfer source addresses in data transfer has been determined, but in the case of data transfer within the image memory, it is necessary to generate the other address as well. However, in order to determine this other address, one more circuit similar to that described above may be provided, but in this embodiment, this is efficiently done by the following method.

That is, as shown in FIG. 4, the offset address, that is, the difference between the addresses of the transfer source and the transfer destination may be always constant. Then, this constant offset address is held in the address offset register 9,
The offset address of this offset register 9 is input to the three-manpower full adder 3 when reading and writing image data. The output of the three-man power full adder 3 at this time becomes the other address. This other address is output to the address bus 14 via the address bus buffer 4 and is input to the base address register 2 via the feedback line 13. Furthermore, in cases other than transfer within the image memory, when the transfer destination or transfer source is added to the address bus as an I10 device, the fixed address of this I10 device may be held in the address offset register 9.

By the way, in the double process, data can only be transferred in byte units. However, when editing images, it is desirable to be able to crop and transfer both vertically and horizontally in bits, and this requires two bits on the data bus.
This is possible by providing a data shifter consisting of two shift registers, a data latch, a shift clock, and a shift generator. That is, in FIG. 3, the data shifter 16 transfers 1 byte of data read from the image memory 1 to the shift clock CLK from the shift clock generator 13 in the P/S shift register 10.
This serial gate is converted into serial data in synchronization with the S/P shift register 11. Then, the lower three bits of column count register 5) CCO to CC2
The shift clock DCL is output from the shift clock generator 13 according to the number of shift bits set by the data.
When K is output, byte data shifted by a desired number of bits from the S/P shift register 11 is latched into the data latch 12. By transferring the data in the data latch 12 to the transfer destination, data transfer can be performed in bit units. This sequence, as shown in FIG.
Shift processing is performed in accordance with the enable state of , and data is written into the bus by signal bus WR/ in accordance with this shift processing. Note that the shift clock generator 13 is a circuit that generates timing pulses for performing the above-described shift processing, and it is desirable that its processing speed be approximately the same as the setup time of the image memory 1. By doing so, efficient, ie, high-speed data transfer can be performed without extending the RAM cycle time. Specifically, this can be achieved by increasing the frequency of the shift clock.

FIG. 6 shows the configuration of the data shifter 16 described above in detail, and FIG. 7 shows the signal states of the main parts of this data shifter 16.

Lower 3 bits CCO to CC of column count register 5
2 is input to the presettable counter 21. As shown in FIG. 7, the sequence starts when the signal RD/ rises, and the shift clock C is applied to the CLK line 23.
Eight shift pulses of LK are output from the shift clock generator 13. Then, the lower three bits CC0 of the column count register 5 are sent to the presettable counter 21 constituting the shift clock generator 13.
- The shift clock DCLK is output from the presettable counter 21 at a timing corresponding to the number of shift bits set by CC2, and at the rising edge of this shift clock DCLK, the byte data shifted by the number of shift bits is latched into the data latch 12. .

Management of vertical lines of image data will be explained.

When counting the number of lines of image data, it may not be necessary to provide a particular register. In other words, the processing in the vertical direction, that is, the sub-scanning direction, of the image is sufficiently slower than the processing in the horizontal direction, that is, the main scanning direction, so that it can be managed by software via the CPU. Specifically, the above-mentioned line synchronization signal is input to the counter, and the CPU monitors this count value during DMA transfer.
D M at any count value, that is, any length in the vertical direction
A transfer can be stopped. Of course, it is also possible to perform the above processing using hardware.
FIG. 8 shows the hardware configuration for performing this processing.

Data on the number of lines is set from the CPU 30 to the presettable counter 31, and the presettable counter 31
When the line synchronization signal is counted and the count value becomes equal to the set value, an interrupt is issued to the CPU 30.

As explained above, in the present invention, the input side of the full adder includes a first register that specifies a predetermined storage area width of an image data area of a memory that stores image data;
A second register that specifies a specific address of a specific image area to be processed is connected to a series of memory addresses determined by the relationship with the area width set in this first register, and the full adder is Since the output is fed back to the input side of the second register to generate the real address, it is possible to speed up the data transfer by using hardware, and the width of the image memory can be set arbitrarily, so the memory size can be reduced. Usage efficiency can be increased, image areas of any size can be set at any location within the set memory plane, multiple images can be stored, and data can be transferred within the image memory.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the configuration of an image editing processing system, Fig. 2 is a diagram showing a memory map of the image memory, Fig. 3 is a block diagram showing an embodiment of the present invention, and Fig. 1 is a data transfer within the memory. FIG. 5 is a time chart when data is transferred in the DMA control device of the present invention, FIG. 6 is a circuit diagram showing the configuration of the data shifter, and FIG. 7 is a data transfer diagram. FIG. 8 is a time chart showing the states of signals in the main parts of the shifter. FIG. 8 is a diagram showing a circuit for managing lines of image data. 1... Image memory, 2... Base address register, 3... 3 person cuffle adder, 5... Column count register, 6... Column counter, 7...'vV
IDTH register, 8...Multiplexer, 9
...Address offset register, 10...P/S
Shift register, 11...S/P shift register, 1
2...Data latch, 13...Shift clock generator-114...Address bus, 15...Data bus. Patent Applicant Minolta Camera Co., Ltd. Agent Patent Attorney Seishaku Sogai 2 RD/Figure 6 Figure 7 Figure 8 LINE = 4th term

Claims (3)

[Claims] (1) A first register that specifies a predetermined storage area width of an image data area of a memory that stores image data, and a series of memory addresses determined by the relationship between the area width set in this first register. On the other hand, a second register specifies a specific address of a specific image area to be processed, and a column of one line corresponding to a horizontal pixel column of the image in the specific image area to be processed. a third register for specifying the number of data; a line synchronization signal generating means for generating a line synchronization signal that defines the timing of processing each line of data in the specific image area to be processed; Column synchronization signal generation means for generating a column synchronization signal that defines timing;
A counter that counts the column synchronization signal with a count value equal to the value set in the third register each time the line synchronization signal is output, and the output of this counter and the output of the first register. and an adder that adds the output of the second register and the output of the signal selection means, each time the counting operation of the counter is completed, the signal selection means The output of the first register is selected and input to the adder, and the output of the adder is fed back to the second register to rewrite the contents of the second register. A direct memory access control device characterized in that an address of the memory to be processed is specified by the output of the device. (2) The device according to claim 1, which provides the adder with the output of an address offset register that holds an offset address that is the difference address between the transfer source address and the transfer destination register in data transfer. . (3) a first shift register that converts parallel data from the memory into serial data; a second shift register that converts serial data from the first shift register into parallel data; A data shifter that has a data latch that updates data from a register, and a synchronization signal output means that outputs a synchronization signal in response to the output of the third register, and transfers data in response to the synchronization signal. An apparatus as claimed in claim 1, comprising: