JPS5785162A - Picture memory access control system - Google Patents

Picture memory access control system

Info

Publication number
JPS5785162A
JPS5785162A JP16046480A JP16046480A JPS5785162A JP S5785162 A JPS5785162 A JP S5785162A JP 16046480 A JP16046480 A JP 16046480A JP 16046480 A JP16046480 A JP 16046480A JP S5785162 A JPS5785162 A JP S5785162A
Authority
JP
Japan
Prior art keywords
register
signal
picture
zero
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16046480A
Other languages
Japanese (ja)
Inventor
Yukichi Ikuta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16046480A priority Critical patent/JPS5785162A/en
Publication of JPS5785162A publication Critical patent/JPS5785162A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To execute the access to a picture memory at a high speed, by updating a value of a register in accordance with an output signal of a zero-checking circuit, continuously adding ''1'' to this value, and generating a memory address in order. CONSTITUTION:A picture memory access control device 3 is started by a picture memory access request 8, outputs a control signal 50 by use of an X zero signal 27 and a Y zero signal 31, and executes an access control to a partial picture being in a picture memory device 1. In case the partial picture is accessed in the lateral direction, a register D and a register F are set to a register E and a register G, respectively. Subsequently, +1 is repeated, updating a register A, an address is generated in order, and the memory is accessed. When an E-counter is subtracted by synchronizing with said operations, E becomes zero, and the X zero signal rises. By this X zero signal, B+C of registers are executed and its output is set to both A and B. Subsequently, D is set to E, and subtraction of a G-counter is executed. When it is repeated, both the signal 27 and the signal 31 rise at the same time, and the access to the partial access picture is finished.
JP16046480A 1980-11-14 1980-11-14 Picture memory access control system Pending JPS5785162A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16046480A JPS5785162A (en) 1980-11-14 1980-11-14 Picture memory access control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16046480A JPS5785162A (en) 1980-11-14 1980-11-14 Picture memory access control system

Publications (1)

Publication Number Publication Date
JPS5785162A true JPS5785162A (en) 1982-05-27

Family

ID=15715501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16046480A Pending JPS5785162A (en) 1980-11-14 1980-11-14 Picture memory access control system

Country Status (1)

Country Link
JP (1) JPS5785162A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60124764A (en) * 1983-12-12 1985-07-03 Minolta Camera Co Ltd Direct memory access controller
JPS62192885A (en) * 1986-02-20 1987-08-24 Fujitsu Ltd Image scanning convertion processing system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60124764A (en) * 1983-12-12 1985-07-03 Minolta Camera Co Ltd Direct memory access controller
JPS62192885A (en) * 1986-02-20 1987-08-24 Fujitsu Ltd Image scanning convertion processing system

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