JPS5731050A - Advance control system for branch instruction - Google Patents
Advance control system for branch instructionInfo
- Publication number
- JPS5731050A JPS5731050A JP10592880A JP10592880A JPS5731050A JP S5731050 A JPS5731050 A JP S5731050A JP 10592880 A JP10592880 A JP 10592880A JP 10592880 A JP10592880 A JP 10592880A JP S5731050 A JPS5731050 A JP S5731050A
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- branch
- advance
- taken
- branch destination
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
- G06F9/3846—Speculative instruction execution using static prediction, e.g. branch taken strategy
Abstract
PURPOSE:To execute a branch instruction at a high speed, by starting to execute a branch destination instruction which has been taken in advance, to a memory device, in case when a branch destination address calculating state, etc. in the effective process of the branch instruction have become definite. CONSTITUTION:When it is detected that a banch instruction exists in instruction buffer registers 1-4, the branch instruction is taken in advance by utilizing a cycle between prescribed cycles. In this case, contents of flags IPF5-8 are inputted to an instruction selecting and generating circuit 15 together with pointers NSIP10-12, an instruction is selected from the instruction buffer through a selector 16, is sent to a decoder 17, and whether it is a branchable instruction or not is analyzed. In the event of being branchable, a branch destination address is calculated through the gap of 2 cycles, and the instruction is fetched to the memory device. In this way, the branch destination instruction is taken in advance at a high speed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10592880A JPS6058489B2 (en) | 1980-07-31 | 1980-07-31 | Branch instruction advance control method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10592880A JPS6058489B2 (en) | 1980-07-31 | 1980-07-31 | Branch instruction advance control method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5731050A true JPS5731050A (en) | 1982-02-19 |
JPS6058489B2 JPS6058489B2 (en) | 1985-12-20 |
Family
ID=14420511
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10592880A Expired JPS6058489B2 (en) | 1980-07-31 | 1980-07-31 | Branch instruction advance control method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6058489B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60105050A (en) * | 1983-11-11 | 1985-06-10 | Fujitsu Ltd | Pipeline control system |
-
1980
- 1980-07-31 JP JP10592880A patent/JPS6058489B2/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60105050A (en) * | 1983-11-11 | 1985-06-10 | Fujitsu Ltd | Pipeline control system |
JPS638492B2 (en) * | 1983-11-11 | 1988-02-23 | Fujitsu Ltd |
Also Published As
Publication number | Publication date |
---|---|
JPS6058489B2 (en) | 1985-12-20 |
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