JPS5729153A - Control system for instruction processing order - Google Patents

Control system for instruction processing order

Info

Publication number
JPS5729153A
JPS5729153A JP10469480A JP10469480A JPS5729153A JP S5729153 A JPS5729153 A JP S5729153A JP 10469480 A JP10469480 A JP 10469480A JP 10469480 A JP10469480 A JP 10469480A JP S5729153 A JPS5729153 A JP S5729153A
Authority
JP
Japan
Prior art keywords
instruction
execution
vacancy
register
registers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10469480A
Other languages
Japanese (ja)
Other versions
JPS6142308B2 (en
Inventor
Tetsuo Okamoto
Shigeaki Okuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10469480A priority Critical patent/JPS5729153A/en
Publication of JPS5729153A publication Critical patent/JPS5729153A/en
Publication of JPS6142308B2 publication Critical patent/JPS6142308B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution

Abstract

PURPOSE:To perform program processing in the shortest time by a data processor which has plural operators, by executing instruction without reference to the order of execution specified by a program. CONSTITUTION:An instruction reception part 7 receives an instruction fetched from a main memory and when execution queuing instruction registers 7-0-7-2 have a vacancy, the instruction is set in an execution queuing instruction register 7-i. An instruction supply determination part 8 checks whether operators corresponding to instructions set in the registers 7-0-7-2 have a vacancy or not and whether the collision between operands occurs or not and when some vacancy is present and no collision occurs, the instruction in the register 7-i is set in an in-execution instruction register 9-m to actuate a corresponding arithmetic pipeline.
JP10469480A 1980-07-29 1980-07-29 Control system for instruction processing order Granted JPS5729153A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10469480A JPS5729153A (en) 1980-07-29 1980-07-29 Control system for instruction processing order

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10469480A JPS5729153A (en) 1980-07-29 1980-07-29 Control system for instruction processing order

Publications (2)

Publication Number Publication Date
JPS5729153A true JPS5729153A (en) 1982-02-17
JPS6142308B2 JPS6142308B2 (en) 1986-09-20

Family

ID=14387577

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10469480A Granted JPS5729153A (en) 1980-07-29 1980-07-29 Control system for instruction processing order

Country Status (1)

Country Link
JP (1) JPS5729153A (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943440A (en) * 1982-09-03 1984-03-10 Toshiba Corp Arithmetic control system
JPS6116335A (en) * 1984-07-02 1986-01-24 Nec Corp Information processor
JPS6188332A (en) * 1984-10-06 1986-05-06 Nec Corp Binary operating circuit
JPH0248732A (en) * 1988-08-11 1990-02-19 Toshiba Corp Micro processor for instruction pipe line system
JPH0391029A (en) * 1989-09-04 1991-04-16 Mitsubishi Electric Corp Data processor
JPH04111127A (en) * 1990-08-31 1992-04-13 Toshiba Corp Arithmetic processor
JPH052484A (en) * 1991-06-24 1993-01-08 Mitsubishi Electric Corp Super scalar processor
EP0605874A1 (en) * 1993-01-08 1994-07-13 International Business Machines Corporation Method and system for increased instruction dispatch efficiency in a superscalar processor system
WO1995016954A1 (en) * 1993-12-15 1995-06-22 Silicon Graphics Inc. Apparatus for processing instruction in computer system
US5615349A (en) * 1990-09-04 1997-03-25 Mitsubishi Denki Kabushiki Kaisha Data processing system capable of execution of plural instructions in parallel
US5745723A (en) * 1989-09-04 1998-04-28 Mitsubishi Denki Kabushiki Kaisha Data processing system capable of execution of plural instructions in parallel
JPH10510146A (en) * 1994-11-21 1998-10-06 ザ ユニバーシティ オブ リーズ Modified proteinase inhibitors
JP2008269067A (en) * 2007-04-17 2008-11-06 Nec Computertechno Ltd Vector processing device

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943440A (en) * 1982-09-03 1984-03-10 Toshiba Corp Arithmetic control system
JPS6116335A (en) * 1984-07-02 1986-01-24 Nec Corp Information processor
JPH0248932B2 (en) * 1984-07-02 1990-10-26 Nippon Electric Co
JPS6188332A (en) * 1984-10-06 1986-05-06 Nec Corp Binary operating circuit
JPH0248732A (en) * 1988-08-11 1990-02-19 Toshiba Corp Micro processor for instruction pipe line system
JPH0391029A (en) * 1989-09-04 1991-04-16 Mitsubishi Electric Corp Data processor
US5812809A (en) * 1989-09-04 1998-09-22 Mitsubishi Denki Kabushiki Kaisha Data processing system capable of execution of plural instructions in parallel
US5745723A (en) * 1989-09-04 1998-04-28 Mitsubishi Denki Kabushiki Kaisha Data processing system capable of execution of plural instructions in parallel
JPH04111127A (en) * 1990-08-31 1992-04-13 Toshiba Corp Arithmetic processor
US5615349A (en) * 1990-09-04 1997-03-25 Mitsubishi Denki Kabushiki Kaisha Data processing system capable of execution of plural instructions in parallel
US6058471A (en) * 1990-09-04 2000-05-02 Mitsubishi Denki Kabushiki Kaisha Data processing system capable of executing groups of instructions in parallel
US6131158A (en) * 1990-09-04 2000-10-10 Mitsubishi Denki Kabushiki Kaisha Data processing system capable of executing groups of instructions, including at least one arithmetic instruction, in parallel
JPH052484A (en) * 1991-06-24 1993-01-08 Mitsubishi Electric Corp Super scalar processor
EP0605874A1 (en) * 1993-01-08 1994-07-13 International Business Machines Corporation Method and system for increased instruction dispatch efficiency in a superscalar processor system
WO1995016954A1 (en) * 1993-12-15 1995-06-22 Silicon Graphics Inc. Apparatus for processing instruction in computer system
US5954815A (en) * 1993-12-15 1999-09-21 Silicon Graphics, Inc. Invalidating instructions in fetched instruction blocks upon predicted two-step branch operations with second operation relative target address
US6247124B1 (en) 1993-12-15 2001-06-12 Mips Technologies, Inc. Branch prediction entry with target line index calculated using relative position of second operation of two step branch operation in a line of instructions
US6691221B2 (en) 1993-12-15 2004-02-10 Mips Technologies, Inc. Loading previously dispatched slots in multiple instruction dispatch buffer before dispatching remaining slots for parallel execution
JPH10510146A (en) * 1994-11-21 1998-10-06 ザ ユニバーシティ オブ リーズ Modified proteinase inhibitors
JP2008269067A (en) * 2007-04-17 2008-11-06 Nec Computertechno Ltd Vector processing device

Also Published As

Publication number Publication date
JPS6142308B2 (en) 1986-09-20

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