JPS6058489B2 - Branch instruction advance control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and in particular, it has one or more instruction buffer registers and a pointer that indicates from which position in the instruction buffer registers an instruction is to be taken out and placed; The present invention relates to advance control of branch instructions in an information processing device that sequentially fetches and processes instructions from a position indicated by the pointer.

FIG. 1 shows the format of a typical branch instruction.

In the figure, OP indicates the operation code of the instruction, and mask field M1 indicates the branch condition. The branch destination address is (X
2) Calculated by the sum of 10(B2)+D2.

() indicates the contents of the register. FIG. 2a shows the operation of a conventional branch instruction in the pipeline control system, and FIG. 2a (7) D, R, A, B, , B2, E, , E.
, CK, and W indicate each state of the pipeline, and a different instruction can enter the pipeline every two cycles, and a plurality of instructions can be processed in parallel. D is the state for decoding the instruction, R is the state for reading the registers of index X2 and base B2 to find the operand address, and A is the state for reading (
) + (B2) + D2, and the state B, , B performs the logical operation to obtain the address for accessing the storage device.
2 is a state in which the storage device is accessed using the obtained address.

However, B in the case of a branch instruction. A state is also a state that makes a branch decision. E, , E2 are states in which operations are performed using the obtained operand data, CK is a state in which data is checked, and W is a state in which writing is performed in various registers. Conventionally, the branch destination instruction is retrieved using the branch instructions D, R, A, B, .
Since it is the E state that takes the branch destination instruction into the instruction buffer, the interval from the branch instruction to the branch destination instruction is five cycles, as shown in FIG. 2A.

In order to improve the performance of branch instructions, the present invention has an index indicating the leading position of an instruction in the instruction buffer corresponding to each instruction buffer, decodes the instruction several instructions after the current instruction position, and reads the branch instruction. , the purpose is to process the branch instruction at high speed by prefetching the branch destination instruction.

Therefore, the present invention has one or more instruction buffer registers and a pointer that indicates from which position in the instruction buffer register an instruction should be taken out, and sequentially takes out instructions from the position indicated by the pointer. The information processing device that performs the processing has an instruction position flag in the instruction buffer register that indicates the starting position of the instruction in each of the above instruction buffer registers, and a subsequent instruction position flag that indicates the starting position of the subsequent instruction, and stores the instruction word from the storage unit. Each time it is read, a new instruction is generated based on the decoding result of at least some bits of the read instruction word, the value of the subsequent instruction position flag at that time, and the status of the instruction position flag in the instruction buffer register that has already been set. The instruction start position in the instruction word is detected, and the instruction position flag in the instruction buffer register of the corresponding instruction buffer register is set, and the pointer is pointed by the value of the above pointer and the instruction position flag in the buffer register. Pre-fetch and decode the next instruction or several instructions after the instruction currently being fetched, and if the pre-fetched instruction is a branch instruction, further calculate the branch destination address, and pre-read the instruction from the branch destination address. It is characterized by being made to do. below,
The present invention will be explained with reference to the drawings.

FIG. 2b is a diagram showing the operation of a branch instruction in the present invention.
The state is the branch instruction decoding state for prefetching the branch destination instruction, and the RP state is the branch instruction decoding state for prefetching the branch destination instruction. The index for determining the address of the branch destination instruction, the read state of the base register, i is the address generation state, and B1 and B2 are the read states from the storage device.

As shown in FIG. 2b, if the current instruction position is instruction 0 and the instruction several instructions after instruction 0 is a branch instruction, one cycle after instruction 0, the prefetch of the branch instruction is performed. DP state begins. If the branch instruction decoded in the DP state is a branch instruction that does not branch (such as when the instruction itself is invalid), the process does not proceed to the RP state. In other cases, advance to RP, l, Bl, B2 and prefetch the branch destination instruction. In this case, the preceding and succeeding instructions, instructions 0 to 3, are not affected in any way. As described later in FIG. 3, four instruction buffer registers IWR, I
WRC, IBR1, and n3RO are created, and the contents of the instruction buffer register IWR shown in FIG. 3, which were taken in before this prefetching operation, are saved in IWRC. Subsequently, the prefetched branch instruction is taken into the IWR.

Therefore, the instruction following the branch instruction is IWRClIBRl
, is in IBRO, and the prefetched branch destination instruction is ■WR
This means that it is included in the . When executing a branch instruction, if the prefetched branch destination instruction is valid, the instruction 3 following the branch instruction
The branch destination instruction begins one cycle after.

Then, in the eight states of the branch instruction, the branch condition within the processing unit and the M1 field are compared to determine whether or not to branch.
Therefore, until the B2 state where a branch is determined, instructions are executed every cycle. If a branch decision is made in the B2 state, either the branch destination instruction or instruction 3 is canceled in accordance with the branch decision, and the remaining instruction is continued. Furthermore, in the present invention, if the branch instruction is an unconditional branch, or if branching can be determined from the R state, the branch destination instruction is started two cycles after the branch instruction. (See FIG. 2C) By performing the above-described prefetching of the branch destination instruction, the conventional branch instruction, which used to take five cycles, can be shortened to two cycles.

Furthermore, if the prefetched branch destination instruction is valid, the branch destination address generation state (second
In FIG. b (7) A state), the next instruction is taken out by adding the prefetched branch instruction length L to the branch destination address (X2)+(B2)+D2 indicated by the branch instruction.

Actually, D2+L is created in the R state and added to (X2) and (B2) in the A state. This means that a large number of instructions after the branch are stored in the instruction buffer. Instructions can be processed without interruption. Next, the third
The figure is a block diagram of the instruction breadthreader section of the embodiment according to the present invention for executing the time chart shown in FIG. The flags (IPF) indicate the instruction positions in the four instruction buffer registers, and there are four flags for one instruction buffer register.

Flag 5 is stored in instruction buffer register IWRl, flag 6 is stored in instruction buffer register IWRl.
corresponds to instruction buffer register IWRC2, flag 7 corresponds to instruction buffer register IBRl, and flag 8 corresponds to instruction buffer register IBRO. 9 is a flag (NEXTIPF) for predicting the leading position of the instruction for the next 8 bytes to be read from the storage device.

10 to 12 are pointers (NSIP) that indicate from which position in the four instruction buffer registers the instruction is taken out, and each time one instruction is placed in the vibe line, the pointer is used to select the next instruction. It will transition.

13 is a subsequent instruction head position detection circuit, 14 is an instruction position detection circuit, 15 is an instruction selection generation circuit, 16 is a selector, and 18
is an instruction register, and 17 is a decoder.

First, the 8-byte data input to IWRl from the storage device is divided into 2-byte units, and the first 2 bits of each 2-byte and the value of NEXTIPF9 are sent to the instruction position detection circuit 14.
, detect the position of the command, and input the Ipl2 to I of IPF5.
Set to pl5.

In this case, the pointer Nl2 is initially set in NEXTIPF9. The reason why the instruction is divided into 2-byte units is because the minimum length of an instruction is 2 bytes, and the first 2 bits of each 2-byte are identified by the first 2 bits of the 0P code at the beginning position of each instruction. This is because the instruction length is identified.

In this way, for example, if four 2-byte length instructions are input to IWRl, Pl2 to 1p15 will all become "1", and if two 4-byte length instructions are input to IWRl, 1p12 and Fpl4 will be If one 2-byte long instruction and one 6-byte long instruction are input to IWRl, Ipl2 and Ipl3 become ``1''. NEXTIP
F9 indicates the head position of the next instruction to be read to 1WR1, and is created by the above two bits of 1P12 to 1p15 in IPF5 and the current IWR1.

For example, Ipl4 in IPF5 is "゜1゛", Ipl5 is "゜゜0゛", and 2 in IWRl corresponding to Ipl4 is
When the bit indicates that the instruction is 6 bytes long, the following instruction start position detection circuit 13 controls the N
In EXTIPF9, Nl3 is set to 6°1°. In other words, in this example, 4 bytes worth of instructions are input to IWRl from the position corresponding to Ipl4, but the remaining 2 bytes are set to the position corresponding to Ipl2 in the next read from the storage device, and It shows that the next instruction starts from the position corresponding to Ipl3.
Ipl2 to Ipl5 in IPF5 shift to IPF6, IPF7, and IPF8 in synchronization with the contents of ■IRl shifting to ■IRC2, IBR1, and IBRO. Therefore, PF5 to PF8 indicate the respective instruction positions in the four instruction buffer registers. Normally, when an instruction is to be executed, the instruction to be executed is selected through the selector 16 from one of the positions of the instruction buffer registers IWR, IWRC, IBRl, and IBRO shown in NSIPlO-12.

The selector 16 is controlled by an instruction selection generation circuit 15 which receives NSIPlO-12 as input. This selection operation is performed every two cycles, and the selected instructions are sequentially put into the vibe line, and processing starts from the D state shown in FIG. 2B. On the other hand, when a branch destination instruction is prefetched, the contents of IPF5 to 8 are inputted to the instruction selection generation circuit 15 along with NSIPlO to 12, the instruction is selected from the instruction buffer through the selector 16, and inputted to the decoder 17, and branching is possible. Analyze whether it is a valid instruction.

If the instruction is a branchable instruction, instruction decoding is started from the DP state shown in FIG. . By performing these operations, it becomes possible to prefetch a branch destination instruction at high speed. Here, among the branch instructions, there is an instruction such as a branch on count instruction. That is, each time the instruction is processed, the branch condition instruction register ■ specified by the above M1
There is an instruction that increments the contents of 1-1J, and when the result of the subtraction is the value RO, the branch is considered successful and the instruction at the branch destination address is executed. In the case of such a branch instruction, by checking the contents of the branch condition instruction register in advance and checking J1, it is possible to determine that the branch is successful without going to the trouble of 1-1J. When combined with the above-mentioned instruction prefetch function, it becomes possible to start executing the next instruction without wasting any time, just as in the case of a normal instruction. However, in general, the above-mentioned index register XR, base register
Register BRl and branch condition instruction register MR are provided in the general-purpose register group.

In conventional large-scale computers, it is possible to read out a total of 4 ports, 2 ports for address calculation and 2 ports for calculation, but since each port is dedicated, XR and BR are read for address calculation. It is not possible to simultaneously read the MR for branch condition checking in the state. However, if you increase the number of general-purpose register votes,
Alternatively, as proposed in Japanese Patent Application No. 54-95727, by providing two sets of 2-port general-purpose registers and controlling them so that the same contents are stored in both. In R-state? It is possible to check. Further, as described later, the address of the branch destination instruction obtained by the prefetch sequence DP, RP, i... of the branch destination instruction is held in the prefetch address register TAR, and the word of the branch destination instruction is stored in the prefetch address register TAR. If the address of the instruction that follows the branch destination instruction is determined by adding the length or one lookahead word length L, there is no need to read the BR and XR of the branch destination instruction address in the R state of the branch instruction. Therefore, the MR can be read without the special configuration as described above.

In this way, if the branch can be determined in the R state of the branch instruction, or if the D state is already determined to be an unconditional branch, the branch destination instruction can be immediately executed without having the B1 and B2 states.

Next, FIG. 4 is a block diagram of an instruction buffer section and an effective address calculation section of an embodiment according to the present invention, illustrating the process from taking an instruction into the instruction buffer to finding an execution address.

In FIG. 4, various pointers, flags, etc. illustrated in FIG. 3 are omitted. In Figure 4, the same numbers as in Figure 3 are the same, 20 is the vibe line, 21
is a decoder, 22 is a general-purpose register, 23 is an index register (XR), 24 is a base register (BR), 25
26 is a display plate register (DR), 26 is an address calculation adder, 27 is an effective address register 28 is a pre-fetch address register (TAR), and 29 is a selector. 1st
The 0P part of the instruction shown in the figure is stored in AO in the instruction register 18, and similarly, M1 is stored in A1, X2 is stored in A2, B2 is stored in A0, and so on.
3, D2 enters A4. Read the registers indicated by X2 and B2 from the general-purpose register 22, and
23, input to BR24, and D2 directly from A4 to DR
25 and is added by an address calculation adder 26 to obtain an effective address. The effective address output from the address calculation adder 26 is sent to the storage device, and advance reading of the instruction is performed. In one embodiment of the present invention, the prefetch sequence DP, RP of the branch target instruction
, i..., the address calculated by the address calculation adder 26 as described above is held in the TAR 28,
In the R and A states of branch instruction 2, this (TAR) and L are added to obtain the address following the branch destination.

Therefore, it is not necessary to read XR and BR at this time, so A1
Read the branch condition instruction register ■ from the general-purpose register 22 according to the register instruction, and check whether the contents are RlJ or not. If it is JlJ, it is assumed that the branch condition has been met, and the bit 8 of NSIPlO in FIG. 3 is immediately set to ゜゜1. stand up,
Read branch destination instruction 3 from IWRl. If RlJ is not present, the instruction following branch instruction 2 is read from prefetch registers 2-4. In addition, if the branch condition is not satisfied, the above (TAR
It goes without saying that there is no need to prefetch the address of )+L.

As described above, according to the present invention, when a branch instruction is generated by decoding an instruction several instructions after the current instruction position in the instruction buffer, the branch destination instruction is prefetched, and the branch condition is set early. By immediately branching to the branch destination when a branch instruction is found, the branch instruction can be processed at a higher speed than in the conventional method, and the performance of the information processing device can be improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the format of a branch instruction, FIG. 2a is a diagram showing the operation of a conventional branch instruction, FIG. 2b is a diagram showing the operation of a branch instruction according to the present invention, and FIG. 3 is a diagram according to the present invention. FIG. 4 is a block diagram of an instruction buffer section and an effective address calculation section of an embodiment according to the present invention.

Claims (1)

[Claims] 1 It has a plurality of instruction prefetch buffer registers, and when instructions are sequentially taken out from the buffer registers every predetermined number of cycles and executed, and when the presence of a branch instruction is detected in the instruction buffer register, In a system that uses cycles to prefetch a branch destination instruction, if the branch destination address calculation state during the execution process of the branch instruction or the establishment of the branch condition is established before that, the predetermined cycle from the branch instruction A branch instruction advance control method characterized in that execution of the prefetched branch destination instruction is started after a few seconds.