JPH024011B2 - - Google Patents

Description

[Detailed Description of the Invention] (A) Technical Field of the Invention The present invention relates to an instruction rereading control method, particularly in a data processing device that performs pipeline control, to control the rereading of subsequent instructions such as the so-called CS instruction, CDS instruction, and TS instruction. This relates to an instruction rereading control method that improves performance by allowing instruction rereading to start early by having an adder that can calculate the start address for instruction rereading from any stage for the required instructions. .

(B) Prior art and problems In data processing devices that execute instructions using pipeline control, CS (Compare and Swap) instructions, known as so-called serialization instructions,
CDS (Compare and Double Swap) instruction, TS
For (Test and Set) commands, it is necessary to discard all subsequent commands that were previously fetched and fetch the command again. This operation is called "instruction rereading".
It is called. The above command, especially in time sharing,
This occurs quite frequently in the operating systems (OS) of large machines that run many tasks. Therefore, it is extremely important for the performance of the processing device to perform instruction reread operations for these instructions at high speed and to reduce loss.

FIGS. 1 and 2 are diagrams for explaining problems with the conventional method.

FIG. 1 shows an example of conventional instruction rereading in a computer with a pipeline configuration in which instruction fetching takes three stages and instruction execution takes six stages.
Instruction fetch control consists of, for example, one stage to determine the address to fetch the instruction, an IT stage to convert the instruction address to a real address, and an IB stage to read the instruction from the buffer.
Execution control includes, after an instruction fetch, a D stage that decodes the instruction, an A stage that calculates the operand address, a T stage that converts the operand address into a real address, and reading from the buffer managed by the storage control unit. It consists of a B stage, an E stage for arithmetic processing, and a W stage for checking and writing results. Each of these stages is generally independent and can be controlled in advance, and on a high-speed computer,
Pipeline processing is occurring. Hereinafter, the case where the control stage described above is provided will be explained as an example, but the present invention is not limited to this.

An instruction that causes instruction re-reading is usually a multi-flow instruction, and multiple sets of D stage to W stage constitute one instruction. As shown in FIG. 1, normally there are several flows f2 to f4 after the flow f1 in which re-reading of an instruction is determined.
In the conventional method, the address for rereading the instruction is calculated after the final W stage of the final flow f4 of the instruction based on the instruction rereading information detected in the random flow f1, and the instruction is reread. was going there.

That is, a conventional circuit for calculating an address for rereading an instruction is, for example, as shown in FIG. In Figure 2, 1 is the instruction address register, 2 is the half-word counter, 3 is the PFK register, and 4 is the PFK register.
is an adder that generates an effective address of an instruction, 5 is an instruction effective address register, 6 is a buffer, and 7 is an instruction word register.

In the conventional circuit, the instruction address register 1 is
Also serves as the instruction address section (PSWIAR) of PSW,
It is the same register as part of PSW. During a normal instruction fetch, instruction address register 1
By adding the contents of PFK register 3 (normally 8), the instruction address to be fetched is determined. For example, when an interrupt occurs and the instruction address (OLDPSW) that was being executed is needed, the displacement between the fetch address and the instruction address that is the content of half-word counter 2 is found by subtracting it from instruction address register 1. It will be done like this.

In such a system, a subsequent instruction can only be fetched after the previous instruction has been completed. That is, since the instruction address register 1 is also used as a part of the PSW, the instruction address register 1 cannot be changed during instruction execution. Therefore, the address for rereading an instruction is not created until after the final flow of instructions is completed, and there is a problem in that a lot of loss occurs between rereading an instruction and starting execution of the readbehind instruction. Ta.

(C) Object and Structure of the Invention The present invention aims to solve the above-mentioned problems, and makes it possible to calculate the start address for rereading an instruction from any stage of any flow when it is necessary to reread a subsequent instruction. The purpose of the present invention is to make it possible to start an instruction fetch at an early timing when rereading an instruction. That is, the instruction rereading control method of the present invention is an instruction rereading control method for an information processing device that controls execution of instructions using a pipeline, and includes a prefetch instruction address register in which an address for pre-reading an instruction is stored, and a register for pre-reading an instruction. an instruction pointer that indicates the beginning of the instruction to be executed; a circuit that calculates the address of the instruction being executed from the prefetch instruction address register and the instruction pointer; and the adder. an instruction address register consisting of a multi-stage shift register that receives the instruction address, an instruction length register consisting of a multi-stage shift register storing the instruction length corresponding to the instruction address register; an adder for calculating the start address of an instruction to be executed next to the instruction at the address held by the instruction address register from one of the address registers and the corresponding instruction length register; The present invention is characterized in that when an event is detected, the output of the adder is set in the prefetch instruction address register, and the instruction is reread. Hereinafter, embodiments will be described with reference to the drawings.

(D) Embodiment of the Invention FIG. 3 is a time chart for explaining the outline of control according to the present invention, FIG. 4 is a main part configuration of an embodiment of the present invention, and FIG. 5 is an instruction processing circuit using the present invention. Here is an example.

In the case of the present invention, the start address and instruction length of the instruction currently being executed are held at each stage, and when it is decided to reread the instruction, based on this information, the address for rereading the instruction, That is, a start address for re-reading the subsequent instruction is created, and re-reading of the instruction is started. In the example shown in FIG. 3, the instruction reread address is determined based on the T stage address and the instruction length of the instruction, and the instruction is reread without waiting for the end of the final flow. The time loss in the example is reduced. Note that, as will be described later, it is also possible to determine the address for rereading the instruction at another stage.

Therefore, a circuit for creating an address for rereading instructions is configured as shown in FIG. 4, for example. In FIG. 4, numerals 3 to 7 correspond to those in FIG. 2, 13 is a prefetch instruction address register for advance reading, and 14 is an instruction pointer, in which the currently executed instruction is at the address indicated by the instruction address register 13. How many half words from
15 is an adder that calculates the address of the prefetched instruction; 16 to 18 are instruction address registers corresponding to each stage; 20 is an instruction length register for the decoded instruction;
21 to 23 are instruction length registers corresponding to each stage, 25 is one of instruction address registers 16 to 18 corresponding to the selected stage,
It represents an adder that adds the corresponding ones of the instruction length registers 21 to 23.

The pre-fetch instruction address register 13 stores an address for pre-reading instructions in 8-byte units, for example. The PFK register 3 has an initial value of "0" and thereafter holds a value of "8". Adder 4 adds the value of instruction address register 13 and the value of PFK register 3, and sets the effective address in register 5. Based on this address, the memory controller searches the buffer 6, fetches the instruction, and reads it into the instruction word register 7. After that, "8" is added to the instruction address and fetches are performed sequentially. Note that a configuration may be adopted in which a plurality of prefetch instruction address registers 13, instruction word registers 7, etc. are provided for the purpose of instruction branching.

The instruction pointer 14 indicates that each instruction to be executed
Holds a relative pointer to where in the instruction fetched bytes. The output of the adder 15 is the address of the instruction flowing in the pipeline, and is sequentially sent to instruction address registers 16 to 18, which are composed of multiple stages of shift registers. Correspondingly, the contents of the instruction length register 20 that holds the instruction length are sent to instruction length registers 21 to 23 provided in a plurality of stages at each stage.

By selecting a pair of instruction address registers 16 to 18 and instruction length registers 21 to 23 corresponding to each stage using a multiplexer and adding their contents together using an adder 25, instructions can be replayed at any stage. It has become possible to generate read addresses. When an instruction reread is required, the instruction reread address generated by the adder 25 is controlled to be set in the prefetch instruction address register 13, so that the instruction fetch sequence is started immediately. It's summery.

FIG. 5 shows an example of an instruction processing circuit using the present invention, and in the figure, the same reference numerals as in FIG. 4 correspond to those in FIG. 26 is an instruction address register that holds the address of the instruction being executed; 27 is an instruction length register that holds the instruction length of the instruction that is being executed; 28 is an adder that calculates the next instruction address; 30 is a displacement register; 31 is a base register, 32 is an index register, 33 is an operand address generation circuit, 34 and 35
is an operand address register, 36 is an operand word register, 37 is an execution circuit, and 38 is a result register.

Initially, when the instruction address to be executed is stored in the PSW instruction address field of the instruction address register 26, the same address is also supplied to the prefetch instruction address register 13. Then, as described above, the instructions are sequentially fetched in units of 8 bytes according to the address calculated by the adder 4.

The operand address generation circuit 33 calculates the effective address of the operand from the contents of the registers 30 to 32, etc., and sets it in the operand address register 34. As a result, the buffer 6 is accessed by the storage control section, an operand word is prepared, and an operation is performed by the execution circuit 37, which is an operation unit section. The result is written to result register 38.

In the case of the present invention, as explained with reference to FIG. 4, the contents of the instruction address registers 16 to 18 that hold instruction addresses corresponding to each stage and the contents of each instruction length register 21 to 23 are added. An adder 25 is provided whose output is directed to the prefetch instruction address register 13, thereby making it possible to reread instructions from the A stage, T stage, or B stage.
Furthermore, in this embodiment, the instruction currently being executed is determined based on the instruction address register 26, which also serves as the instruction address field (PSWIAR) of the PSW, and the instruction length register 27, which holds the instruction length of the instruction in the W stage. An adder 28 is provided which calculates the address of the next located instruction. Adder 28
Apart from the address calculation for advance reading by the adder 4, the start address of the next instruction is
Since it is constantly calculated, this allows the instruction reread sequence to start early.

(E) Effects of the Invention As explained above, according to the present invention, an address for rereading an instruction is created at an early timing, and an instruction can be reread at an early stage from any stage of any flow of an instruction being executed. Since the process can be started, processing performance is improved.

[Brief explanation of drawings]

1 and 2 are diagrams for explaining problems with the conventional method, FIG. 3 is a time chart for explaining the outline of control according to the present invention, and FIG. 4 is a main part configuration of an embodiment of the present invention. FIG. 5 shows an example of an instruction processing circuit using the present invention. In the figure, 1 is an instruction address register, 2 is a half-word counter, 3 is a PFK register, 4 is an adder that generates the effective address of the instruction, 5 is an instruction effective address register, 6 is a buffer, 7 is an instruction word register,
13 is a prefetch instruction address register, 14 is an instruction pointer, 16 to 18 are instruction address registers corresponding to each stage, and 20 to 2.
4 represents an instruction length register, and 25 represents an adder.

Claims (1)

[Claims] 1 In an instruction rereading control method in an information processing device that controls execution of instructions using a pipeline, a prefetch instruction address register stores an address for pre-reading an instruction, a register stores a pre-read instruction, and a register for storing an instruction to be executed. an instruction pointer indicating the beginning of the instruction to be executed; a circuit that calculates the address of the instruction being executed from the prefetch instruction address register and the instruction pointer; and a multi-stage shift register that receives the instruction address calculated by the adder. an instruction address register consisting of an instruction address register, an instruction length register consisting of a multi-stage shift register in which an instruction length is stored corresponding to the instruction address register, and one of the instruction address registers and the above instruction address register corresponding to the instruction address register. and an adder that calculates the start address of the instruction to be executed next to the instruction at the address held by the instruction address register from the instruction length register, and the output of the adder is preempted when an instruction reread event is detected. An instruction rereading control system characterized in that an instruction is set in an instruction address register to execute instruction rereading.