JPH06332701A - Information processor - Google Patents

Abstract

PURPOSE:To attain the further high speed of the execution of an instruction in the information processor of a pipeline control system. CONSTITUTION:An instruction buffer 1 stores an instruction string first-read from a memory. One instruction or two instructions are segmented from the instruction buffer 1 through a selector 2 to an instruction register 3 under the control of an instruction select control part 7. An instruction parallel discriminating circuit 4 discriminates the bit format of the instruction register 3, and allows the instruction register 3 to simultaneously output the two instructions through selectors 5 and 6 when the two instructions are present in the instruction register, and the competition of a resource is not generated between the two instructions. For example, when the instruction is outputted from the selector 5, a computing element 26 is used, and an access to a buffer memory 16 is not performed, and when the instruction is outputted from the selector 6, the access to the buffer memory 16 is performed, and the computer element 26 is not used. Then, those two instructions are executed in parallel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline control type information processing apparatus, and more particularly to an information processing apparatus for simultaneously executing in parallel an instruction using an arithmetic unit and an instruction to access a memory. .

[0002]

2. Description of the Related Art Command words of an information processing apparatus are generally classified into 2 bytes, 4 bytes, and 6 bytes. FIG. 2 shows the format of each command word, and the numbers represent bit positions.

The 2-byte instruction mainly performs an operation between general purpose registers (hereinafter abbreviated as GPR). GP
As R, there are generally 16 registers for storing 4-byte data, and these are designated by numbers 0 to 15. Bits 0 to 7 of the instruction word are instruction codes representing operations (OP) such as addition and subtraction. Bits 8 to 11 and bits 12 to 15 each consist of 4 bits and are fields for designating a GPR number. For example, in the addition instruction, the 4-byte contents of the GPR specified in the R1 field (first operand data) and the 4-byte contents of the GPR specified in the R2 field (second operand data) are added, and the result is displayed in the R1 field. This means storing in the specified GPR.

The 4-byte instruction mainly performs arithmetic operation and transfer of data between the memory and the GPR. In this case, the content of the GPR specified by the X2 field of bits 12 to 15 of the instruction word (index address) and the content of the GPR specified by the B2 field of bits 16 to 19 (base address) and the bits of 20 to 31 An address (operand address) on the memory is obtained by adding the three data of the value of the D2 field of the above. Bits 0 to 7 and bits 8 to 11 have the same meanings as the 2-byte instruction. For example, in the load instruction, X2, B2, and D
Transfers the data (operand data) at the corresponding address on the memory specified in 2 to the GPR specified in the R1 field, and in the store instruction, the GPR specified in the R1 field
Data (operand data) is transferred to the corresponding address on the memory specified by X2, B2, and D2, and in the addition instruction, the content of GPR specified by the R1 field is 4 bytes (first operand data), X2, B2, and D2. It means that the data of 4 bytes (second operand data) at the corresponding address on the memory specified by is added and the result is stored in the GPR specified by the R1 field.

The 6-byte instruction is mainly for calculating and transferring data between memories. In this case, bit 16
The sum of the 4 bytes of the GPR specified in the B1 field of ˜19 and the value of the D1 field of bits 20 to 31 becomes one address (first operand address) on the memory, and the B2 field of bits 32 to 35. Contents of GPR specified in 4 bytes and D of bits 36 to 47
The value obtained by adding the values of the two fields becomes the other address (second operand address) on the memory. Bit 0
The meaning of ~ 7 is the same as that of the 2-byte instruction or the 4-byte instruction. L1 field of bits 8-11, bits 12-1
The L2 field of 5 has the first operand and the second operand, respectively.
It specifies the number of bytes in the operand. Since this 6-byte instruction is not subject to instruction parallel execution of the present invention, detailed description thereof will be omitted.

On the other hand, in an information processing apparatus, there is a pipeline control method as a method for speeding up the execution of instruction processing. This pipeline control system divides the processing of one instruction into a plurality of independent stages, and simultaneously executes the processing of each stage of a plurality of different instructions in a pipeline manner to realize an effective one instruction. This is a control method that shortens the execution processing time.

Conventionally, in this type of pipeline control type information processing apparatus, regardless of the type of instruction, each stage is executed with a unique pitch (cycle) shift for all instructions.

FIGS. 8 and 9 show an example of such pipeline processing. In this example, the processing of one instruction is divided into 6 stages of D, M, A, L, E and W. Here, D is an instruction decoding stage, M is an address calculation stage for obtaining the logical address of the operand, A is an address conversion stage for converting the calculated logical address of the operand into a real address, and L is a buffer memory or main memory. Is a read stage for reading operand data from E, E is an operation stage for performing an operation using the obtained operand data, and W is a storage stage for writing the operation result to a register or the like. In the example of FIG. 8, these stages are executed at a pitch of 1 cycle, and each instruction is effectively processed in 1 cycle. However, if the instruction requires 3 cycles, such as instruction 3 in FIG.
The stage extends to 3 cycles, and M of the following instruction 4
Delayed stage launch. Incidentally, this type of pipeline processing is described in, for example, Japanese Patent Laid-Open No. 2-48733.

Further, as a special pipeline control system, a pipeline control system in which the order of execution of instruction sequences is changed is also used in order to avoid disturbance of the pipeline in the event of resource competition. An information processing apparatus using this type of pipeline control system is disclosed in, for example, Japanese Patent Laid-Open No. 61-61.
-16335.

[0010]

In the prior art, no consideration is given to simultaneously activating the pipeline processing of the preceding instruction and the succeeding instruction, and all the instructions are uniquely shifted in pitch and each stage is assigned. Therefore, there is a problem that useless cycles occur depending on the type of instruction, and the advantage of pipeline control cannot be fully exerted.

For example, in FIG. 8, since all instructions are executed in 6 stages, in a 2-byte instruction, M
And nothing is executed in the A stage, and G is executed in the L stage.
Operand data is read from PR, and in a 4-byte instruction load instruction, the operand data read from the buffer memory in the L stage is stored in GPR, and no execution is performed in the E and W stages. In the store instruction, the operand data is read from the GPR in the A stage, the operand data read in the L stage is stored in the buffer memory, and nothing is executed in the E and W stages. Different cycles occur.

An object of the present invention is, in a pipeline control type information processing apparatus, a load or store instruction of a 2-byte instruction that does not access a memory and uses an arithmetic unit and a 4-byte instruction that accesses a memory and does not use an arithmetic unit. like,
Depending on the type of instruction, the processing of the preceding instruction and the succeeding instruction is simultaneously activated and executed in parallel to speed up the processing of the instruction.

[0013]

In order to achieve the above object, the invention of claim 1 divides the processing of instructions into a plurality of independent stages, and executes the processing of each stage of a plurality of different instructions in parallel. In an information processing apparatus of a pipeline control system, an instruction buffer that stores an instruction sequence prefetched from a memory, a selector that cuts out one or two instructions from the instruction buffer, and one or two instructions cut out from the instruction buffer. Instruction register to store,
An instruction parallel determination means for determining the bit format of the instruction register, storing two instructions in the instruction register, and activating pipeline processing of the two instructions at the same time when resource competition does not occur between the two instructions. It is characterized by being provided.

According to a second aspect of the present invention, in the instruction parallel determination means, two instructions are stored in the instruction register, one instruction accesses a memory and does not use an arithmetic unit, and the other instruction operates. In the case of an instruction that uses a memory and does not access the memory, the pipeline processing of the two instructions is activated at the same time.

[0015]

If the instruction register has a length of 6 bytes, only one 6-byte instruction can be stored, but two instructions, a 2-byte instruction and a 4-byte instruction, which are adjacent to each other, can be stored at the same time. If no resource conflict occurs between the two instructions stored in this instruction register, an instruction that accesses the memory and does not use the arithmetic unit by activating the parallel execution of the two instructions, for example, a load instruction of a 4-byte instruction And a store instruction, and an instruction that uses an arithmetic unit and does not access the memory, for example, 2
Pipeline processing such as addition of byte instructions can be executed in parallel at the same time. As a result, E and W that are wasted in instructions that access the memory and do not use the arithmetic unit
It is possible to effectively use the M, A, and L stages that are wasted in the instructions that use the stages and the arithmetic units and do not access the memory.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be specifically described below with reference to the drawings.

FIG. 1 is a block diagram of an information processing apparatus showing an embodiment of the present invention. In this embodiment, similarly to the above, an apparatus adopting a pipeline control system including six stages D, M, A, L, E and W will be described as an example.

In FIG. 1, reference numeral 1 is an instruction buffer for storing a prefetched instruction sequence from a buffer memory or main memory (not shown), and 2 is an instruction selector for selecting an instruction to be executed next from the instruction buffer 1. An instruction register 3 stores the instruction selected by the selector 2. In this embodiment, it has a length of 6 bytes and can store a 6-byte instruction, or a 2-byte instruction and a 4-byte instruction at the same time.
An instruction parallel determination circuit 4 determines whether or not two instructions can be executed in parallel when the two instructions are stored in the instruction register 3. The selectors 5 and 6 respectively select an instruction from the instruction register 3 based on the instruction of the instruction parallel determination circuit 4. The instruction select control unit 7 also controls the selecting operation of the instruction selector 2 based on the instruction from the instruction parallel determination circuit 4.

Reference numeral 8 is a decode storage for decoding the instruction selected by the selector 6, and 9 is a decode data register for holding the instruction decoding result. A stage controller 10 controls the M, A, and L stages according to the contents of the register 9.

Reference numeral 11 is a general purpose register (GPR), and in this embodiment, 16 registers each storing 4-byte data are formed. Reference numeral 12 is an address calculator that calculates a logical address, 13 is a logical address register that holds the calculated logical address, 14 is a TLB that associates the logical address with a real address, and 15 is a real address register that holds the real address. Reference numeral 16 denotes a buffer memory (cache memory) that holds a copy of a part of the main memory (main memory).
5 is accessed.

Reference numeral 17 designates the instruction selected by the selector 5 as M
The instruction register that holds the stage delay, 18 is A
Instruction register that holds the instruction delayed to the stage, 1
Reference numeral 9 is an instruction register that holds an instruction delayed to the L stage. Reference numeral 20 is a micro address register that holds the address of a micro program activated by the instruction code of the instruction register 18, 21 is a control storage that stores the micro program and is accessed by the micro address register 20, and 22 is read from the control storage 21. A micro data register for holding a micro program, 23 is a register 22
Is a decoder that decodes the contents of the.

Reference numerals 24 and 25 are input registers to which data for calculation are input. 26 is register 2
It is an arithmetic unit for adding and subtracting the contents of 4, 25, and the arithmetic operation is instructed by the decoding result of the decoder 23. 27
Is an output register of the arithmetic unit 26.

The pipeline processing operation during instruction parallel execution in the information processing apparatus of FIG. 1 will be described below.

When the instruction buffer 1 holds an instruction of 6 bytes or more, 6 bytes are read from the instruction buffer 1 by the selector 2 and stored in the instruction register 3.
The instruction parallelism determination circuit 4 determines the number and type of instructions stored in the instruction register 3, 6 bytes consists of two instructions, and these instructions use an arithmetic unit without accessing the memory (2 When it is determined that there is no GPR11 conflict between two instructions, which is a pair of a byte instruction) and an instruction that accesses the memory and does not use the arithmetic unit (4 byte instruction), the control line 40 tells the selector 5 Is
It is instructed to select one of the two instructions that uses the arithmetic unit without accessing the memory, and the control line 41 instructs the selector 6 to access the memory and select the instruction that does not use the arithmetic unit. Instruct to do. Further, the instruction parallel determination circuit 4 instructs the instruction selection control unit 7 to cut out an instruction 6 bytes ahead in order to decode the next instruction.

According to the instruction from the instruction parallelism determination circuit 4, the selector 5 selects a 2-byte instruction that uses the arithmetic unit without accessing the memory from the instruction register 3, and the selector 6 accesses the memory from the instruction register 3 to access the arithmetic unit. Select a 4-byte instruction that does not use. The two instructions are executed concurrently in parallel as follows.

The instruction (4 byte instruction) selected by the selector 6 accesses the decode storage 8 by the OP field of the instruction in the D stage and reads the decoded data to the register 9. Based on the contents of the decode data register 9, the stage control unit 10 controls the M stage, A stage, and L stage after the D cycle. That is, in the M stage, the selector 6
The GPR 11 is accessed according to the values of the B2 field and the X2 field of the instruction selected by, the base address and the index address are read, and the values of the D2 field of the instruction selected by the selector 6 are added by the address calculator 12. Then, the logical address is obtained and stored in the logical address register 13. At the A stage, the TLB 14 is accessed by the logical address of the logical address register 13 to obtain the real address and stored in the real address register 15. In the L stage, when the instruction selected by the selector 6 is a load instruction, the data is read from the buffer memory 16 by the real address of the real address register 15 and stored in the GPR 11 designated by the R1 field of the instruction. When the instruction selected by is a store instruction, data is read from the GPR 11 in the R1 field of the instruction, and the buffer memory 16 is read by the real address of the real address register 15.
To store. Nothing is done in the E and W stages.

On the other hand, the instruction (2-byte instruction) selected by the selector 5 is stored in the instruction register 17 in the D stage. In the M stage, the instruction is transferred from the instruction register 17 to the instruction register 18. A
At the stage, the instruction is transferred from the instruction register 18 to the instruction register 19, and the microprogram start address obtained from the instruction code (OP) of the instruction register 18 is stored in the microaddress register 20. In the L stage, the micro address register 2
Control storage 2 with a micro address of 0
The contents read from 1 are the micro data registers 22.
Stored in. Further, the GPR 11 is accessed by the values of the R1 field and the R2 field of the instruction register 19 to read the respective data and store them in the registers 24 and 25. Register 2 at the E stage
The data of 4 and 25 are used for calculation by the calculator 26, and the calculation result is stored in the register 27. The arithmetic unit 26 is controlled by the result of decoding the contents of the micro data register 22 by the decoder 23. At the W stage, the data of the register 27 is stored in the GPR 11 designated by the R1 field of the instruction.

When the two instructions cut out to the instruction register 3 are not a pair of an instruction that does not access the memory and uses the arithmetic unit and an instruction that accesses the memory and does not use the arithmetic unit, or the instruction register 3 If only one instruction is contained in, the instructions are not executed in parallel and are executed one by one. This is from the instruction parallel determination circuit 4 to the control line 4
The selectors 5 and 6 are controlled to select from the head of the instruction register 3 through 0 and 41, and the instruction select control unit 7 cuts out the instruction one instruction ahead in order to decode the next instruction. It is realized by controlling the selector 2.

Next, the instruction parallel determination circuit 4 and the selectors 5 and 6 will be described in detail with reference to FIGS.

FIG. 3 shows a bit format when the instruction register 3 stores a 2-byte instruction that does not access the memory and uses the arithmetic unit and a 4-byte instruction that accesses the memory and does not use the arithmetic unit in this order. is there. 4 is shown in FIG.
On the contrary, the bit format is used when the instruction register 3 stores a 4-byte instruction that accesses the memory and does not use the arithmetic unit and a 2-byte instruction that does not access the memory and uses the arithmetic unit.

FIG. 5 is a detailed diagram of the instruction parallel decision circuit 4, which decides the load instruction (L) and the store instruction (ST) of the 4-byte instruction which accesses the memory and does not use the arithmetic unit. , One-cycle instruction (R
R) for determining R), determination circuits 46, 47 and 48 for identifying race conditions of the GPR 11, an inverter 49, a 2-input NOR circuit 50, and 3-input AND circuits 51 and 52.

In FIG. 5, when the instruction register 3 has the bit format shown in FIG. 3, the decision circuit 43 is established and the decision circuit 44 is established.
If there is no conflict of 1, the match determination circuits 47 and 48
Is not established, the control line 41 of the selector 6 is "1".
Becomes Further, since the determination circuits 42 and 45 are not established, the control line 40 of the selector 5 becomes "0". on the other hand,
When the instruction register 3 has the bit format shown in FIG. 4, the determination circuit 42 is established and the determination circuit 45 is established, and if there is no GPR11 conflict between both instructions, the coincidence determination circuit 46 is not established. , The control line 40 of the selector 5 becomes "1". Further, the determination circuits 43 and 44
Is not established, the control line 41 of the selector 6 is "0".
Becomes

FIG. 6 is a diagram for explaining the operation of the selector 5. 6, bits 0 to 15 of the instruction register 3 are selected when the control line 40 is "0" (case of FIG. 3), and bits 32 to 47 of the instruction register 3 are selected when the control line 40 is "1". Is selected (case of FIG. 4). As a result, the selector 5 selects an instruction that uses the arithmetic unit without accessing the memory when executing the parallel instruction.

FIG. 7 is a diagram for explaining the operation of the selector 6. In FIG. 7, bits 0 to 31 of the instruction register 3 are selected when the control line 41 is “0” (case of FIG. 4), and bits 16 to 47 of the instruction register 3 are selected when the control line 41 is “1”. Is selected (case of FIG. 3). As a result, the selector 6 selects the instruction that accesses the memory and does not use the arithmetic unit when executing the parallel instruction.

10 and 11 show an example of pipeline processing according to the present invention.

FIG. 10 corresponds to the case where the instruction register 3 has the bit format shown in FIG. 3, where the instruction 2 is a 2-byte instruction that uses the arithmetic unit without accessing the memory, and the instruction 3 accesses the memory and the arithmetic unit Is a 4-byte instruction that does not use. Instruction 2 and instruction 3 simultaneously start operation from the D stage. The instruction 2 moves only to the instruction registers 18 and 19 in the M and A stages and does not execute anything. In the L stage, data is read from the GPR 11 and the register 24 and
25, stores the result in the register 27 after the arithmetic operation by the arithmetic unit 26 in the E stage, and registers 2 in the W stage.
The data of No. 7 is stored in GPR11. On the other hand, instruction 3
At the M stage, the base address and index address are read from the GPR 11, the logical address is obtained by the address calculator 12 and stored in the logical address register 13, and at the A stage the real address is obtained from the TLB 14 and stored in the real address register 15, In the stage, if the instruction 3 is a load instruction, the data is read from the buffer memory 16 at the real address of the real address register 15 and stored in the GPR 11, and if the instruction 3 is a store instruction,
The data is read from the GPR 11 and the buffer memory 16
, And do nothing in the E and W stages. In the L stage, GPR11 is executed by instruction 2 and instruction 3.
However, there is no problem because the instruction parallel determination circuit 4 determines that the same register is not used.

FIG. 11 corresponds to the case where the instruction register 3 has the bit format shown in FIG. 4, where the instruction 2 accesses the memory and does not use the arithmetic unit, and the instruction 3 does not access the memory and the arithmetic unit does not use the arithmetic unit. Is a 2-byte instruction that uses. In FIG. 11, instruction 2 and instruction 3 are shown in FIG.
If the instructions 3 and 2 of 0 are replaced, the operation is exactly the same as in FIG.

As shown in FIGS. 10 and 11, the memory is accessed by executing the instruction that accesses the memory and does not use the arithmetic unit in parallel with the instruction that uses the arithmetic unit without accessing the other memory. The execution cycle of an instruction that does not use an arithmetic unit can be apparently set to zero. Therefore, the processing of the instruction becomes faster.

In the above description of the embodiment, the pipeline processing stage is the instruction decoding stage D, the operand
It is assumed that the calculation stage M includes an address calculation stage M, an operand address conversion stage A, an operand data read stage L, an operand data operation stage E, and an operation result storage stage W. There is no need to limit.

For example, if the pipeline stage is D,
In the case of 5 stages of M, A, E and W, in parallel execution of 2 instructions, 2 instructions are decoded in the D stage, operand address calculation of the instruction to access the memory is performed in the M stage, and the A stage is executed. In the same way, the operand address of the instruction that accesses the memory is converted from the logical address to the real address, and the memory access of the instruction that accesses the memory is performed at the E stage, and the operation of the instruction that uses the arithmetic unit is performed (resource competition). However, the operation result of the instruction using the arithmetic unit may be stored in the W stage.

The pipeline stages are D, M,
In the case of 4 stages of E and W, in parallel execution of 2 instructions, 2 instructions are decoded in the D stage, operand address calculation of the instruction to access the memory is performed in the M stage, and memory is accessed in the E stage. The memory access of the instruction to be executed is performed, the operation of the instruction using the arithmetic unit is performed, and the operation result of the instruction using the arithmetic unit is stored in the W stage.

Further, the pipeline stages are D,
In the case of three stages of E and W, in parallel execution of two instructions, the two instructions are decoded in the D stage, the operand address calculation of the instruction to access the memory is performed in the E stage, and the instruction using the arithmetic unit is used. Is performed, the memory access of the instruction to access the memory in the W stage is performed, and the operation result of the instruction using the arithmetic unit is stored.

[0043]

As described above, according to the present invention,
When resource conflicts do not occur between two instructions, such as instructions that access the memory and do not use the arithmetic unit and instructions that do not access the memory and use the arithmetic unit, the two instructions can be simultaneously executed in parallel in parallel. Therefore, the execution of instructions in the pipeline control type information processing apparatus is further speeded up.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an information processing device according to the present invention.

FIG. 2 is a diagram showing formats of a 2-byte instruction, a 4-byte instruction, and a 6-byte instruction.

3 is a diagram showing an example of a bit format in which two instructions that can operate in parallel are stored in an instruction register 3 in FIG.

4 is a diagram showing another example of a bit format in which two instructions capable of operating in parallel are stored in the instruction register 3 of FIG.

5 is a diagram showing a detailed configuration of an instruction parallel determination circuit 4 in FIG.

FIG. 6 is a diagram showing a detailed configuration of a selector 5 in FIG.

FIG. 7 is a diagram showing a detailed configuration of a selector 6 of FIG.

FIG. 8 is a diagram showing an example of conventional pipeline processing.

FIG. 9 is a diagram showing another example of conventional pipeline processing.

FIG. 10 is a diagram showing an example of pipeline processing according to the present invention.

FIG. 11 is a diagram showing another example of pipeline processing according to the present invention.

[Explanation of symbols]

 1 Instruction Buffer 2 Instruction Selector 3 Instruction Register 4 Instruction Parallel Judgment Circuit 5 Selector 6 Selector 7 Instruction Select Control Unit 8 Decode Storage 9 Decode Data Register 10 Stage Control Unit 11 General Purpose Register 16 Buffer Memory 20 Micro Address Register 21 Control Storage 22 Micro Data register 23 Decoder 26 Operation unit

Claims (2)

[Claims] 1. A pipeline control type information processing apparatus for dividing instruction processing into a plurality of independent stages and executing processing of different stages of a plurality of instructions in parallel stores an instruction string prefetched from a memory. An instruction buffer, a selector for cutting out one or two instructions from the instruction buffer, an instruction register for storing one or two instructions cut out from the instruction buffer, a bit format of the instruction register, and the instruction An information processing apparatus, comprising: two instructions stored in a register; and instruction parallel determination means for simultaneously activating pipeline processing of the two instructions when resource competition does not occur between the two instructions. 2. The instruction parallelism determining means stores two instructions in the instruction register, one instruction accessing a memory and not using a computing unit, and the other instruction accessing a memory using a computing unit. The information processing apparatus according to claim 1, wherein in the case of an instruction not to be executed, pipeline processing of the two instructions is simultaneously started.