JPH0991139A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase pipe-line processing speed by selectively using either precedence operation or the preread of branching destination instruction at the time of the unused cycle of an instruction address adder. SOLUTION: When an instruction stored in an instruction register 4 for precedence instruction is an LR instruction, at an instruction address adder use method discrimination circuit 18, a value (such as a bit '1', for example) showing the preceding reading of the branching destination instruction is outputted to a line 18A but in the case of LA instruction, a value (such as a bit '0', for example) showing the precedence operation is outputted to a line 18 and applied to an adder input select signal generating circuit 17. Therefore, when the precedence instruction is the LR instruction and a following instruction is a BC instruction, the adder input select signal generating circuit 17 allows an instruction address adder 13 to execute branching destination instruction pre-reading function so that the processing of the BC instruction can be started earlier one cycle and an instruction 3 of a branching destination instruction example is put into the pipeline in the 7th cycle.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline type information processing apparatus, and more particularly to an information processing apparatus that processes an instruction string including branch instructions at high speed.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram for explaining a pipeline type information processing device according to the prior art, FIG. 3 is a diagram for explaining an example of an instruction to be used, and FIGS. It is a time chart explaining the pipeline, below,
A conventional information processing apparatus will be described with reference to these drawings.

In FIG. 2, 1 is an instruction buffer register, 2 is an instruction cutout aligner A, 3 is an instruction cutout aligner B, 4 is an instruction register for a preceding instruction, 5 is an instruction register for a succeeding instruction, and 6 is an instruction capable of performing a preceding operation. Circuit, 7 branch instruction detection circuit, 8 general-purpose register, 9 operand address adder, 10 operand TLB, 11 operand buffer storage device, 12 arithmetic unit, 13 instruction address adder, 14 instruction TLB, 15 is an instruction buffer storage device, 16 is a preceding operation result register, and 17 is an adder input select signal generation circuit.

The conventional information processing apparatus shown in FIG. 2 is configured to include the functional blocks shown in the figure, and each functional block is configured to have the functions described below.

The instruction buffer register 1 is a register that holds an instruction to enable high-speed access of the instruction, and the instruction cutout aligner A2 cuts the instruction buffer register 1 from which an instruction to be processed next is started. It has a function to put out. The instruction cutout aligner B3 has a function of cutting out an instruction following the instruction cut out by the instruction cutout aligner A2.

The instruction register 4 for the preceding instruction is a register for storing the instruction supplied from the instruction cutout aligner A2. The instruction register 5 for the subsequent instruction is a register in which the instruction supplied from the instruction cutout aligner B3 is stored. The preceding operation possible instruction detection circuit 6 determines whether or not the instruction stored in the instruction register 4 for the preceding instruction is an instruction capable of preceding operation. Instructions that can be calculated in advance will be described later. The instruction in each instruction register is decoded by a decoder (not shown).

The branch instruction detection circuit 7 detects whether the instruction stored in the instruction register 5 for the subsequent instruction is a branch instruction. The adder input select signal generation circuit 17 uses the instruction stored in the instruction register 4 for the preceding instruction and the information obtained by the preceding operation enable instruction detection circuit 6 and the branch instruction detection circuit 7 to add the instruction address adder 13 It has a function to select the data to be input to.

The operation contents of the operand address adder 9 are determined by the instruction stored in the instruction register 4 for the preceding instruction, and the index or base supplied from the general-purpose register 8 composed of, for example, 16 register groups. The logical address of the operand is calculated by using the register data or a part of the instruction register 4 for the preceding instruction. The operand TLB 10 has a function of converting the logical address from the operand address adder 9 into a physical address. The operand buffer storage device 11 supplies the data specified by the physical address from the operand TLB 10 to the arithmetic unit 12. The arithmetic unit 12 has a function of executing an arithmetic operation using the operand data supplied from the operand buffer storage device 11 and the general-purpose register 8.

When the instruction stored in the instruction register 4 for the preceding instruction is a branch instruction, the instruction address adder 13
For example, it has a function of calculating a branch destination logical address by using an index or base register data supplied from the general-purpose register 8 or a part of the instruction register 4 for the preceding instruction.

The instruction stored in the instruction register 4 for the preceding instruction is not a branch instruction, and the branch instruction detection circuit 7
In, when the instruction stored in the instruction register 5 for the subsequent instruction is detected to be a branch instruction, the instruction address adder 13 calculates the branch destination logical address of the branch instruction stored in the instruction register 5 for the subsequent instruction. Equipped with.

The instruction TLB 14 converts the logical address from the instruction address adder 13 into a physical address, and the instruction buffer storage device 15 stores the instruction string designated by the physical address from the instruction TLB 14 into the instruction buffer register 1. And a function for supplying to the instruction register 4 for the preceding instruction.

When the preceding instruction is not a branch instruction and the succeeding instruction is a branch instruction, and the general-purpose registers designated by the operands of the respective instructions are different, the preceding instruction and the succeeding instruction are simultaneously put into the pipeline to branch the branch instruction. The destination address is calculated by the instruction address adder 13. As a result, the instruction sequence at the branch destination can be supplied one cycle ahead of the normal sequence. This function is called branch destination instruction read-ahead.

Another function of the instruction address adder 13 has a preceding operation function. The preceding operation possible instruction detection circuit 6 detects that the instruction stored in the instruction register 4 for the preceding instruction is an instruction that uses only the data of the general-purpose register 8 for the operation, and determines whether the instruction can execute the preceding operation. To judge. That is, the instruction arithmetically operable instruction has the same value as the value obtained by the arithmetic unit 12 as the instruction address adder 13
It is an instruction that can be obtained at.

When the preceding operation enabling instruction detection circuit 6 detects that the instruction stored in the instruction register 4 for the preceding instruction is an instruction capable of performing the preceding operation, the adder input select signal generation circuit 17 detects the instruction for the preceding instruction. A signal for selecting the data required by the instruction stored in the instruction register 4 is generated. Therefore, the instruction address adder 13 obtains the operation result of the instruction stored in the instruction register 4 for the preceding instruction, and the operation result is stored in the preceding operation result register 16
To be stored. Therefore, the calculation result is stored in the preceding calculation result register 16 in a cycle before the calculation by the calculator 12 and the storage in the general-purpose register 8.

After that, the adder input signal select circuit 17
Detects a match between the general-purpose register number to be used in the subsequent branch-destination address calculation and the general-purpose register number to which the operation result stored in the preceding operation result register 16 is stored,
The data of the preceding operation result register 16 instead of the general-purpose register 8 is supplied to the instruction address adder 13.

Next, an example of instructions used in the information processing apparatus having the above-mentioned functions will be described using the format shown in FIG.

The L instruction (load instruction) is an instruction to transfer the data in the main memory designated by the second operand to the general-purpose register designated by the first operand. OP is an operation code indicating that this instruction is an L instruction, R1 is a field indicating the above-mentioned first operand, X2 is a field specifying the index address register of the second operand, and B2 is a base address register of the second operand. A designated field, D2, is a field indicating the displacement address of the second operand. In this instruction, the address specified by the second operand is obtained by adding the contents of the index address register specified by the X2 field, the contents of the base address register specified by the B2 field, and the contents of the D2 field. You can

The LR instruction (load register-to-register instruction) is an instruction to transfer the contents of the general-purpose register specified by the second operand to the general-purpose register specified by the first operand. OP is an operation code indicating that this instruction is an LR instruction, R1, R2
Is a field indicating the above-mentioned first and second operands.

The LA instruction (load address instruction) is the second
This is an instruction to transfer the address value specified by the operand to the general-purpose register specified by the first operand. OP is an operation code indicating that this instruction is an LA instruction, R1 is a field indicating the above-mentioned first operand, X2 is a field specifying the index address register of the second operand, and B2 is a base address register of the second operand. A designated field, D2, is a field indicating the displacement address of the second operand. In this instruction, the address value designated by the second operand is obtained by adding the contents of the index address register designated by the X2 field, the contents of the base address register designated by the B2 field, and the contents of the D2 field. be able to.

The BC instruction is a conditional branch instruction that branches to the branch destination address designated by the second operand when the condition code is set in the state designated by the mask field. OP is an operation code indicating that this instruction is a BC instruction, M
1 is a mask field, X2 is a field that specifies the index address register of the second operand, B2 is a field that specifies the base address register of the second operand,
D2 is a field indicating the displacement address of the second operand.

In this instruction, the branch destination address specified by the second operand adds the contents of the index address register specified by the X2 field, the contents of the base address register specified by the B2 field, and the contents of the D2 field. It can be obtained by M1 is compared with the condition code at the time of executing the BC instruction, and if they match, the branch is taken. If they do not match, the instruction next to the BC instruction is executed.

Although the above branch instruction is not limited to the conditional branch instruction, a BC instruction which is an example of the branch instruction will be described here as an example.

Next, with reference to FIGS. 4 to 7, description will be given of a processing operation in the case of processing an instruction string including the above-mentioned instruction in the conventional technique configured as described above. In these figures, the upper horizontal axis indicates the pipeline execution cycle. In addition, D, A, T, B, and
L and E represent pipeline stages, and perform the following processes, respectively.

The D stage is the instruction register 4 for the preceding instruction.
The instruction stored in 1 is decoded, and the processing for referring to the general register 8 for generating an operand or instruction address performed in the A stage is performed.

In the A stage, the operand address adder 9 is used to obtain the logical address of the operand using the contents of the general-purpose register 8 referred to in the D stage and a part of the instruction register 4 for the preceding instruction. In the case of a branch instruction, the instruction address adder 13 in the A stage performs a process of obtaining the logical address of the branch destination.

At the T stage, the logical address of the operand obtained by the operand address adder 9 at the A stage is converted into a physical address by the TLB 10 for the operand. In the case of a branch instruction, the instruction TLB 14 converts the logical address of the branch destination instruction obtained by the instruction address adder 13 into a physical address.

The B stage refers to the operand buffer storage device 11 by the physical address of the operand obtained by the TLB for operand 10 in the T stage and performs a process of obtaining operand data. Further, in the case of a branch instruction, in the T stage, a process of obtaining a branch destination instruction string is performed by referring to the instruction buffer storage device 15 with the physical address of the branch destination instruction obtained by the instruction TLB 14.

The L stage transfers the operand data obtained in the operand buffer storage device 11 to the arithmetic unit 12 in the B stage. In the case of an instruction that uses the data stored in the general-purpose register 8 as operand data, a process of transferring the contents of the general-purpose register 8 to the arithmetic unit 12 is performed. Further, in the case of a branch instruction, in the B stage, processing of transferring the branch target instruction sequence obtained from the instruction buffer storage device 15 to the instruction buffer register 1 is performed. If the branch of the branch instruction is taken, the branch destination instruction is stored in the instruction register 4 for the preceding instruction. That is, when the branch of the branch instruction is taken, the branch destination instruction is input to the pipeline and the D stage is started in the cycle next to the L stage of this branch instruction.

The E stage uses the operand data previously obtained by the arithmetic unit 12 to perform a process of executing an arithmetic operation. The operation result is a general register 8,
Alternatively, it is written in the operand buffer storage device 11.

Since each stage of the above-mentioned processing can be processed without conflict of the logic used, it is possible to execute the processing by overlapping each stage utilizing this.

Of the method of using the instruction address adder 13, the branch destination instruction advance read function and the advance operation function in the conventional information processing apparatus will be described below.

(Branch Destination Instruction Preceding Read Function) First, the case where the branch destination instruction leading read is executed in the conventional information processing apparatus will be described. In the time chart shown in FIG. 4, the L instruction and the BC instruction are consecutive, and the general register indicated by the R1 field changed by the L instruction does not match the general register indicated by the X2 or B2 field of the BC instruction. The pipeline flow is shown when the branch of the BC instruction is taken at time.

In the information processing apparatus shown in FIG. 2, the instruction register includes two instruction registers, that is, the instruction register 4 for the preceding instruction and the instruction register 5 for the subsequent instruction. And
As mentioned above, the preceding L instruction is not a branch instruction,
Moreover, since the general-purpose register number indicated in the R1 field of the preceding L instruction and the general-purpose register number indicated in the X2 or B2 field of the following BC instruction do not match, the branch destination instruction preceding read is possible.

That is, in the second cycle of FIG. 4, the D stage of the L instruction of the instruction register 4 for the preceding instruction and the BC instruction of the instruction register 5 for the subsequent instruction is started. For the BC instruction not satisfying the above conditions, the processing of the D stage is started in the third cycle which is delayed by one cycle.

The L instruction input to the pipeline is input to the operand address adder 9 to be processed in the A stage, and as described above, the processing of T, B, L and E is performed. On the other hand, a BC instruction (preceding read of branch destination instruction is possible) input to the pipeline at the same time as the L instruction is input to the instruction address adder 13 and processed in the A stage. Is done. The adder input select signal generation circuit 17 calculates the branch destination address of the BC instruction in response to the detection of the branch instruction by the branch instruction detection circuit 7, and thus the instruction address adder 13
Selectively control input to.

As described above, since the BC instruction (branch destination instruction read-ahead) can be started from the second cycle, the branch destination instruction of the BC instruction, instruction 3, is input to the pipeline from the seventh cycle, and the normal operation is performed. It is inserted into the pipeline one cycle earlier than the BC instruction.

As described above, the activation condition of the branch destination instruction preceding read function is that the instruction stored in the instruction register 4 for the preceding instruction is not the branch instruction but the instruction stored in the instruction register 5 for the subsequent instruction branches. It is time to order.

(Preceding Calculation Function) In order to compare the case where the preceding calculation is possible and the case where the preceding calculation is not possible, first, the case where the preceding calculation is impossible will be described.

The time chart shown in FIG. 5 shows the L instruction and the B instruction.
The C instruction is continuous and the L instruction changes the general-purpose register indicated by the R1 field and the BC instruction X2 or B.
General-purpose registers indicated by 2 fields match, and
The pipeline flow when a branch of a BC instruction is taken is shown.

The L instruction writes the data in the main memory designated by the second operand into the general-purpose register designated by the first operand. As the data to be written, the result obtained in the E stage of the seventh cycle is transferred to the general-purpose register 8 in the eighth cycle, and is written in the general-purpose register 8 in the ninth cycle. Although the BC instruction is input to the pipeline in the third cycle, the branch destination address cannot be calculated until the writing of the L instruction to the general register is completed. Therefore, the branch destination address calculation of the BC instruction can be executed in the 10th cycle. After that, the instruction 3 of the branch destination instruction is the first
It is put into the pipeline from 4 cycles.

The case where the preceding calculation is possible is as follows. FIG. 6 shows a pipeline flow when the L instruction is changed to the LA instruction in the instruction sequence shown in FIG. 5, and the instruction address adder 13 executes the preceding operation.

The LA instruction is an instruction for writing the address value designated by the second operand to the general-purpose register designated by the first operand, and unlike the L instruction, it does not require the data in the main memory, so that the instruction address adder is used. In 13, it is possible to process the preceding calculation. In this process, the operation result of the second operand of the LA instruction by the instruction address adder 13 is obtained in the third cycle and stored in the preceding operation result register 16.

In the fourth cycle, the adder input select signal generation circuit 17 stores the general-purpose register number to be used for the calculation of the branch destination address of the BC instruction and the general-purpose storage destination register of the operation result stored in the preceding operation result register 16. When the coincidence of the numbers is detected, the data of the preceding operation result register 16 is controlled to be selected instead of the general-purpose register 8 and is supplied to the instruction address adder 13 so that the branch destination address of the BC instruction can be calculated. Instruction 3 of the branch destination instruction is input to the pipeline from the eighth cycle.

Comparing FIG. 5 and FIG. 6, it can be seen that the preceding operation function of FIG. 6 reduces the overhead of 5 cycles. The activation condition of the preceding operation function described above is when the instruction stored in the instruction register 4 for the preceding instruction is not a branch instruction and does not require the data in the main storage device. When the instruction stored in the instruction register 5 for the subsequent instruction is not a branch instruction, the preceding operation function is activated and there is no problem.
However, when the subsequent instruction is a branch instruction as in the instruction sequence described in FIG. 6, it conflicts with the activation condition of the branch destination instruction preceding read function described above. Then, when the activation conditions conflict, the conventional information processing apparatus controls to execute the preceding calculation function, as shown in FIG.

The time chart shown in FIG. 7 shows the LR instruction,
When the BC instruction is continuous and the general register indicated by the R1 field changed by the LR instruction does not match the general register indicated by the X2 or B2 field of the BC instruction,
Moreover, the pipeline flow when the branch of the BC instruction is taken is shown.

In the second cycle of FIG. 7, the LR instruction is stored in the instruction register 4 for the preceding instruction, and the BC instruction is stored in the instruction register 5 for the subsequent instruction in the third cycle. Since the preceding LR instruction is not a branch instruction and does not require the data in the main storage device, the general register indicated by the R1 field of the preceding LR instruction and the following BC instruction X2.
Alternatively, the preceding operation function is controlled regardless of whether the general-purpose register indicated by the B2 field matches.

Therefore, the instruction string read of the branch destination instruction of the BC instruction is not started from the second cycle as shown in FIG. 4 described above, but is started from the third cycle (that is, the branch destination instruction preceding read is not performed. ), The instruction 3 which is the branch destination instruction of the BC instruction is input to the pipeline from the eighth cycle.

The above-mentioned conventional techniques are disclosed, for example, in Japanese Patent Laid-Open Nos. 62-262141 and 63-195.
No. 736.

[0049]

Even if the preceding operation function is executed as described above, the general-purpose register indicated by the R1 field of the preceding LR instruction and the following X2 of the BC instruction.
Alternatively, when the general-purpose registers indicated by the B2 field do not match, the preceding operation function has no effect. In such a case, the performance is improved by executing the branch target instruction advance read function, but the conventional information processing device cannot activate the branch target instruction advance read function, and the pipeline flow shown in FIG. Therefore, there is a problem that the processing speed of the pipeline cannot be improved.

An object of the present invention is to perform information processing in which the processing speed of a pipeline is improved by selecting and using either a preceding operation or a branch destination instruction preceding read in an unused cycle of the instruction address adder. To provide a device.

[0051]

In order to achieve the above object, according to the present invention, an instruction buffer means for temporarily holding an instruction sequence sequentially read from a memory, and an instruction fetched sequentially from the instruction buffer means. First instruction fetching means for activating a pipeline process, second instruction fetching means for fetching an instruction following the instruction fetched by the first instruction fetching means from the instruction buffer means, and a branch destination address A branch destination address adding means, a means for holding a result calculated by the branch destination address adding means and supplying the result to the branch destination address adding means, and an instruction fetched by the first instruction fetching means can be pre-calculated. A second instruction, a means for detecting that the instruction fetched by the second instruction fetching means is a branch instruction, and a second instruction In the pipeline type information processing apparatus, a means for executing at least a part of the processing of the branch instruction fetched by the instruction fetching means in parallel with the pipeline processing of the preceding instruction, When the instruction fetched by the instruction fetching means is a first instruction that does not use data in the main memory and the instruction fetched by the second instruction fetching means is a branch instruction, the branch destination address adding means On the other hand, a second instruction that instructs the branch destination instruction read-ahead and the instruction fetched by the first instruction fetching means does not use the data in the main memory.
When the instruction fetched by the second instruction fetching means is a branch instruction, the branch destination address adding means is provided with means for instructing a preceding operation.

As described above, the main function of the adder for calculating the instruction address is to calculate the branch destination address when the preceding instruction is a branch instruction. However, with this function alone, the adder for calculating the instruction address is not used when the preceding instruction is other than the branch instruction. The instruction address adder usage determination circuit detects that the preceding two consecutive instructions are not branch instructions and the subsequent instructions are branch instructions, or the general instructions and the subsequent instructions that the preceding instructions change are used. It is detected that the general-purpose registers are matched, and one of the preceding operation function and the branch destination instruction preceding read function is selected. As a result, the adder for calculating the instruction address can be effectively used, and the processing time of the instruction sequence can be shortened.

[0053]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be specifically described below with reference to the drawings. FIG. 1 shows the configuration of a pipeline type information processing apparatus according to an embodiment of the present invention. FIG.
FIG. 6 is a diagram illustrating a pipeline flow of the present invention.
In FIG. 1, reference numeral 18 is an instruction address adder use method determination circuit provided by the present invention. The other constituent elements are the same as those in FIG. 2, and therefore their explanations are omitted.

Instruction address adder usage decision circuit 18
One of the inputs is connected to the output of the instruction register 4 for the preceding instruction, and the other input is connected to the instruction register 5 for the subsequent instruction.
Are connected to each other, and the output 18A of the determination circuit 18 is input to the adder input select signal generation circuit 17. The instruction address adder usage determination circuit 18 provided by the present invention is a circuit that determines the contents to be calculated by the instruction address adder 13 based on the instruction register 4 for the preceding instruction and the instruction register 5 for the subsequent instruction.

Further, the instruction address adder usage determination circuit 18 is provided with a circuit for decoding the instruction code of the preceding instruction stored in the instruction register 4 for the preceding instruction, and the LR instruction and LA instruction shown in FIG. Etc., and a logic circuit for deciding the usage of the instruction address adder based on the recognized instruction code is also provided.

As described above, when the instruction address adder input select signal generating circuit 17 satisfies only one of the starting conditions of the preceding operation function and the branch destination instruction preceding read function, the condition is satisfied. The instruction address adder 13 controls the calculation.

The present invention is characterized in that it is provided with a judging circuit for determining how to use the instruction address adder 13 when both the starting condition of the preceding operation function and the starting condition of the branch destination instruction preceding read function are satisfied. The determination of the method of use will be described below.

When the activation conditions for both the preceding operation and the preceding read of the branch destination instruction are satisfied, the prior art executes the preceding operation regardless of the contents of the instruction, as described above. Therefore, even if the general-purpose register changed by the preceding instruction is not used for the address calculation of the subsequent branch instruction, the branch destination instruction precedent reading is not performed, so that the processing time can be shortened as shown in the time chart of FIG. What cannot be achieved is as described above.

By the way, in the general instruction sequence, the general-purpose register R1 changed by the LR instruction and the general-purpose register X2 used for calculating the branch destination address of the branch instruction following the LR instruction.
Or B2 rarely competes. On the other hand, LA
The general-purpose register R1 changed by the instruction often coincides with the general-purpose register X2 or B2 used for calculating the branch destination address of the branch instruction.

The present invention pays attention to this point, and the instruction stored in the instruction register 4 for the preceding instruction is the LR instruction, and the instruction stored in the instruction register 5 for the subsequent instruction is the branch instruction.
When the activation conditions for both the preceding operation and the branch destination instruction read-ahead are satisfied, the branch destination instruction read-ahead is executed as shown in FIG. When the instruction stored in the instruction register 4 for the preceding instruction is the LA instruction and the instruction stored in the instruction register 5 for the subsequent instruction is the branch instruction, the preceding operation is executed as shown in FIG.

That is, in the instruction address adder usage determining circuit 18, when the instruction stored in the instruction register 4 for the preceding instruction is the LR instruction, the value (for example, bit 1) indicating the branch destination instruction preceding reading is given to the line 18A. Output to LA
In the case of an instruction, a value indicating the preceding operation (for example, bit 0) is output to the line 18A and given to the adder input select signal generation circuit 17. Therefore, when the preceding instruction is the LR instruction and the subsequent instruction is the BC instruction, the adder input select signal generation circuit 17 causes the instruction address adder 13 to execute as the branch destination instruction preceding read function, and therefore, as shown in FIG. In addition, the processing of the BC instruction is started one cycle earlier, and the branch destination instruction sequence, instruction 3, is input to the pipeline in the seventh cycle.

As described above, in the present embodiment, the instruction address adder can be effectively used when both the preceding operation and the branch destination instruction preceding read are satisfied.
The processing speed of the information processing device can be improved.

By the way, in the case where the LR instruction and the BC instruction are consecutive, the general-purpose register R1 changed by the LR instruction
And the general-purpose register X2 or B2 used for calculating the branch destination address of the BC instruction may collide. In such a case, the branch-destination instruction read-ahead is executed, but the branch-destination address cannot be calculated until the general-purpose register R1 to be changed by the LR instruction is obtained. The time chart in this case is the same as that in which the L instruction in FIG. 5 is replaced with the LR instruction.

Further, in the case where the LA instruction and the BC instruction are consecutive, the general-purpose register R1 changed by the LA instruction,
The general-purpose register X2 or B2 used for calculating the branch destination address of the BC instruction may not match. In such a case, the preceding operation is executed and the result of the LA instruction is written in the preceding operation result register, but the general-purpose register R1 changed by the LA instruction is not used for calculating the branch destination address.
The time chart in this case is the same as that in FIG. 6, and is the same regardless of the collision of general-purpose registers.

Therefore, another embodiment for determining how to use the instruction address adder will be described. In the instruction address adder usage determination circuit 18, the number of the general-purpose register changed by the instruction stored in the instruction register 4 for the preceding instruction,
It is detected whether or not the numbers of the general-purpose registers used for the address calculation of the subsequent branch instruction stored in the instruction register 5 for the subsequent instruction match. The instruction address adder usage determination circuit 18 uses the output signal 18A (for example, bit 1) to execute the preceding arithmetic function when the number of the general-purpose register matches the adder input select signal generation circuit 17. If it is reported and the numbers of the general-purpose registers do not match, the execution of the branch destination instruction preceding read function is output signal 18A.
(For example, bit 0).

When the preceding operation function is executed, the time chart shown in FIG. 6 is obtained, and the instruction following the instruction 0 is L
Not only the A instruction but also the LR instruction and the like have the same time chart. As compared with the case where the preceding operation in FIG. 5 is not executed, the branch destination instruction, instruction 3, is inserted into the pipeline 6 cycles earlier.

On the other hand, when executing the branch destination instruction read-ahead function, the time chart shown in FIG.
The instruction following the instruction 0 is not limited to the LR instruction, but the LA instruction or the like has the same time chart. As compared to the case where the branch destination instruction read-ahead in FIG. 7 is not executed, the instruction 3 of the branch destination instruction is 1
It is put into the pipeline early in the cycle. As a result, in this embodiment, the instruction address adder is effectively used, and the processing speed of the information processing device can be improved.

[0068]

As described above, according to the present invention, by controlling the method of using the instruction address adder, the number of the general-purpose register to be changed by the instruction and the number of the general-purpose register necessary for the address calculation are determined. It is possible to reduce the address calculation overhead when the addresses match or the overhead of reading the branch destination instruction when the general-purpose register numbers do not match, and to improve the processing speed of the information processing device.

[Brief description of drawings]

FIG. 1 shows the configuration of a pipeline type information processing apparatus according to an embodiment of the present invention.

FIG. 2 shows a configuration of a conventional information processing device.

FIG. 3 shows an example of instructions used.

FIG. 4 is a diagram for explaining a pipeline flow of a branch destination instruction preceding read executed by an instruction address adder in the related art.

FIG. 5 is a diagram for explaining a pipeline flow in the case where the instruction address adder cannot execute the preceding operation in the related art.

FIG. 6 is a diagram for explaining a pipeline flow in the case where an instruction address adder can execute a preceding operation in the conventional technique.

FIG. 7 is a diagram for explaining a pipeline flow in the case where the start condition of the preceding operation function and the branch destination instruction preceding read function compete in the instruction address adder in the prior art.

FIG. 8 is a diagram illustrating a pipeline flow of the present invention.

[Explanation of symbols]

 1 instruction buffer register 2 instruction cutout aligner A 3 instruction cutout aligner B 4 instruction register for preceding instruction 5 instruction register for subsequent instruction 6 instruction calculation circuit for preceding instruction 7 branch instruction detection circuit 8 general-purpose register 9 operand address adder 10 TLB for operand 11 Operand Buffer Storage Device 12 Operation Unit 13 Instruction Address Adder 14 Instruction TLB 15 Instruction Buffer Storage Device 16 Preceding Operation Result Register 17 Adder Input Select Signal Generation Circuit 18 Instruction Address Adder Usage Determination Circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akihiro Nakatani 5-22-1 Kamisuihoncho, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Co., Ltd. (72) Inventor Tsukasa Inoue 1 Horiyamashita, Horiyamashita, Hadano-shi, Kanagawa

Claims (1)

[Claims] 1. An instruction buffer means for temporarily holding an instruction sequence sequentially read from a memory, a first instruction fetch means for fetching instructions from the instruction buffer means and activating pipeline processing, and a first instruction fetch means. A second instruction fetching means for fetching an instruction following the instruction fetched by the first instruction fetching means from the instruction buffer means, a branch destination address adding means for obtaining a branch destination address, and the branch destination address adding means. A means for holding the operation result and supplying it to the branch destination address adding means, a means for detecting that the instruction fetched by the first instruction fetching means is a precalculable instruction, and a second instruction Means for detecting that the instruction fetched by the fetching means is a branch instruction, and less processing of the branch instruction fetched by the second instruction fetching means. In the pipeline type information processing apparatus, at least a part of the processing includes means for executing the pipeline processing of the preceding instruction in parallel.
When the instruction fetched by the instruction fetching means is a first instruction that does not use data in the main memory and the instruction fetched by the second instruction fetching means is a branch instruction, the branch destination address adding means On the other hand, a second instruction that instructs the branch destination instruction read-ahead and the instruction fetched by the first instruction fetching means does not use the data in the main memory.
And the instruction fetched by the second instruction fetching means is a branch instruction, the branch destination address adding means is provided with means for instructing a preceding operation. apparatus.