JP3493110B2 - High-speed branch processing unit - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an improvement in operating frequency.
The present invention relates to a high-speed branch processing device that enables

[0002]

2. Description of the Related Art In recent years, with the advent of the multimedia era, real-time image processing has become very important in moving image processing represented by MPEG (Moving Picture Experts Group) processing. Since such moving image processing deals with image data, the amount of data to be processed is enormous, and therefore, a very large processing capability is required for the microprocessor. Further, if all the processing is performed by hardware, an increase in cost is unavoidable. Therefore, if possible, it is desirable to perform some or all of the processing by software using a general-purpose microprocessor, and therefore, more and more. There is a situation where it is desired to improve the processing capability of the microprocessor. In addition, PDA (Person
Similarly, high-speed processing is required for mobile devices such as al Digital Assistance), but it is also important to reduce power consumption in these devices.

There are roughly three important factors that determine the processing capability of a microprocessor: the operating frequency, the number of executed instructions, and the number of cycles per instruction. For example, the operating frequency is typically determined by the critical path (cr
It is determined by the delay time of itical path), but in microprocessors, instruction fetch is often a critical path, especially when the condition is met during execution of a conditional branch instruction.

Here, a typical RISC (Reduced Inst
ruction set computer) MIPS C which is a processor
omp. Systems, Inc. A case where the above instruction fetch becomes a critical path will be described by taking R3000 of FIG.

The instruction fetch when the condition is satisfied when the conditional branch instruction is executed is a conditional branch instruction (bne, beq, etc.).
It is performed by comparing the registers at the operation stage of, and after the comparison result is confirmed, reading the instruction for the branch destination address from the instruction memory and fetching it into the instruction register, but this processing is executed in the same cycle, so it is critical. It is often a pass. The flow of data and control signals in the above instruction fetch will be described below with reference to the drawings.

FIG. 11 is a block diagram of a conventional branch processing device. This branch processing device uses a pipeline method, which is a technique for reducing instruction execution time, and includes a program counter 1 for storing an address of an instruction currently being executed, an instruction memory 3 for storing an instruction, and an instruction memory. An instruction register 5 in which the instruction read from 3 is fetched,
An instruction decoder 7 that decodes the instruction set in the instruction register 5 to generate various control signals, an adder 9, a branch destination address register 11 that captures the branch destination address output from the adder 9, and a conditional branch instruction A register file 13 including a plurality of registers (not shown) for storing contents to be compared, and an ALU (Arithmetic and Logic U)
nit; arithmetic and logic unit 15), input registers 17a and 17b of the ALU 15, and a selector 19.

In the conventional branch processing device having such a configuration, first, in the F stage (fetch stage),
An instruction (conditional branch instruction) is read from the instruction memory 3,
It is taken into the instruction register 5.

Next, in the D stage (decode stage), the instruction in the instruction register 5 is decoded by the instruction decoder 7 and each control signal for performing address calculation is output. The branch destination address is obtained by adding the index value specified in the instruction and the address stored in the program counter 1 by the adder 9, and the branch destination address is stored in the branch destination address register 11. At the same time, the values stored in the two registers to be compared are fetched from the register file 13 into the input registers 17A and 17B of the ALU 15 by the control signal given from the instruction decoder 7.

Next, in the E stage (execution stage), the ALU 15 inputs the two values stored in the input registers 17A and 17B and obtains the operation result. The result of this operation becomes a control signal for branch determination, and the address indicated by the program counter 1 which is the read address of the instruction memory 3 when the branch is not taken and the branch destination address which is the read address of the instruction memory 3 when the branch is taken One of the branch destination addresses stored in the register 11 is selected through the selector 19 based on the operation result which is the control signal. If the branch is taken, the branch destination address of the instruction memory 3 is accessed, the branch destination instruction is read out, and stored in the instruction register 5 in the same manner as described above.

As described above, in the conventional branch processing device, when a conditional branch instruction is executed, an ALU operation for branch determination in the same cycle and a cache read of a branch destination instruction when the branch is taken. Since it is necessary to perform the processing of 1 and 3 in series, the delay of this path is large and it often becomes a critical path. Therefore, when executing a conditional branch instruction, the instruction fetch when the branch is taken becomes a bottleneck, and it is very difficult to raise the operating frequency.

[0011]

As described above, in the conventional branch processing device, the pipeline structure is such that the branch judgment must be made in the same cycle, and subsequently the instruction to the branch destination address must be fetched. If this is the case, this path becomes a critical path, and the operating frequency of the microprocessor as a whole cannot be raised sufficiently.

The present invention has been made in view of the above circumstances.
And its purpose is to enable an increase in operating frequency,
In addition, high-speed components that can also reduce power consumption
The purpose is to provide a processing unit.

[0013]

In order to achieve the above object, a first feature of the present invention is to provide an instruction memory for storing instructions, a program counter for holding an address to the instruction memory, and the instruction memory. In a high-speed branch processing device including an instruction register for storing an instruction read from and decoded from the instruction memory, a read control means for reading a predetermined number of instructions with consecutive addresses from the instruction memory at once, and the read control means. Two instruction buffers for temporarily storing a plurality of instructions read from the instruction memory, and one of the two instruction buffers selected, and a plurality of instruction buffers stored in the selected instruction buffer. An instruction buffer selecting unit for selecting any one of the instructions and outputting the instruction to the instruction register, When the start address of said plurality of instructions by program counter is specified, reads a first plurality of instructions that from said read control means said instruction memory, said first plurality of instructions of the two instructions when stored towards old last access time of the buffer, the instruction buffer selecting means is output to the instruction register to the first plurality of instructions in the address order, the decoded instruction is a conditional branch instruction Is the address of consecutive addresses including the branch destination address before the conditional branch judgment is completed.
The read control means reads a second plurality of instructions from the instruction memory, and the second plurality of instructions is read by the second controller.
One of the stores in the older of the last access time of the instruction buffer, co if the instruction buffer selection means outputs to the instruction register to the second plurality of instruction address order
The address allocation of the instruction stored in the instruction memory is
Read multiple instructions of 1 and read multiple instructions of 2
A high-speed branch processing device whose protrusion does not match
The main point is that it is a table .

According to the above configuration, the fetch processing of the branch destination address when the branch is taken in the conditional branch instruction which often becomes the critical path can be speeded up without increasing the cost. Therefore, the operating frequency of the microprocessor can be improved.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

Here, the high-speed branch processing device according to the present embodiment basically has the following five-stage (five-stage) pipeline configuration, for example, MIPS Comp. Sy
stems, Inc. General R such as R3000
This is a pipeline configuration used in the ISC processor.

(1) F stage (fetch stage):
This is a stage for inputting an instruction that fetches the instruction from the memory (cache) and sets it in the instruction register. (2) D stage (decode stage): This stage decodes the instruction on the instruction register and generates each control signal. (3) E stage (execution stage): executes an operation.
Alternatively, it is a stage for generating an address for access to the memory (cache). (4) M stage (memory stage): This is a stage for accessing the memory (cache). (5) WB stage (write back stage): a stage for writing data to the register.

First Embodiment FIG. 1 is a block diagram of a high-speed branch processing device according to this embodiment. In FIG. 1, a high-speed branch processing device according to the present embodiment has a program counter 1 for storing the address of an instruction currently being executed and an instruction memory 3 for storing the instruction.
And an instruction register 5 for fetching the instruction read from the instruction memory 3, and an instruction decoder 7 for decoding the instruction set in the instruction register 5 and generating various control signals.
A register file 13 including an adder 9, a branch destination address register 11 for fetching a branch destination address output from the adder 9, and a plurality of registers (not shown) for storing contents to be compared with the conditional branch instruction. , ALU (Arit
hmetic and Logic Unit) 15 and
Input registers 17a and 17b of the ALU 15, a selector 19 for selecting one of the address indicated by the program counter 1 and the branch destination address stored in the branch destination address register 11, and a plurality of consecutive memory read from the instruction memory 3. Of the two instructions selected by the selectors 23A and 23B, the instruction buffers 21A and 21B for fetching the instruction of, the selectors 23A and 23B for selecting one of the plurality of instructions fetched in the instruction buffers 21A and 21B, and Selector 25 for selecting either
And a branch instruction flag register 29 for fetching a branch instruction flag output from the instruction decoder 7, and a control circuit 27 for controlling the selector 25.

Here, from the instruction memory 3 to the instruction buffer 2
1A and instruction buffer 21B fetches instructions by LR
It is executed by the U (Least Recently Used) method. L
The RU method is a method of fetching an instruction in the older one of the instruction buffers 21A and 21B at the time of the last fetch.

Next, the operation of the high-speed branch processing device according to this embodiment will be described. First, reading of the instruction memory 3 shown in FIG. 1 will be described with reference to FIG.
FIG. 2 is a conceptual diagram showing the read operation of the instruction memory 3 shown in FIG. 1, and when the read signal is in the Enable state, a plurality of instructions at consecutive addresses including the designated address are read at once. The number of instructions read at one time is arbitrary, but is four in FIG. 2, for example.

There are two cases where the read signal is in the Enable state. One is when the address stored in the program counter 1 of FIG. 1 comes to the address boundary of a plurality of instructions which are read at a time, and the other. One is when fetching an instruction at a branch destination address by a branch instruction.

When the address of the program counter 1 reaches the address boundary of a plurality of instructions which are read at once, for example, in the instruction sequence in which there is no branch instruction in the instruction sequence as shown in FIG. Counter 1
When the address of "8008000" indicates that the read signal is in the Enable state, the address is "8000800".
0 "," 80008004 "," 800008008 ",
Four instructions of "8000800c" are read at one time. After that, when the pipeline progresses and the address of the program counter 1 indicates "80008010", the read signal becomes the enable state again and the address becomes "8.
"0008010", "80008014", "8000
Similarly, four instructions “8018” and “8000801c” are read at once. In this way, the instruction memory 3
The access to the instruction memory 3 is reduced as compared with the conventional case because the address of the program counter 1 is read at the address boundary of four instructions which are read at once.

On the other hand, the case of fetching the instruction of the branch destination address by the branch instruction is, for example, the following case. When the address of the program counter 1 indicates "8008000" in the sequence of instructions having a branch instruction in the instruction sequence as shown in FIG. 3B, the read signal is in the enable state as in FIG. "8
00080000 "," 80008004 "," 8000
Four instructions "8008" and "8000800c" are read at one time. At this time, if the read instruction includes a branch instruction (instruction with address “80008004”), the branch instruction is executed and the branch destination instruction (instruction with address “800008104” indicated by target in the figure) is read. However, even in this case, the read signal is in the Enable state. Further, when the instruction of the branch destination is not on the above-mentioned address boundary as shown in FIG. 3A, four instructions including the branch destination instruction whose address is “800008104”, that is, the address “80008100”, "800
08104 "," 80008108 "," 800081 "
Four instructions of "c" are read at one time. In this way, consecutive addresses with the address of the branch destination instruction as the start address are “800008104”, “800008108”,
Instead of the four instructions “80081c” and “80008200”, the address including the branch destination instruction is “80008c”.
100 "," 80008104 "," 80000810 "
The four instructions “8” and “80081c” are read at a time because the instruction of the instruction memory 3 is implemented.
This can be facilitated.

Next, FIG. 1 shows the flow of data and control signals until the instruction of the conditional branch instruction is fetched, the conditional branch instruction is executed, and the instruction at the branch destination is fetched in the high-speed branch processing apparatus according to the present embodiment. The description will be made with reference. Here, as a precondition, it is assumed that the program counter 1 currently indicates the head addresses of four instructions read at one time, and the instructions stored at the head addresses are conditional branch instructions. To do. However, it is assumed that the preceding two instructions are not branch instructions. Further, although the virtual address and the physical address are the same, the contents of the present invention do not change even if address conversion is required.

First, in the F stage (fetch stage), the address indicated by the program counter 1 and the branch destination address stored in the branch destination address register 11 are input to the selector 19 and either one of them is controlled by the control signal a. To be selected. The control signal a is a signal indicating whether or not the preceding instruction, that is, the instruction at the E stage (execution stage) is a branch instruction.
Reference numeral 9 selects the branch destination address stored in the branch destination address register 11 when the control signal a indicates that the preceding instruction is a branch instruction, and selects the address indicated by the program counter 1 when it indicates that it is not a branch instruction. select. Here, since the preceding two instructions are not branch instructions according to the above-mentioned preconditions, the address indicated by the program counter 1 is input to the instruction memory 3 by the control signal a as the read address. Further, since that address is the start address of the address boundary according to the precondition, the read signal of the instruction memory 3 is in the Enable state, and it follows the address indicated by the program counter 4
Instructions are read from the instruction memory 3. The four instructions read from the instruction memory 3 are loaded into the instruction buffer 21A or 21B. The selection of the instruction buffer for fetching the read instruction is executed by the above-mentioned LRU method. For example, if the last fetch in the previous cycle of the instruction buffer 21A is older, the fetch signal c input to the instruction buffer 21A is in the Enable state, and the fetch signal d input to the instruction buffer 21B is Disabl.
The state becomes e, and as a result, the read instruction is taken into the instruction buffer 21A.

Then, the four instructions stored in the instruction buffer 21A are sent to the selector 23A and the instruction buffer 21
The four instructions stored in B are input to the selector 23B, and one instruction at the address specified by the control signals e and f is selected. The two instructions selected by each selector are output to the selector 25. The selector 25 outputs 2 according to the control signal g output from the control circuit 27.
Instruction register 5
Output to. The control circuit 27 receives a conditional branch determination signal h, which is the operation result of the ALU circuit 15 in the E stage (execution stage), a control signal a indicating that the instruction in the E stage (execution stage) is a branch instruction, and an instruction buffer. Two
A control signal i indicating which one of 1A and 21B is the last fetched instruction is input, and it is determined that the instruction at the E stage (execution stage) is a non-branch instruction or the branch instruction is a branch taken instruction. In this case, of the two instruction buffers, fetching selects the newer buffer in the current cycle, and when the E stage (execution stage) instruction is determined to be a non-branch by a branch instruction, the oldest one in the current cycle is selected. A control signal g for selecting a buffer is generated and output to the selector 25. Since it is assumed here that there is no branch instruction in the E stage (execution stage) as a precondition, as a result, the instruction output from the instruction buffer 21A whose fetch is the latest in the current cycle is the selector. 25, the instruction register 5
Is taken into.

Next, in the D stage (decode stage), the instruction decoder 7 decodes the instruction stored in the instruction register 5 to generate various control signals. The instruction decoder 7 outputs the index value in the instruction to the adder 9, and the adder 9 adds the index value and the address indicated by the program counter 1 to determine the branch destination address. The branch destination address is fetched in the branch destination address register 11, and at the same time, the branch instruction flag indicating that the instruction is a branch instruction is fetched in the branch instruction flag register 29. On the other hand, the instruction decoder 7 inputs the control signal j to the register file 13 to make a conditional branch decision at the next E stage (execution stage). Register file 1
3 reads the values of the corresponding two sets of registers, and ALU1
5 in the input registers 17A and 17B.

Next, in the E stage (execution stage), the arithmetic operation is executed in the ALU 15, and the arithmetic result h is output. Here, the feature of the present invention resides in that the following processing is performed at the same time when this calculation is performed, and will be continuously described below.

As described above, the instruction decoder 7 outputs a branch instruction flag indicating that the input instruction is a branch instruction to the register 29. In response to this branch instruction flag, the read signal b of the instruction memory 3 is enabled. It becomes a state. That is, in the conventional technique shown in FIG. 7, the read signal is enabled only when the branch is taken based on the result of the operation, waiting for the completion of the operation of the ALU 15 in the E stage (execution stage). Then E
When the stage (execution stage) instruction is a branch instruction, the read signal b is
It will be in the Enable state. Therefore, the instruction at the branch destination address is read without waiting for the completion of the operation by the ALU 15. On the other hand, the branch destination address fetched in the branch destination address register 11 and the address indicated by the program counter are both input to the selector 19, and the branch destination address is set by the control signal a based on the branch instruction flag stored in the branch instruction flag register 29. Is selected and output to the instruction memory 3. Therefore, this branch destination address becomes the read address for the instruction memory 3. Then, four consecutive instructions including the branch destination address are stored in the instruction memory 3
Read from. The four instructions read from the instruction memory 3 are loaded into the instruction buffer 21A or 21B. The selection of the instruction buffer for fetching the read instruction is executed by the above-mentioned LRU method. Instruction buffer 2
When the last fetch in the previous cycle is older in 1B, the fetch signal input to the instruction buffer 21B is in the Enable state and the fetch signal input to the instruction buffer 21A is in the Disable state, and as a result, it is read. The instruction will be fetched into the instruction buffer 21B.

Then, the four instructions stored in the instruction buffer 21A are stored in the selector 23A and stored in the instruction buffer 21B.
The four instructions stored in are input to the selector 23B, and one instruction at the address specified by the control signals e and f is selected. 2 selected by each selector
This instruction is output to the selector 25. The selector 25 selects one of the two instructions according to the control signal g output from the control circuit 27 and outputs it to the instruction register 5. Here, if the conditional branch is established, the control circuit
27 generates a control signal g for selecting the buffer of the two instruction buffers that has been fetched later, so that the branch destination instruction is selected and output to the instruction register 5.

As described above, conventionally, the condition judgment of the conditional branch instruction is made after the ALU operation for branch judgment at the E stage (execution stage) is completed and the branch is judged from the result of the operation. According to the present embodiment, when the instruction at the branch destination address when taken is satisfied, the result of the ALU operation at the next E stage (execution stage) when the instruction at the D stage (decode stage) is a conditional branch instruction. Run independently without waiting for
The instruction at the branch destination address is read from the instruction memory 3 regardless of whether the condition determination is satisfied or not satisfied.
Since the LU operation is hidden by the instruction memory reading process, the instruction at the branch destination can be fetched at high speed. Therefore, in the microprocessor, the fetching of the branch destination instruction when the branch is taken by the conditional branch instruction that tends to become the critical path can be executed at high speed without increasing the cost. Thereby, the operating frequency of the microprocessor can be improved.

Here, FIG. 4 is a timing chart showing the fetch operation of the branch destination instruction, and FIG.
The operation of the conventional branch processing device shown in
FIG. 3B shows the operation of the branch processing device according to the present embodiment shown in FIG. As shown in FIG. 4A, in the conventional branch processing device, the ALU 15 is operated at times t _{1 to} t ₂ .
Instruction register operation, selected by the selector 19 at time t ₂ ~t _3, read instructions from the instruction memory 3 at time t ₃ ~t _4, at time t ₄ ~t ₅ by 5
Commands are being sequentially fetched into. On the other hand, FIG.
(B), the branched processing apparatus according to this embodiment, the time T ₁ through T reading of instructions from the instruction memory 3 in _2, selected by the selector 25 at time T ₂ through T _3, time T ₃ Although instructions are sequentially fetched into the instruction register 5 at T _{4 to} T ₄ , the operation by the ALU 15 (the period indicated by A in the figure) is executed during the period in which the instructions are read from the instruction memory 3 and is apparent. It is hidden in the reading of the instruction from the upper instruction memory 3. Therefore, as apparent from FIGS. 4A and 4B, the operating frequency can be increased in this embodiment.

Second Embodiment A high-speed branch processing device according to the present embodiment stores the conditional branch instruction stored in the instruction memory 3 shown in FIG.
In the two cases in which the read signal is in the Enable state, that is, when the address stored in the program counter 1 in FIG. 1 comes to the address boundary of a plurality of instructions to be read at once, and the instruction of the branch destination address by the branch instruction. Are arranged at addresses that do not match when fetching.

By arranging the instructions of the execution program stored in the instruction memory 3 as described above, the conflict between the read by the address boundary and the read by the branch instruction execution which occurs in the first embodiment is avoided. be able to. Therefore, high-speed branch processing can be realized without increasing the hardware cost.

This is because, as shown in FIG. 5A, a branch instruction (address "800008008" indicated by branch in the figure) is used.
When the branch instruction reaches the E stage (execution stage), the F stage (fetch stage) Since the address indicated by the program counter of is at the beginning address of the address boundary,
In the branch processing device according to the embodiment of the present invention, as described above, contention occurs between the reading by the address boundary and the reading by executing the branch instruction. However, as shown in FIGS. 5B to 5C, the above conflict does not occur by arranging the branch instruction other than the second from the end of the address boundary.

Third Embodiment In the high-speed branch processing device according to the second embodiment described above, by arranging a branch instruction at a position other than the second from the end of the address boundary, reading and execution of the branch instruction at the address boundary are performed. The conflict with the read by is avoided. FIG. 6 shows the above-mentioned two read operations by inserting the nop (No OPeration) instruction so that the branch instruction is placed at a position other than the second from the end of the address boundary, as shown in FIG. 5 (a). FIG. 3 is a diagram showing an address arrangement in which no conflict occurs. By doing so, the above conflict can be avoided, but on the other hand, the code size of the program may increase.

Therefore, in the present embodiment, by adopting a configuration in which the hardware detects the conflict between the two readings and processes the conflict, the program that may occur in the second embodiment is stored. It is possible to avoid the above conflict without increasing the code size.

FIG. 7 is a diagram showing an example of the address arrangement of the execution instructions in the high speed branch processing device according to the present embodiment, and FIG. 7 (a) is a diagram showing a case where it is determined that the branch is taken, FIG. 7B is a diagram showing a case where it is determined that the branch is not taken. In FIGS. 7A and 7B, first, in the D stage (decode stage) of the branch instruction (inst2), there is a conflict between the read of the branch target instruction (insta) and the read of the first instruction (inst4) of the address boundary. To detect. Here, this detection can be easily performed by checking whether the instruction code corresponding to the address of the instruction is a branch instruction. When a conflict is detected, the read of the first instruction (inst4) at the address boundary, which is executed when it is determined that the branch is not taken in the next stage, is suspended and the branch destination instruction (insta) is read. Then, when it is determined that the branch is taken, the process proceeds as it is, as shown in FIG. On the other hand, when it is determined that the branch is not taken, as shown in FIG. 7B, the branch destination instruction (insta) read earlier in the next stage is further invalidated. At the same time, the read of the suspended first instruction (inst4) of the address boundary is executed, and then the process proceeds.

FIG. 8 is a block diagram showing a part of a high-speed branch processing device for performing the above-mentioned processing. This high-speed branch processing device is a program counter 1 and a selector 19 which constitute the high-speed branch processing device shown in FIG. It is configured such that a selector 31 and an adder 33 are further added between and. The other parts are exactly the same as those of the high-speed branch processing device of FIG. In FIG. 8, at the E stage (execution stage) of the branch instruction (inst2), the address stored in the program counter 1 and the branch destination address stored in the branch destination address register 11 are input to the selector 19. here,
As mentioned above, the previous D stage (decode stage)
When a conflict between the read of the branch destination instruction (insta) and the read of the first instruction (inst4) of the address boundary is detected, the branch destination address is preferentially selected by the control signal 1 and the instruction memory (shown in the figure The branch destination address is input as the read address. The branch destination address is also input to the adder 33, and the adder 33 adds (in this case, 4). The addition result and the address stored in the program counter 1 are assigned to the selector 31.
One of them is selected by the control signal k. In the E stage (execution stage), the conditional branch determination is performed at the same time, but when it is determined that the branch is taken (in the case of FIG. 7A), the addition result is selected by the control signal k, The address input to the program counter 1 and designated by the program counter is changed to the above addition result. On the other hand, when it is determined that the branch is not taken (in the case of FIG. 7B), the program counter 1
The address stored in is selected and similarly input to the program counter 1. That is, the address stored in the program counter 1 is held. Further, the branch destination instruction stored in the instruction register (not shown) is invalidated.

Fourth Embodiment In the third embodiment, the branch destination instruction (insta
) And the read of the first instruction of the address boundary (inst4) conflicts, the first instruction of the address boundary (inst4) suspends it, but
In this embodiment, the reading of the branch destination instruction (insta) is suspended.

FIG. 9 is a diagram showing an example of the address arrangement of the execution instructions in the high speed branch processing device according to the present embodiment, and FIG. 9 (a) is a diagram showing the case where the branch is determined to be taken, FIG. 9B is a diagram showing a case where it is determined that the branch is not taken. In FIGS. 9A and 9B, first, in the D stage (decode stage) of the branch instruction (inst2), there is a conflict between the read of the branch destination instruction (insta) and the read of the first instruction (inst4) of the address boundary. To detect. Here, this detection can be easily performed by checking whether the instruction code corresponding to the address of the instruction is a branch instruction. When a conflict is detected, the reading of the branch destination instruction (insta) is suspended at the next stage, and the first instruction (inst4) of the address boundary that is executed when it is determined that the branch is not taken is read. And
When it is determined that the branch is taken, as shown in FIG. 9A, the first instruction (inst4) of the address boundary read earlier in the next stage is invalidated (invali).
date) and the branch target instruction (inst
The reading of a) is executed, and then the process proceeds. on the other hand,
When it is determined that the branch is not taken, the process proceeds as it is, as shown in FIG.

FIG. 10 is a block diagram showing a part of a high-speed branch processing device for performing the above-mentioned processing. This high-speed branch processing device is a program counter 1 and a selector 19 which constitute the high-speed branch processing device shown in FIG. Further, a selector 35 and an adder 37 are added between and. In addition,
The other parts are exactly the same as those of the high-speed branch processing device of FIG. In FIG. 9, at the E stage (execution stage) of the branch instruction (inst2), the address stored in the program counter 1 and the branch destination address stored in the branch destination address register 11 are input to the selector 19. here,
As mentioned above, the previous D stage (decode stage)
When a conflict between the read of the branch destination instruction (insta) and the read of the first instruction (inst4) of the address boundary is detected, the address stored in the program counter 1 is preferentially selected by the control signal n. The address stored in the program counter 1 is input to the instruction memory (not shown) as its read address. The address stored in the program counter 1 is also input to the adder 37, and the adder 37 adds (4 in this case). The result of this addition and the branch destination address are the selector 3
5, and one of them is selected by the control signal m. In the E stage (execution stage), the conditional branch determination is performed at the same time, but when it is determined that the branch is taken (in the case of FIG. 9A), the branch destination address is selected by the control signal m, The address input to the program counter 1 and designated by the program counter is changed to the branch destination address. Furthermore, the first instruction (in the address boundary) stored in the instruction register (not shown)
st4) is invalidated. On the other hand, when it is determined that the branch is not taken (the case of FIG. 9B), the addition result is selected and similarly input to the program counter 1.

[0043]

As described above, according to the present invention,
The fetch processing of the branch destination address can be performed at high speed when the branch of the conditional branch instruction, which is a critical path that limits the operating frequency of the microprocessor, is taken. Further, by reading out a plurality of instructions at once, the number of times of accessing the instruction memory can be reduced, and thus power consumption can be reduced. Furthermore, by providing two instruction buffers for temporarily storing a plurality of read instructions, the instruction memory can be handled by the one-port reading instead of the two-port reading, so that the cost does not increase. .

[Brief description of drawings]

FIG. 1 is a block diagram of a high-speed branch processing device according to a first embodiment of the present invention.

FIG. 2 is a conceptual diagram showing a read operation of the instruction memory shown in FIG.

FIG. 3 is a diagram for explaining a read operation of the instruction memory shown in FIG.

4 is a timing chart showing a fetch operation of a branch target instruction, FIG. 4A shows an operation of the conventional branch processing device shown in FIG. 7, and FIG. 4B is the first branch shown in FIG. 3 illustrates an operation of the high-speed branch processing device according to the embodiment.

FIG. 5 is a diagram for explaining a high-speed branch processing device according to a second embodiment of the present invention.

FIG. 6 is a diagram for explaining a high-speed branch processing device according to a third embodiment of the present invention.

FIG. 7 is another diagram for explaining the high-speed branch processing device according to the third embodiment of the present invention.

FIG. 8 is a block diagram showing a part of a high-speed branch processing device according to a third embodiment of the present invention.

FIG. 9 is a diagram for explaining a high-speed branch processing device according to a fourth embodiment of the present invention.

FIG. 10 is a block diagram showing a part of a high-speed branch processing device according to a fourth embodiment of the present invention.

FIG. 11 is a block diagram of a conventional branch processing device.

[Explanation of symbols]

1 Program Counter 3 Instruction Memory 5 Instruction Register 7 Instruction Decoder 9, 33, 37 Adder 11 Branch Destination Address Register 13 Register File 15 ALU (Arithmetic and Logic Unit) 17A, 17B Input Register 19, 23A, 23B , 25, 31, 35 selectors 21A, 21B instruction buffer 27 control circuit 29 branch instruction flag register

Continuation of front page (56) Reference JP-A-6-161751 (JP, A) JP-A-7-121371 (JP, A) JP-A-4-162134 (JP, A) JP-A-3-156534 (JP , A) JP-A-2-105938 (JP, A) JP-A-63-318634 (JP, A) JP-A-5-224927 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB) Name) G06F 9/38

Claims (3)

(57) [Claims] 1. An instruction memory for storing instructions, a program counter for holding an address to the instruction memory,
A high-speed branch processing device comprising an instruction register for storing an instruction read from the instruction memory and decoded, and a read control unit for reading out a predetermined number of consecutive addresses from the instruction memory at one time, Two instruction buffers for temporarily storing a plurality of instructions read from the instruction memory by the read control means, and one of the two instruction buffers are selected,
An instruction buffer selecting unit that selects any one of the plurality of instructions stored in the selected instruction buffer and outputs the selected instruction to the instruction register; When the start address of each instruction is designated, the read control means reads the first plurality of instructions from the instruction memory, and the first plurality of instructions is read as the last one of the two instruction buffers. The instruction buffer selecting means stores the oldest one at the time of access, outputs the first plurality of instructions to the instruction register in the address order, and determines the conditional branch if the decoded instruction is a conditional branch instruction. Before completion, the read control means reads from the instruction memory a second plurality of instructions at consecutive addresses including the branch destination address, A plurality of instructions are stored in the older one of the two instruction buffers at the time of the last access, and the instruction buffer selecting means outputs the second plurality of instructions to the instruction register in the order of addresses, and A high-speed branch process characterized in that the address arrangement of the instructions stored in the instruction memory is such that the reading of the first plurality of instructions and the reading of the second plurality of instructions do not match. apparatus. 2. An instruction memory for storing instructions and the instructions
A program counter that holds the address to memory,
Instructions read from the instruction memory and decoded
In a high-speed branch processing device equipped with an instruction register for storing
And a predetermined number of consecutive addresses from the instruction memory
Read control means for reading at a time, and read from the instruction memory by the read control means.
Two instruction buffers for temporarily storing a plurality of stored instructions.
And one of the two instruction buffers,
In addition, multiple instructions stored in the selected instruction buffer
Select any one of the orders, and
Instruction buffer selecting means for outputting to the instruction register, and the program counter causes the head of the plurality of instructions to be output.
When an address is specified, the first plurality of instructions
The read control means reads from the instruction memory,
The first plurality of instructions are stored in the two instruction buffers.
The instruction buffer is stored in the old one at the time of the last access.
Selecting means precedes the first plurality of instructions in the order of addresses.
If the decoded instruction is a conditional branch instruction, the condition is output to the instruction register.
Consecutive including the branch destination address before the branch judgment is completed
Read control of a second plurality of instructions at an address
Means reads from said instruction memory, said second plurality
Last instruction of the two instruction buffers
The oldest one is stored, and the instruction buffer selection means
The second plurality of instructions in the order of addresses
In addition to the above, the high-speed branch processing device further detects a conflict between the reading of the first plurality of instructions and the reading of the second plurality of instructions, and the conflict detecting means. If a read conflict is detected by, the read of the first plurality of instructions is suspended and the read of the second plurality of instructions is preferentially performed before the end of the conditional branch determination. As a result of the conditional branch determination, if the branch is not taken, the read second plurality of instructions are invalidated, and the suspended first instruction is read. And a high-speed branching processing device. 3. An instruction memory for storing instructions and the instructions
A program counter that holds the address to memory,
Instructions read from the instruction memory and decoded
In a high-speed branch processing device equipped with an instruction register for storing
And a predetermined number of consecutive addresses from the instruction memory
Read control means for reading at a time, and read from the instruction memory by the read control means.
Two instruction buffers for temporarily storing a plurality of stored instructions.
And one of the two instruction buffers,
In addition, multiple instructions stored in the selected instruction buffer
Select any one of the orders, and
Instruction buffer selecting means for outputting to the instruction register, and the program counter causes the head of the plurality of instructions to be output.
When an address is specified, the first plurality of instructions
The read control means reads from the instruction memory,
The first plurality of instructions are stored in the two instruction buffers.
The instruction buffer is stored in the old one at the time of the last access.
Selecting means precedes the first plurality of instructions in the order of addresses.
If the decoded instruction is a conditional branch instruction, the condition is output to the instruction register.
Consecutive including the branch destination address before the branch judgment is completed
Read control of a second plurality of instructions at an address
Means reads from said instruction memory, said second plurality
Last instruction of the two instruction buffers
The oldest one is stored, and the instruction buffer selection means
The second plurality of instructions in the order of addresses
In addition to the above, the high-speed branch processing device further detects a conflict between the reading of the first plurality of instructions and the reading of the second plurality of instructions, and the conflict detecting means. If a read conflict is detected by, the read of the second plurality of instructions is suspended and the read of the first plurality of instructions is preferentially performed before the end of the conditional branch determination. As a result of the conditional branch determination, if the branch is taken, the first plurality of instructions that have been read are invalidated, and the second plurality of instructions that have been suspended are read. And a high-speed branching processing device.