JP2508021B2 - Data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processor having an instruction pipeline processing function and a branch target instruction buffer.

[Conventional technology]

FIG. 3 is a block diagram of a conventional microprocessor equipped with an instruction pipeline processing function and a branch target instruction buffer. In the figure, (1) is an instruction prefetch queue, (2) is an instruction decoding section, and FIG. (3) is an instruction execution unit, (12) is a branch target instruction buffer B,
(5) is a comparator that compares the jump destination address stored in the branch target instruction buffer B (12) with the true jump destination address after the instruction execution, and (6) disables the instruction decoding currently being executed. This is the cancel signal. FIG. 4 shows the structure of the branch target instruction buffer B (12). In the figure, (13) is the address tag storing the address of the branch instruction, and (9) is the address of the address tag section (13). The jump address of the stored instruction, (10) is an N-byte instruction code starting from the jump address (9), and (11) is an invalid bit indicating that the entry is invalid when 1 '. .

Next, the operation of the microprocessor will be described. In the instruction pre-fetch queue (1), an instruction is fetched in advance by utilizing the time when the main memory is not accessed, and the next instruction to be executed is transferred from the instruction pre-fetch queue (1) to the instruction decoding section (2). This reduces the time required for instruction prefetching.
Further, while the instruction executing unit (3) is executing the instruction, the instruction decoding unit (2) decodes the next instruction, and when the instruction executing unit (3) finishes executing the instruction decoding (2)
The next instruction whose decoding has been completed is immediately executed. As described above, in the microprocessor, the pipeline processing is performed to increase the effective speed.

However, when an instruction such as a branch instruction that disturbs the flow of instructions, for example, a jump instruction, is executed, the decoding result in the instruction decoding unit (2) and the instruction data fetched by the instruction prefetch queue (1) are canceled. Then, the instruction pre-fetch queue (1) newly performs the queue from the jump destination address. That is, the instruction executed for the first time after the execution of the jump instruction must be fetched directly from the main memory, and the instruction execution unit (3) must interrupt the execution of the instruction during that time.

In the microprocessor, in order to improve this point, a branch target instruction buffer B (12) is provided to perform branch prediction. Describing the operation, when the instruction code is fetched from the instruction prefetch queue (1) to the instruction decoding section (2), the instruction decoding is started, and the branch target instruction buffer B (12) is started at the address value of the instruction. Search inside. In the branch target instruction buffer B (12), a branch instruction address such as a recently executed jump instruction is used as an address tag section (13), and an instruction jump destination address (at the address of the address tag section (13) ( 9) and an N-byte instruction code (10) starting from the address are stored. Further, each entry has an invalid bit (11) indicating whether the entry is valid or invalid. When the value is "1", the entry is invalid and does not hit.

When the instruction currently being decoded is not a branch instruction, or even if it is a branch instruction, it is executed for the first time, or another instruction is registered many times after it is executed, and the desired instruction is stored in the branch target instruction buffer B (12). When the value of the address of the instruction currently being decoded is not found in the branch target instruction buffer B (12), such as when there is no data, the instruction decoding unit (2) outputs from the instruction prefetch queue (1). Fetch the next instruction and continue processing. On the other hand, if the instruction currently being decoded is a recently executed branch instruction, the data is registered in the branch target instruction buffer B (12), so that when the search is performed, the entry there is hit. At this time, the instruction decoding unit (2) fetches the jump destination instruction data (9) stored in the branch target instruction buffer B (12). Also, the instruction prefetch queue (1) is reset, the transmission to the instruction decoding section (2) is stopped, and the instruction is executed from the N-bide destination address of the predicted jump destination address (9). When an instruction that disturbs the flow of the instruction enters the execution phase and the jump destination address is determined, the jump destination address and the branch target instruction buffer B (1
The comparator (5) compares the jump destination address (10) stored in 2). As a result of the comparison, if they match each other, the processing is continued as it is, and if they do not match, the current instruction decoding unit (2) is caused by the reset signal (6) output from the comparator (5).
The instruction being decoded is canceled, and the instruction prefetch queue (1) is reset, and the instruction execution unit (3)
It is necessary to wait until an instruction is fetched from the true jump destination address determined in. If the prediction is not correct and the instruction flow is not disturbed, it is highly possible that the instruction flow is not disturbed the next time this instruction is executed, and it is highly probable that the branch target instruction buffer B (12) has an invalid bit ( Set 11) to '1' to invalidate that entry. In addition, even if the address of the instruction currently being decoded or the branch target instruction buffer B (12) is not found, the branch target instruction buffer B (12) is detected when the branch is taken or when the branch is found.
If a branch is made to an address different from the contents of the above, the registration operation is performed to the branch target instruction buffer B (12). At this time, the address of the instruction that disturbed the flow is changed to the address tag (1
3), the jump destination address (9) and the N-byte instruction code (10) starting from that address are stored in the branch target instruction buffer B (12). The invalid bit (11) is set to '0'.

In this way, the branch target instruction buffer B
Even if the flow of instructions is disturbed by the addition of (12), the disturbance of pipeline processing is minimized and the effective processing speed of the microprocessor is increased.

[Problems to be solved by the invention]

When executing a branch instruction as described above, the conventional data processing device having a pipeline processing function for an instruction uses the address of the branch instruction as an address tag and the start address of the instruction sequence of the jump destination and N bytes starting from that address. By providing a branch target instruction buffer that stores the instruction code of, the disturbance of pipeline processing after execution of branch instructions such as jump instructions is suppressed. However, the address of the next instruction to be processed is obtained by determining the instruction length and adding the current program counter value to it,
Also, it takes time to search the branch target instruction buffer and prepare for fetching the instruction sequence of the jump destination into the instruction decode unit. There is a problem that it is difficult to take the instruction sequence into the instruction decoding unit.

The present invention has been made to solve the above problems, and an object of the present invention is to enable decoding of an instruction executed after a branch instruction to be started earlier.

[Means for solving problems]

A data processing apparatus according to the present invention uses a branch target instruction buffer in which an address of an instruction executed before a branch instruction is used as an address tag, and a start address of a branch destination and an N-byte instruction code starting from the address are stored. The old program counter storage unit holds the program counter value of the instruction executed before the instruction currently being executed by the execution unit.

[Action]

The data processor according to the present invention predicts the branch target address by searching the branch target instruction buffer with the address of the instruction executed before the branch instruction, and determines the instruction sequence starting from the branch target address as the branch instruction address. Immediately after that, it flows into the pipeline in a shorter time. If the branch prediction is incorrect, new branch information is registered in the branch target instruction buffer at the address of the old program counter storage unit.

〔Example〕

An embodiment of the present invention will be described below. FIG. 1 is a block diagram of a microprocessor according to an embodiment of the present invention. In the figure, (1) is an instruction prefetch queue, (2) is an instruction decode section, (3) is an instruction execution section,
(4) is a branch target instruction buffer A, (5) is a comparator for comparing the jump destination address (9) stored in the branch target instruction buffer A (4) with the true jump address after the instruction execution, (6) is a cancel signal for invalidating the instruction decoding currently being executed. (7) is an old program counter storage unit that holds a program counter of an instruction executed immediately before the instruction currently being executed by the instruction execution unit (3). FIG. 2 shows a branch target instruction buffer A (4). In the figure, (8) is an address tag storing the address of the instruction executed immediately before the branch instruction, and (9) is the jump of the branch instruction executed next to the address of the address tag section (8). The destination address, (10) is an N-byte instruction code starting from the jump destination address (9), and (11) is an invalid bit indicating that the entry is invalid when it is '1'.

Next, the operation of the above embodiment will be described. When the instruction code is fetched from the instruction prefetch queue (1) to the instruction decoding section (2), the instruction decoding is started and the branch target instruction buffer A (4) is searched by the address value of the instruction. In the branch target instruction buffer A (4), the address of the instruction executed immediately before the recently executed branch instruction is used as the address tag (8), and the flow executed next to the address of the address tag section (8) is set. The jump destination address (9) of the disturbed instruction and the N-byte instruction code (10) starting from the address are stored.
Each entry has an invalid bit (11) indicating whether the entry is valid or invalid. When the value is "1", the entry is invalid and does not hit. If the instruction next to the instruction currently being decoded is a branch instruction such as a jump instruction, or if the instruction is executed for the first time even if it is a branch instruction, other instructions are registered many times and branch Target command buffer A
When the value of the address of the instruction currently being decoded is not found in the branch target instruction buffer A (4), such as when there is no desired data in (4), the instruction decoding unit (2) The next instruction is fetched from the instruction prefetch (1) and the processing is continued. On the other hand, if the instruction currently being decoded is an instruction that disturbs the flow of the recently executed instruction, the data is registered in the branch target instruction buffer A (4), so that the entry is hit when the search is performed. At this time, since the search in the branch target instruction buffer A (4) is started with the address of the instruction executed immediately before the branch instruction, the search is started earlier than the search with the address of the branch instruction. It will be. Therefore, since the instruction code (10) of the hit entry can be prepared to be fetched into the instruction decode unit (2) accordingly, the instruction code (10) of the jump destination is immediately transferred to the instruction decode unit (10) immediately after the completion of the decoding of the branch instruction. 2) can be incorporated. Further, the instruction prefetch queue (1) is reset and at the same time the sending to the instruction decoding section (2) is stopped, and the predicted jump address (9) is N.
Queuing is performed from the byte address. When the branch instruction enters the execution phase and the jump destination address is determined, the jump destination address and the jump destination address (10) stored in the branch target instruction buffer A (4) are compared by the comparator (5). It As a result of the comparison, if they match, the process is continued, and if they do not match, the comparator (5)
The reset signal (6) issued from the instruction cancels the instruction decoding currently being performed, and the instruction prefetch (1) is also reset, and the instruction is executed from the true jump destination address determined by the instruction execution unit (3). Have to wait until If the prediction is incorrect and no branch occurs, it is highly possible that the next execution of this instruction will not cause a branch, and the instruction execution unit (3) sets the program counter of the instruction executed immediately before the instruction currently being executed. The invalid bit of the entry corresponding to the contents of the stored old program counter storage unit (7) is set to "1" to invalidate the entry. Further, when the address of the instruction currently being decoded is not found in the branch target instruction buffer (4) and the instruction is branched, or when the branch is found but the branch target instruction buffer A is found.
When branching to an address different from the content of (4), it is registered in the branch target instruction buffer A (4).
At this time, the address of the instruction immediately before the branch instruction held in the old program counter storage unit (7) is used as the address tag (8), and the jump address (9) and the N-byte instruction code (10) starting from that address ) Is stored in the branch target instruction buffer A (4). Invalid Bit (11)
Set to '0'.

As described above, by providing the branch target instruction buffer (4) having the address of the instruction executed immediately before the branch instruction as the address tag, the prediction of the jump destination can be started before being decoded from the branch instruction. As a result, the instruction code of the jump destination can be fetched into the instruction decoding unit (2) earlier than the completion of decoding the branch instruction.

In the above embodiment, when the result of the search in the branch target instruction buffer A (4) is bit, the instruction code stored in the branch target instruction buffer A (4) is directly input to the instruction decoding unit (2). However, when the data stored in the branch target instruction buffer A (4) is larger than the size of the input bus of the instruction decoding unit (2), a part of the instruction code is put into the instruction decoding unit (2) and the rest is left. The instruction code of 1 may be incorporated in the instruction prefetch queue (1).

In the above embodiment, if the result of searching in the branch target instruction buffer A (4) is a hit, the instruction prefetch (1) is reset and the jump destination address () in the branch target instruction buffer A (4) is Although it is possible to perform the query from N bytes of 9), the condition jump may have been jumped last time but not jumped this time. Therefore, the instruction decode uses the instruction data of the branch target instruction buffer A (4). However, the instruction prefetch is not reset and only the transmission of the data to the instruction decoding unit (2) is stopped, and the instruction prefetch (1 ) Is reset and queuing is newly performed from the jump destination address, and if the prediction is off and the flow of instructions is not disturbed, Decree pre Hue Tutsi cue placed in the instruction decoding unit to the instruction code that was incorporated into (1), it may be to continue Kiyuingu.

In the above embodiment, the branch prediction is performed at the address of the instruction executed immediately before the branch instruction, but the branch prediction is performed at the address of any instruction executed before the branch instruction even if not immediately before. May come.

〔The invention's effect〕

As described above, according to the present invention, by using the address tag of the branch target instruction buffer as the address of the instruction executed immediately before the branch instruction, the instruction executed next to the branch instruction after the decoding of the branch instruction is completed. The queue can be fetched to the instruction decoding unit in a shorter time than the conventional device even if there is no waiting time, even if there is a waiting time, so even when an instruction branches, the disturbance of pipeline processing is suppressed and the micr processor The effect is that the effective speed can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of a microprocessor according to an embodiment of the present invention, FIG. 2 is a configuration example of the branch target instruction buffer A of FIG. 1, and FIG. 3 is a block diagram of a conventional microprocessor. The figure shows the structure of the branch target instruction buffer B of FIG. In the figure, (1) is the instruction prefetch, (2)
Is an instruction decoding unit, (3) is an instruction execution unit, (4) is a branch target instruction buffer A, (5) is a jump destination address (8) stored in the branch target instruction buffer A, and a true address after the instruction execution. A comparator for comparing the jump destination address, (6) is a cancel signal for invalidating the instruction decoding currently being executed, and (7) is the instruction executed immediately before the instruction currently being executed by the instruction executing section (3). Old program counter storage unit that holds the program counter, (8) is an address tag that stores the address of the instruction executed immediately before the branch instruction, (9) is the jump destination address of the branch instruction, (10)
Is an N-byte instruction code starting from the jump address (9), (11) is an invalid bit indicating that the entry is invalid when it is "1", (12) is a branch target instruction buffer B, and (13) is An address tag that stores the address of a branch instruction. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A first storage device for storing a plurality of instructions in a plurality of regions ordered by region recognition symbols according to a certain rule, and a region distinguished by a first region recognition symbol of the first storage device. An instruction execution device for executing a first instruction sequence consisting of one or a plurality of instructions stored in, and the first instruction sequence while the first instruction sequence is being executed by the instruction execution device. Next, the second instruction sequence consisting of one or more instructions stored in the area distinguished by the second area recognition symbol of the first storage device to be executed by the instruction execution device is analyzed. While the instruction analysis device and the second instruction sequence are being analyzed by the instruction analysis device, the second instruction sequence is followed by the first storage device which is to be analyzed by the instruction analysis device. One or multiple stored in the area distinguished by the three area recognition symbols From a command prefetching device that fetches a third command sequence consisting of the command and one or a plurality of commands stored in a region distinguished by the fifth region recognition symbol of the first storage device in the command execution device. As a result of executing the fifth instruction sequence, the area is distinguished by the sixth area recognition symbol other than the area in the order following the area distinguished by the fifth area recognition symbol of the first storage device. The first memory executed before the fifth instruction sequence, when the sixth instruction sequence consisting of one or more stored instructions needs to be executed next by the instruction execution device. The area recognition symbol of the fourth command sequence consisting of one or more instructions distinguished by the fourth area recognition symbol of the device is used as an index, and the sixth area recognition symbol is stored in the first data storage unit. , Storing the sixth command sequence in the second data storage unit A comparison for comparing the area recognition symbol to be executed next by the second memory device and the instruction execution device with one of the area recognition symbols stored in the first data storage unit of the second memory device. Device,
A data processing device comprising: a third storage device for storing an area recognition symbol of an instruction sequence executed by the instruction execution device before the instruction sequence currently executed by the instruction execution device.