JPS63106046A - Data processor - Google Patents

Abstract

PURPOSE:To increase effective processing speed, by fetching an instruction data from a first memory device directly to an execution device through a bypassing circuit when an instruction prefetching device is vacant, and registering the instruction data passing through the bypassing circuit in a second memory device. CONSTITUTION:In a data processor provided with the prefetching function of data, an instruction queue 1 as the instruction prefetching device, an instruction decoding part 2, an instruction executing part 3 as the execution device, an instruction cache 4 as a second memory device, and the bypassing circuit 5 as the bypassing circuit, are provided. And when the instruction prefetching device 1 becomes vacant, the instruction data is fetched from a main memory directly to the instruction decoding part 2 through the bypassing circuit 5, and the instruction data passed through the bypassing circuit 5 is stored in the second memory device 4. In such way, it is possible to increase the effective processing speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device having an instruction brief fetch function.

[Conventional technology]

FIG. 3 is a block system diagram of a conventional microprocessor equipped with an instruction briefetch function.

In FIG. 3, ■ is an instruction queue, 2 is an instruction decode section, and 3 is an instruction execution section.

Next, the operation of the microprocessor shown in FIG. 3 will be explained. In a microprocessor, the time required to access main memory is much longer than the time required to access data inside the processor. Even if it operates at high speed, the effective speed does not increase.

To improve this point, the microprocessor shown in Figure 3 uses the time when the main memory is not being accessed to load instructions into instruction queue 1 in advance, and then decodes the next instruction to be executed from instruction queue 1. By fetching the data into part 2, the effective speed of the decoding processing device is increased. However, when the instruction decoder 2 issues an instruction fetch request to the instruction queue 1 after executing a certain instruction sequence,
If instruction queue 1 is empty, the next instruction to be executed must be fetched directly from main memory.

[Problem that the invention seeks to solve]

As described above, in a data processing device equipped with a conventional instruction briefetch function, if instruction queue 1 is empty, execution must be suspended until the next instruction to be executed is directly fetched from main memory. There was a problem in that the execution speed slowed down.

The present invention has been made in view of the above points, and an object thereof is to obtain a data processing device that reduces the possibility of accessing instruction data to main memory when an instruction queue becomes empty. There is a particular thing.

[Means for solving problems]

To achieve such an object, the present invention provides a first storage device that stores a plurality of instructions in a plurality of areas ordered by area recognition symbols according to a certain rule, and a first storage device of the first storage device. 1 stored in an area distinguished by an area recognition symbol
an execution device that executes a first instruction sequence consisting of one or more instructions; and an execution device that executes a first instruction sequence consisting of one or more instructions; 1 stored in the area distinguished by the second area recognition symbol
An instruction prefetching device that captures a second instruction sequence consisting of one or more instructions, and a third area recognition symbol of the first storage device when the instruction data captured in this instruction prefetching device runs out. A detour circuit for directly fetching a third instruction string consisting of one or more instructions stored in the area into the execution device without passing through the instruction prefetching device; In this embodiment, the data processing device is provided with a second storage device that stores the area recognition symbol No. 3 as an index.

[Effect]

In the present invention, when the instruction prefetch device becomes empty,
Instruction data is directly fetched from the main memory to the instruction decoding section through the detour circuit, and the instruction data that has passed through the detour circuit is stored in the second storage device.

〔Example〕

FIG. 1 is a block system diagram showing one embodiment of a microprocessor of a data processing device according to the present invention. 1st
In the figure, 1 is an instruction queue as an instruction prefetching device;
2 is an instruction decoding section, 3 is an instruction execution section as an execution device, 4 is an instruction cache as a second storage device, and 5 is a bypass circuit as a detour circuit.

FIG. 2 shows an example of the structure of the instruction cache 4 in the case of entry numbers Q - and -n. In the figure, 6 is an address tag as an area recognition symbol, and 7 is an address tag 6.
This is 4-byte instruction data starting from the address.

Next, the operation of the microprocessor shown in FIG. 1 will be explained. Normally, the instruction decoding unit 2 fetches and decodes 2-byte data from the instruction queue 1, and the instruction queue 1 stores multiple instructions in multiple areas ordered by area recognition symbols that follow certain rules. Queuing is performed from the main memory as the first storage device.

However, when the instruction queue 1 becomes empty while a certain instruction sequence is being executed, the instruction queue 1 refers to the instruction cache 4. In the instruction cache 4, the address of the next instruction to be fetched when the instruction queue 1 becomes empty during the execution of a recent instruction sequence is set as an address tag 6, and 4-byte instruction data 7 starting from that address is stored. has been done. A cache miss occurs when an instruction sequence is executed for the first time, or when other instructions are registered many times after execution and the desired data is not present in the instruction cache 4. In this case, the first two bytes of the four-byte instruction data fetched from the main memory are directly input to the instruction decoding section 2 through the bypass circuit 5. At the same time, the 4-byte instruction data that has passed through the bypass circuit 5 is registered in the instruction cache 4 along with its starting address. The last 2 bytes of the 4 bytes of instruction data currently registered in the instruction cache 4 are queued in the instruction queue 1.

On the other hand, if the executed instruction sequence was recently executed and instruction queue 1 was empty the last time it was executed, then
There is a high possibility that it will be a catschhit. In the case of a cache hint, the instruction queue 1 queues instruction data stored in the instruction cache 4. Therefore,
There is no need to wait for instructions to be fetched from main memory.

When executing a loop, if instruction queue 1 becomes empty when a certain instruction sequence is executed, the same situation will often occur when the same instruction sequence is executed again, increasing the cache hint rate. With the addition of the instruction cache 4, the possibility of accessing instruction data to the main memory is reduced.In addition, with the addition of the bypass circuit 5, even in the case of a cache miss, the instruction data from the main memory is directly accessed through the bypass circuit 5. It is efficient because it is taken into the decoding section 2.

As described above, the instruction cache 4 and the bypass circuit 5
By adding , the effective speed of the microprocessor can be increased.

Furthermore, since the instruction queue 1 is canceled after execution of a branch instruction, the queue becomes empty, instruction data of the branch destination is registered, and instruction fetch after execution of the recently executed branch instruction can be performed at high speed.

As another embodiment of the present invention, a bypass circuit for the instruction queue 1 may be provided for directly fetching the first two bytes of instruction data from the instruction cache 4 into the instruction decoding section 2 when the instruction cache 4 is referenced.

〔Effect of the invention〕

As explained above, the present invention allows instruction data to be directly fetched from a first storage device to an execution device through a detour circuit when the instruction prefetch device is empty, and to register instruction data that has passed through the detour circuit in a second storage device. By doing so, when the same instruction sequence is executed again, the instruction data can be fetched from the second storage device, so there is no need to wait for instructions to be fetched from the first storage device, and the data processing device This has the effect of increasing the effective processing speed.

[Brief explanation of the drawing]

FIG. 1 is a block system diagram showing an embodiment of a microprocessor in a data processing device according to the present invention, FIG. 2 is a block diagram showing an example of the structure of an instruction cache, and FIG. 3 is a block diagram showing an example of a microprocessor in a conventional data processing device. FIG. 1...Instruction queue, 2...Instruction decoding section, 3...
- Instruction execution unit, 4... instruction cache, 5... bypass circuit.

Claims (1)

[Claims] a first storage device that stores a plurality of instructions in a plurality of areas ordered by area recognition symbols according to a certain rule;
an execution device that executes a first instruction sequence consisting of one or more instructions stored in an area distinguished by a first area recognition symbol of a storage device; and an execution device that executes the first instruction sequence by the execution device. A second instruction sequence consisting of one or more instructions stored in an area distinguished by a second area recognition symbol in the order subsequent to the area distinguished by the first area recognition symbol while being It consists of an instruction prefetching device to be fetched, and one or more instructions stored in an area distinguished by a third area recognition symbol of the first storage device when the instruction data fetched by the instruction prefetching device runs out. a detour circuit for directly fetching a third instruction string into the execution device without passing through the instruction pre-fetching device; and a second circuit for storing the third instruction string that has passed through the detour circuit using a third area recognition symbol as an index. A data processing device comprising: a storage device.