JPS6051947A - Instruction prefetching system in virtual storage computer - Google Patents

Abstract

PURPOSE:To raise a throughput for processing the instruction of a virtual storage computer by executing an address conversion only at the time of a page transition. CONSTITUTION:When a page transition is detected by a location counter 64, an instruction processing part 63 address converts the virtual page address of a next page to store a new actual page address in the counter 64, and also an instruction buffer control part 66 stops the operation of an instruction prefetch mechanism. Thereafter, when the actual page address is stored in the counter 64, the operation stop of the instruction prefetch mechanism is releases. In this way, when the page transition is generated, the new actual page address is set automatically to the location counter 64, and it will do that the address conversion is executed by an address converting part 68 only when the page transition is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an instruction fetching method in computer instruction processing, and more particularly to an instruction prefetching method in a virtual memory computer.

[Technical background of the invention]

Generally, the processing of instructions in a computer is usually performed in the following steps. (1) instruction fetch (to retrieve an instruction), (2) decoding of the instruction, (3) calculation of an operand address, (4) operand fetch (to retrieve an operand), and (5) execution. Among these, in order to perform the instruction fetch (1) efficiently and at high speed, a method of pre-fetching instructions has been commonly used.

FIG. 1 shows a conceptual diagram of a conventional instruction prefetching method. As shown in the figure, the instructions read from the main storage device (including cache memory) 1 are not directly sent to the instruction processing section 3, but are once stored in the instruction buffer 2 and then sent to the instruction processing section 3. When an instruction is taken out from the instruction buffer 2 and the instruction buffer becomes empty, the instruction buffer 12 takes out an instruction next to the taken out instruction or several steps ahead from the main memory 1 and stores it therein. This is command preemption. By such an operation, reading of instructions from the main memory device 1 is performed in parallel with instruction processing in the instruction processing section 8, and the throughput of instruction processing is improved.

Funokoku shows an example of a virtual computer system to which the conventional instruction preemption method is applied. An I cage counter (hereinafter referred to as LOC) 4 stores the virtual page address of the next instruction to be prefetched, and an instruction buffer 12
After the instructions held in the LOC are sent to the instruction processing section 8, when a space becomes available in the instruction buffer 2, the virtual page address from the LOC 4 is converted into a real page address by the address conversion section 5 and transferred to the main memory 1. The command is prefetched. The instruction read from the real page address of the main memory 10 is stored in the instruction buffer 12, and when this storage is completed, LOC4 is counted up and the address (virtual) where the next instruction in the main memory 1 is stored is stored. address).

The instruction prefetch operation described above is performed on the premise that the storage address in the storage device 1 of the next instruction to be processed is the same as the storage address of the instruction currently being processed. , branch, interrupt, etc.), the storage address of the next instruction to be processed (branch destination, interrupt destination instruction) cannot be predicted from the storage address of the instruction currently being processed. It may be an address. In such a case, it is necessary to newly set (load) the address of the branch destination and interrupt destination in LOC4 and then restart instruction prefetching. , each time an instruction is fetched from the main storage device 1, the address translation unit 5 performs LOC
The virtual page address from No. 4 must be converted into a real page address, which has the drawback that the throughput F of instruction processing deteriorates by the time required for this address conversion.

FIG. 3 shows a 3-instruction preemption system proposed to eliminate the above drawbacks. The difference between the example in FIG. 3 and the example shown in FIG. 2 is that in FIG. This is where the address after address conversion by the address conversion unit 5, that is, the real page address is stored. As a result, when the address translation unit 5 has to perform address translation, it is limited to only when setting the initial value to LOC4, and the address translation is performed every time the main b11 storage device 1 is accessed, as in the example shown in FIG. This eliminates the need for pre-fetching instructions, making it possible to speed up instruction prefetching.

[Problems with back fist technique]

However, the proposed example shown in FIG. 3 has problems that do not exist in the conventional example shown in FIG. 2, and these will be described below. 4 and 5 show the concept of the virtual storage system. The virtual storage space 6 and the real storage space 7 are each divided into capacity units called pages, and the two are associated in page units. However, the consecutive units nSn+1 and n+2 in the virtual storage space 6 are not necessarily continuous in the real storage space 7. FIG. 5 is a diagram showing the relationship between virtual addresses and real addresses, where virtual address 8 has segment number 81, page number 82, and intra-page address 83.
This is converted into a real address 10 by the address translation mechanism 9.

That is, segment number 81 and page number 82 of virtual address 8 are converted to page address 10 by address translation mechanism 9.
1, real address 10 becomes page address 101
and an intra-page address 102.

By the way, since a program is written using a virtual address 8 as shown in Figure S, it occupies consecutive pages in the virtual memory space 6, but if consecutive pages are allocated in the memory space γ. is not limited. Therefore, a situation occurs in which two consecutive instructions in the virtual storage space 6 are placed in completely different pages with discontinuous addresses in the storage space 7. Alternatively, the first half and the second half of one instruction may be placed in different pages in the real storage space γ. In this way, the next instruction to be prefetched is placed on a different page from the immediately previous prefetched instruction, which is hereinafter referred to as page crossing.

In the proposed example shown in FIG. 3, since the address translation unit 5 converts the l, - real address and stores it, if a page transfer occurs at this real address,
There is a problem in that a page address that is -j different from the page address stored in OC4 must be reset to LOC4 to perform instruction prefetching, and resetting LOC4 takes time, making it difficult to efficiently perform instruction prefetching. The drawback was that it could not be done.

[Purpose of the invention]

SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks, an object of the present invention is to provide an instruction prefetching method in a virtual memory machine X that improves the throughput of instruction processing by quickly and efficiently removing instructions.

[Summary of the invention]

In the instruction prefetching method in the virtual memory meter A location that has a register and counter function to store the real page address.
A white counter, a means for detecting a page transfer based on the contents of this location white counter, a means for prohibiting prefetching of an instruction to an instruction buffer when a page transfer is detected, and a means for locating a new real page address when a page transfer is detected. - a means for setting on the chiron counter, and
When a page transfer is detected in the silon counter, the instruction prefetch operation is prohibited, and after storing a new real page address in the location silon counter, the instruction prefetch operation is restarted, and address conversion is performed only when a page transfer occurs. By adopting this method, the above objective is achieved.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an instruction prefetching method in a virtual memory computer according to the present invention will be described below with reference to the drawings. FIG. 6 is a block diagram showing an embodiment of a virtual computer system to which the instruction prefetching method in a virtual memory computer of the present invention is applied. The instructions read into the main memory 101 are held in an instruction buffer 62 and then transferred to an instruction processing section 63. The location counter 64, which functions as a register and a counter, has a page address section 641 and a page address section 642.
is provided and stores the real page address. When a space becomes available in the instruction buffer 62, a real page address is given to the main memory device 61 from the LOe 64 via line 1-02. The instruction corresponding to the above-mentioned real page address is transferred from the main memory device M61 to the instruction buffer 162, and the instruction is prefetched. When the instruction in the main memory 61 is held in the instruction buffer 62, the LOC 64 is counted up and points to the real page address where the next instruction is stored.

Now, when a carry-out signal is output from the in-page address 642 of the LOC 64 to the line 103, a page ripple is detected, and this carry-out signal is input to the set terminal S of the flip-flop 650. Set. When the flip-flop 65 of this 8- is set, the signal line 1
A page transfer signal is output to the instruction processing section 63 via the instruction processing section 04, and the instruction processing section 6
Let 3 know. At the same time, the page transfer signal is input to the instruction buffer 1 control unit 66 and the main memory access prohibition gate 67. For this reason, the signal line 10! from the instruction back 1 control unit 66 to the main memory 61! The access permission signal transferred via I is blocked by the gate 67, and the instruction buffer 1 control unit 66 outputs a signal that prohibits holding a new instruction in the instruction buffer 62, thereby preventing the operation of the instruction prefetch mechanism. to stop.

On the other hand, the instruction processing unit 6 has learned that a page transition has occurred.
3 sends the page number and segment number of the virtual address of the page next to the page in which the instruction currently being processed is stored to the address conversion unit 68, where the real page address is converted and the LOC is sent via line 10&. Transfer to counter 64. At the same time, the instruction processing unit 63
A new page address transfer signal is output, whereby the new real page address on line 105 is set in page address field 641 in LOC 64 . Note that the intra-page address of the virtual page address is directly sent from the instruction processing unit 63 via the line 107 to the intra-page address section 6 of the LOC 64.
42 and stored therein. Further, the new page address transfer signal outputted from the instruction processing unit @3 to the line 106 is inputted to the reset terminal H of the flip-flop 65, and this 7-lip-flop 6s is reset. Then, 7
The page transfer signal on the signal line 1040 of the lip-flop 65 becomes O-level, and the stoppage of the above-mentioned instruction prefetching mechanism is released.

According to this embodiment, when a page transition is detected in the LOC 64, the instruction processing unit 63 that knows this converts the virtual page address of the next page in the address conversion unit 68 and converts it into a new real page address. In addition to storing it in LOCa4, by detecting the page crossing, the instruction buffer 1
The control unit 66 stops the operation of the instruction prefetch mechanism constituted by the main storage device 61 and the instruction processing unit 63. after that,
When a real page address is stored in LOC@4, by canceling the stoppage of the instruction prefetch mechanism, a new real page address is automatically loaded into LO when a page transfer occurs.
C64, and the address translation unit 68 only needs to perform address translation when a page transfer occurs between pages. Therefore, the instruction prefetch operation can be performed quickly and efficiently, improving the throughput of instruction processing. be able to.

〔Effect of the invention〕

As described above, according to the instruction prefetching method in the virtual memory computer of the present invention, the instruction prefetching is performed quickly and efficiently, thereby improving the throughput of instruction processing.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the concept of a general instruction prefetching method, Fig. 2 is a block diagram showing an example of a system to which the conventional instruction prefetching method is applied, and Fig. 3 is a diagram showing a newly proposed instruction prefetching method. Figure 4 is a diagram showing the relationship between virtual storage space and real storage space, Figure 5 is a diagram showing an example of virtual addresses and real addresses, and Figure 6 is a diagram showing an example of the applied system. 1 is a block diagram showing an implementation of an instruction prefetching method in a virtual memory computer according to the present invention; FIG. 61...Main storage device, 62...-Instruction unit 71.63
...Instruction processing unit, 64...Location counter,
65-=7 lip flops, 66...Instruction buffer 1 control unit, 67...Main memory access prohibition gate agent Patent attorney Hon 1) Takashi 12-

Claims (1)

[Claims] In an instruction prefetching method in a virtual memory computer, an address conversion unit converts a virtual address transferred from an instruction processing unit into a real page address, and stores a real address in the main memory where an instruction to be prefetched is located. a location scene counter, a means for detecting a page transition based on the contents of the location scene counter, and when this page transition is detected, a new virtual page address from the instruction processing section is converted into a real page address by the address conversion section. means for setting the new real page address in the location scene counter, and an instruction prefetch comprising the main memory and the instruction buffer from when a page transition is detected until the new real page address is set in the location scene counter. 1. An instruction prefetching method in a virtual memory computer, characterized by comprising means for temporarily stopping the operation of the mechanism.