JPS63149733A - Instruction fetching system - Google Patents

Abstract

PURPOSE:To improve the processing speed of macro-instruction fetching by executing the fetch processing in accordance with the validity/invalidity of a flag indicating whether a macro-instruction effective for a buffer exists or not at the time of generating a microinstruction for fetching the macro- instruction. CONSTITUTION:The titled system is provided with a register 11 for counting up a macro-instruction address one by one to prepare the succeeding macro- instruction, a flag forming part for forming a flag 4 indicating whether the contents of an instruction buffer 7 is valid or invalid and an AND 13 finding up an AND condition between an invert signal of the flag 4 and an ON output of a register 6 in which a microinstruction is set up and sending a memory request signal 2. Thus, the processing speed of macro-instruction fetching can be improved by constituting the system so that the fetch processing of the macro-instruction correspond to the validity/invalidity of the flag 4 at the time of generating the microinstruction (RQF instruction) for fetching the macroinstruction.

Description

[Detailed Description of the Invention] [Summary] In order to improve the processing speed of macro instruction fetch based on internal firmware in an instruction fetch method in a microprogramming computer, an instruction buffer that supports word boundaries and its It has a flag indicating whether or not a valid macro instruction exists in the instruction buffer, and is configured to perform macro instruction fetch processing depending on whether the flag is disabled or enabled when a micro instruction for fetching a macro instruction is issued. As a result, the processing speed of macro instruction fetching can be improved, and processing can be performed in a simple manner without being aware of the flag in firmware.

[Industrial application field]

The present invention relates to an instruction fetch method in a microprogramming type computer.

In general, computers use macro instructions (one in a source language).
(one instruction) is placed on main memory and must be read from main memory to fetch one macro instruction. Note that the read data is stored in the instruction buffer.

The main memory that constitutes the main memory is generally a dynamic RAM (Random Access Memory).
y), etc., and the access time thereof is slower than the processing speed of the central processing unit (hereinafter referred to as CPU).

Therefore, the CPU is configured to take two to six cycles to access the macro instruction from the main memory.

Further, the data bus width between the main memory and the CPU is 4 bytes, so that a 4-byte wide instruction can be fetched into the instruction buffer with one main memory access.

However, since each macro instruction read by the firmware is one byte at a time, the firmware must be aware of which part of the instruction buffer has been used.Therefore, there is a need for a method to simplify this process.

[Conventional technology]

FIG. 4 shows a block diagram illustrating a conventional example.

FIG. 4 is composed of a CPt 11 having the arithmetic processing function of a microprogramming type computer, and a main memory device 2 constituting a main memory.

The CPU also has an arithmetic logic unit (hereinafter referred to as ALU) 3 that performs fixed-point arithmetic operations and logical operations, and an AL[J
an instruction fetch address register (hereinafter referred to as iA) 4 that holds an instruction fetch address sent from the main memory 3; an address register (hereinafter referred to as SAR) 5 that stores an address for accessing the main memory 2; a microinstruction register (hereinafter referred to as MiR) 6 that holds instructions for decoding the contents of the device 2; - an instruction buffer (hereinafter referred to as iB) 7 that holds instructions read from the main memory 2; Multiplexers (hereinafter referred to as MPX) 8a to 8d that select one from input signals and send it out, and MPX8
The register 9 stores the data selected in step d.

In order to operate the hardware shown in FIG. 4, processing is performed using predetermined firmware, and the operation based on this firmware will be described below.

First, when fetching macro instructions in firmware,
Whether the macro instruction exists in iB7 or in the main memory in the main memory device 2 depends on the value of iA4 at that time.

That is, iA4 indicates the macro instruction address to be fetched next, and if the lower two bits of that address are, for example, "11", the macro instruction to be fetched next is stored on the main memory in the main memory device 2. Yes, and if the value is other than °11, then the macro instruction to be fetched next exists in iB7.

Note that iB7 is a latch that sets an instruction at a word boundary (an address within a storage area specified by an integral multiple of the word length).

As mentioned above, to know the value of the lower 2 bits of iA4,
In addition, for iA4 count up and change, iA4
The output of is connected to one side of AlI3, for example, to the input side of liver χ8b.

Therefore, for example, the logical operation of AlI3 (00...011
The value of the lower two bits can be found by

In this way, as a result of judgment based on the value of the lower 2 bits of iA4, if an instruction exists in iB7, a microinstruction (hereinafter referred to as an RQF instruction) for fetching a macro instruction to fetch an instruction from iB7 is determined. If no instruction exists in the iB7, an RQF instruction is issued in order to fetch the instruction from the main memory in the main memory device 2.

In order to read an instruction from the main memory in the main memory device 2 described above, the output is turned on when the RQF instruction is set to a predetermined position in the MiR6, and the RQF instruction causes the Mi
The memory request signal (2) from R6 is turned on, and the main memory in the main memory device 2 is accessed by the address from 5AR5 (carried through the address bus (2)).

[Problem to be solved by the invention] In the case of the above-mentioned operation processing, since the firmware is aware of how far the data in the iBT is used, if the instruction fetch addresses are consecutive, the instruction fetch address When the lower two bits of ``11'' become ``oo'', the instruction at the address ``OO'' is iB7,
Therefore, it was necessary to issue a new microinstruction (ie, RQF instruction) for fetching the macroinstruction.

Therefore, it has not been possible to improve the processing speed of macro instruction fetch beyond a predetermined level.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the invention in detail.

The principle block diagram of the present invention shown in FIG. 1 includes the functional blocks 2, 3.5 to 7, and 8c explained in FIG. Flag creation means (flag creation unit) that counts up the instruction address by one and creates a flag (■) indicating whether the contents of the rows (iAAlI3, iB7 are valid or invalid)
12, the invert signal of the flag ■ generated by the flag creation unit (flag creation unit) 12, and the fact that the RQF command is set in the MiR6 and its output is turned on, and the memory request signal ■ is generated. ANO1 to send
3.

[Effect]

When operating instructions for firmware-based macro instruction fetch, iB7 that supports word boundaries
The iB7 has a flag ■ that indicates whether a valid macro instruction exists or not, and when a macro instruction fetch microinstruction (RQF instruction) is issued, the macro instruction fetch processing is disabled or enabled by the flag ■. By configuring to correspond, it is possible to improve the processing speed of macro instruction fetch, and furthermore, it is possible to process data in a simple manner without being aware of the flag (2) in firmware.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a block diagram explaining the present invention in detail, and FIG. 3 is a diagram explaining the processing situation in an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

iAAlI3 of this embodiment, i^4 and i explained in FIG.
It consists of a plus 1 circuit 11a that sequentially counts up the value of A4 by plus 1.

In addition, the flag creation unit 12 generates the NAN of the lower 2 bits in the iAd.
NAN port circuit 12a and NAND circuit 12a that take D condition
F, F circuit 12b and F, F circuit 12 that latch the output of
It consists of an inverter 12c that inverts the output of b.

Note that the output of the F and F circuits 12b becomes a flag ■ indicating whether or not a valid macro instruction exists in iB7, and is hereinafter referred to as iBV.
Display with ■. Further, CLK input to this CK terminal indicates a system clock generated by a circuit not shown.

In this embodiment, for example, when the value of the lower two bits in iAd becomes "11", F, F12 in the flag creation section 12
iBV■ which is the output of b is turned off, and if the value of the lower two bits in iAd is other than '11°, iBV■ is turned on.

This iBV■ signal is passed through the inverter 12c to 8N0
A signal that is turned on when an RQF command is sent to the MiR6 is input to one input terminal of the AND 13, and a signal that is turned on when an RQF command is sent to the MiR 6 is input to the other input terminal, and the output of the AND 13 is sent out as a memory request signal (2).

Note that RQF commands are continuously issued to MiR6 as shown in FIG. Further, only the value of the lower two bits of iA4 is shown in FIG.

According to the tie chart in FIG. 3, when the RQF instruction (1) is executed, the value of iA4 is 2 (i^4=2), and (
When executing the RQF instruction 2), 1A4=3. or,(
When executing the RQF instruction in 3), 1A4=o, RQ in (4)
When the F instruction is executed, it is 1A4-1.

Here, since i^4=3 when the RQF instruction (2) is executed, iBV■ is turned off when the RQF instruction (3) indicating the execution of the next RQF instruction is executed. That is, RQ of (3)
This indicates that the macro instruction fetched by the F instruction does not exist in iB7.

Therefore, the RQF command in (3) is the main memory tα in the main memory 2.
In order to read the desired macro instruction from the memory, the memory request signal (2) is turned on.

Furthermore, the RQF command drives MPX8c so that the value of iA4 is automatically set to 5AR5.

In this way, the firmware in this embodiment is
Regardless of whether or not there is valid data in 7, it is sufficient to issue the RQF command, so efficient firmware can be realized.

Furthermore, since no extra microsteps are required, processing speed can be improved.

〔Effect of the invention〕

According to the present invention as described above, the processing speed of macro instruction fetching can be improved and the macro instruction fetching process can be executed using a simple method.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining the processing situation in an embodiment of the present invention, and FIG. 4 is a conventional block diagram. In the block diagram explaining an example, 1 and 10 are CPUs, 2 is a main storage device, and 3
8 LU, 4
is i8, 5 is SAR, and 6 is MiR. 7 is 1ilts 8a-8d is M
PX. 9 is a register, 11 is an iA section, 11a is a plus 1 circuit, 12 is a flag creation section, 12a is a NAND
, 12b is F, 12c is an inverter, 13 is AND. are shown respectively. 7vt bundle Ida'J ELtIT T37"U rough g-chofu 4rin

Claims (1)

[Claims] A computer having a main memory (2) and accessing the main memory (2) using a microprogram, comprising: an instruction buffer (7) corresponding to a word boundary; Address storage means (5) for storing an address for accessing the storage memory (2), instruction fetch address holding means (11) for fetching macro instructions, and determining whether the contents of the instruction buffer (7) are valid or invalid. The flag ([4]) indicating whether
11), and further defines a microinstruction for fetching a macroinstruction, and when the flag ([4]) is invalid, the main memory (
Read the word boundary data including the desired instruction from 2) and set it in the instruction buffer (7), and when the flag ([4]) is valid, read the word boundary data containing the desired instruction.
Selecting a desired instruction from 7), counting up the instruction fetch address holding means (11) to prepare for the micro instruction for fetching the next macro instruction; An instruction fetch method characterized by determining whether an instruction valid for a microinstruction exists in the instruction buffer (7) and updating the flag ([4]) for the next microinstruction.