JPH0464094B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In order to improve the processing speed of macro instruction fetches based on internal firmware in an instruction fetch method in a microprogramming computer, an instruction buffer corresponding to word boundaries is provided. It has a flag indicating whether or not a valid macro instruction exists in the instruction buffer, and is configured to perform macro instruction fetch processing depending on whether the flag is disabled or enabled when a micro instruction for macro instruction fetch is issued. By doing so, the processing speed of macro instruction fetching can be improved and processing can be performed in a simple manner without being aware of the flags in the firmware.

[Industrial application field]

The present invention relates to an instruction fetch method in a microprogramming type computer.

Generally, in a computer, a macro instruction (one instruction in a source language) is placed in main memory,
To fetch one macroinstruction, it must be read from main memory. Note that the read data is stored in the command buffer.

The main memory that constitutes the main memory is generally dynamic RAM (Random Access Memory).
etc. are used, and their access time is slower than the processing speed of the central processing unit (hereinafter referred to as CPU).

Therefore, the CPU is configured to take two to six cycles to access macro instructions from main memory.

Furthermore, the data bus width between the main memory and the CPU is 4 bytes, so that a 4-byte wide instruction can be fetched into the instruction buffer with one main memory access.

However, since the macro instructions read by the firmware are one byte at a time, the firmware must be aware of which part of the instruction buffer has been used, so a method to simplify this process is desired.

[Conventional technology]

FIG. 4 shows a block diagram illustrating a conventional example.
The computer shown in FIG. 4 is composed of a CPU 1 having an arithmetic processing function of a microprogramming type computer, and a main memory device 2 constituting a main memory.

In addition, CPU1 is an arithmetic logic unit (hereinafter referred to as ALU) that performs fixed-point arithmetic operations and logical operations.
3 and the instruction fetch address register (hereinafter referred to as
iA) 4, and an address register (hereinafter referred to as SAR) that stores the address for accessing the main memory 2.
5, a microinstruction register (hereinafter referred to as MiR) 6 that holds instructions for decoding the contents of the main memory 2, and an instruction buffer (hereinafter referred to as iB) that holds instructions read from the main memory 2. ) 7, and multiplexers (hereinafter referred to as MPX) 8a to 8d that select one from multiple input signals and send it out.
and a register 9 for storing data selected by MAX8d.

In order to operate the hardware shown in FIG. 4, processing is performed using predetermined firmware, and the operation based on this firmware will be described below.

First, when fetching a macro instruction using the firmware, it is important to know whether the macro instruction exists in the iB7 or in the main memory in the main storage device 2.
Depends on the iA4 value at that time.

That is, iA4 indicates the address of the macro instruction to be fetched next, and if the lower two bits of that address are, for example, "11", the macro instruction to be fetched next is stored on the main memory in the main memory device 2. Yes, and if it is other than "11", the macro instruction to be fetched next exists in iB7.

Note that iB7 is a latch that sets an instruction at a word boundary (an address within a storage area specified by an integral multiple of the word length).

As mentioned above, in order to know the value of the lower 2 bits of iA4, and also to count up and change iA4, the output of iA4 is output from one side of ALU3, for example.
Connected to the input side of MAX8b.

Therefore, for example, the logical operation of ALU3 (“00...
011”) to find the value of the lower two bits.

In this way, as a result of judgment based on the value of the lower two bits of iA4, if an instruction exists in iB7, a microinstruction (hereinafter referred to as this) for fetching a macro instruction to fetch an instruction from iB7 is determined.
If no instruction exists in the iB7, an RQF instruction is issued in order to fetch the instruction from the main memory in the main memory device 2.

Note that when reading an instruction from the main memory in the main memory device 2 described above, the output is turned on when the RQF instruction is set at a predetermined position in the MiR6.
The RQF command turns on the memory request signal from MiR6, and the main memory in the main memory device 2 is accessed using the address from the SAR5 (carried through the address bus).

[Problem that the invention seeks to solve]

In the case of the above operation processing, the firmware is aware of how far the data in the iB7 is used, so if the instruction fetch addresses are consecutive, the lower two bits of the instruction fetch address will be "11". ” to “00”, it is determined that the instruction at the address “00” is not in the iB7, and the microinstruction for fetching the macroinstruction (i.e.,
A new RQF Order) had to be issued.

Therefore, the processing speed of macro instruction fetching could not be improved beyond a predetermined level.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the principle of the invention.

As shown in FIG.
A computer that accesses the main memory 2 using a microprogram, comprising: an instruction buffer 7 that stores instructions consisting of a predetermined number of bytes defined by a word boundary; an instruction fetch address holding means 11 having an address count-up means and sending an access address to the address storage means 5 for the next macro instruction fetch; A flag creating means 12 creates a flag indicating whether the contents of the instruction buffer 7 are valid or invalid from the contents of the instruction fetch address holding means 11, and when the flag is invalid, the main memory is written by a microinstruction. A predetermined number of bytes of instructions defined by the word boundary are read from the memory 2 and set in the instruction buffer 7, and when the flag is valid, the predetermined number of bytes stored in the instruction buffer 7 is read. This is achieved by an instruction fetch control device characterized in that a desired instruction specified by the instruction fetch address holding means 11 is selected from among the instructions.

[Effect]

When operating an instruction for fetching a macro instruction based on firmware, it has an iB7 corresponding to the word boundary and a flag indicating whether or not a valid macro instruction exists in that iB7. By configuring the macro instruction fetch processing to correspond to the invalidation/enablement of the flag when a command (instruction) is issued, it is possible to improve the processing speed of the macro instruction fetch, and furthermore, the firmware can be made aware of the flag. This makes it possible to process data in a simple way without any hassle.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a block diagram illustrating an embodiment of the present invention, and FIG. 3 is a diagram illustrating a processing situation in the embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

The iA section 11 of this embodiment is the iA unit 11 explained in FIG.
4 and a plus 1 circuit 11a that sequentially counts up the value of iA4 by plus 1.

The flag creation unit 12 also has a NAND circuit 12a that takes the NAND condition for the lower two bits in iA4.
FF circuit 1 that latches the output of NAND circuit 12a
2b and an inverter 12c that inverts the output of the FF circuit 12b.

Note that the output of the FF circuit 12b serves as a flag indicating whether or not a valid macro instruction exists in iB7.
Displayed below in iBV. Furthermore, CLK input to this CK terminal indicates a system clock generated by a circuit not shown.

In this embodiment, for example, when the value of the lower two bits in iA4 becomes "11",
Turn off iBV, which is the output of F.F12b, and
If the value of the lower two bits is other than “11”, iBV
Turn on.

This iBV signal is passed through the inverter 12c.
A signal is input to one input terminal of AND13, and a signal that turns on when the RQF command is set to MiR6 is input to the other input terminal.
The output of is sent as a memory request signal.

Note that RQF commands are continuously issued to MiR6 as shown in FIG. Also, iA4 is in the bottom 2
Only the bit values are shown in FIG.

According to the time chart in Figure 3, (1)
When the RQF instruction is executed, the value of iA4 is 2 (iA4=2), and when the RQF instruction (2) is executed, the value of iA4 is 3.
Also, when executing the RQF instruction in (3), iA4 = 0, and (4)
When the RQF instruction is executed, iA4=1.

Here, since iA4=3 when the RQF instruction (2) is executed, iBV is turned off when the RQF instruction (3) indicating the execution of the next RQF instruction is executed. That is, (3)
The macro instruction fetched by the RQF instruction is iB7
indicates that it does not exist.

Therefore, since the RQF instruction (3) goes to the main memory in the main memory device 2 to read the desired macro instruction, the memory request signal is turned on.

Also, the value of iA4 is automatically converted to SAR by the RQF command.
MPX8c is driven so that it is set to 5.

In this way, the firmware in this embodiment can be used regardless of whether or not there is valid data on the iB7.
Since it is only necessary to issue the RQF command, efficient firmware can be realized.

Furthermore, since no extra microsteps are required, processing speed can be improved.

〔Effect of the invention〕

According to the present invention as described above, the processing speed of macro instruction fetching can be improved and the macro instruction fetching process can be executed using a simple method.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the principle of the present invention.
FIG. 2 is a block diagram explaining an embodiment of the present invention;
Fig. 3 is a diagram explaining the processing situation in the embodiment of the present invention, and Fig. 4 is a block diagram explaining the conventional example. iA, 5 is SAR, 6 is MiR,
7 is iB, 8a to 8d are MPX, 9 is register, 1
1 is the iA section, 11a is the plus 1 circuit, 12 is the flag creation section, 12a is NAND, 12b is FF, 12
c represents an inverter, and 13 represents an AND.

Claims (1)

[Claims] 1. In a computer having a main memory 2 and accessing the main memory 2 using a microprogram, an instruction for storing an instruction consisting of a predetermined number of bytes defined by a word boundary. It has a buffer 7, an address storage means 5 for storing an address for accessing the main memory 2, and an address count-up means, and stores the access address in the address storage means 5 for the next macro instruction fetch. It comprises an instruction fetch address holding means 11 for sending out, and a flag creation means 12 for creating a flag indicating whether the contents of the instruction buffer 7 are valid or invalid from the contents of the instruction fetch address holding means 11, When the flag is invalid, a predetermined number of bytes of instructions defined by the word boundary are read from the main memory 2 by a microinstruction and set in the instruction buffer 7, and when the flag is valid, the instructions are read from the main memory 2 and set in the instruction buffer 7. An instruction fetch control device characterized in that a desired instruction specified by the instruction fetch address holding means 11 is selected from among the instructions of the predetermined number of bytes stored in the buffer 7.