JPH0528409B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In order to improve the processing speed of macro instruction fetching based on firmware in an instruction fetching method in a microprogramming type computer, an instruction buffer corresponding to word boundaries and its instructions are provided. It has a flag that indicates whether or not a valid macro instruction exists in the buffer, and is configured to match macro instruction fetch processing depending on whether the flag is disabled or enabled when a micro instruction for macro instruction fetch is issued. By doing so, it is possible to improve the processing speed of macro instruction fetch and reduce the load on the firmware.

[Industrial application field]

The present invention relates to an instruction fetch method in a microprogramming type computer.

Generally, in a computer, a macro instruction (one instruction in a source language) is placed in main memory,
To fetch one macroinstruction, it must be read from main memory.

The main memory that constitutes the main memory is generally dynamic RAM (Random Access RAM).
The access time is slower than the processing speed of the central processing unit (hereinafter referred to as CPU). Therefore, the CPU is configured to take two to six cycles to access macro instructions from main memory.

Furthermore, the data bus width between the main memory and the CPU is 4 bytes, so that a 4-byte wide instruction can be fetched into the instruction buffer with one main memory access.

However, since each macro instruction read by the firmware is one byte at a time, the firmware must be aware of which part of the instruction buffer has been used.

Furthermore, in a computer using a virtual memory system, a main memory address (physical address) is obtained by converting a logical address that can be recognized by a program.

Address translation operations are typically performed using TLB
This is done by referring to a translation table called (Translation Lookaside Buffer). When this address conversion is performed, the physical address may change significantly.

Since the instruction buffer contains macro instructions with consecutive addresses, when the physical addresses change discontinuously due to address translation, the macro instructions in the instruction buffer must be invalidated.

Therefore, the flag must be turned off by firmware after address conversion. These firmware operations increase the number of program steps and slow down processing.

Therefore, there is a need for an instruction fetching method that reduces the load on firmware and increases processing speed.

[Conventional technology]

FIG. 4 shows a block diagram illustrating a conventional example.
Figure 4 shows a CPU 1 that has the arithmetic processing function of a microprogramming computer, a main storage device 2 that constitutes the main memory, and a conversion table (hereinafter referred to as TLB) that is referenced during address conversion operations.
It consists of 10.

In addition, CPU1 is an arithmetic logic unit (hereinafter referred to as ALU) that performs fixed-point arithmetic operations and logical operations.
3, an instruction fetch address register (hereinafter referred to as iA) 4 that holds the instruction fetch address sent from the ALU 3, and an address register (hereinafter referred to as SAR) that stores the address for accessing the main memory 2.
5, and to obtain the physical address of main storage device 2,
Instruction to refer to TLB10 (hereinafter this will be referred to as
microinstruction register (hereinafter referred to as MiR) that sets the TQF instruction)
6, an instruction buffer (hereinafter referred to as iB) 7 that holds the instructions read out from the main memory 2, and multiplexers (hereinafter referred to as MPX) 8a to 8d that select one from a plurality of input signals and send it out.
and a register 9 for storing data selected by the MPX8d.

In order to operate the hardware shown in FIG. 4, processing is performed using predetermined firmware, and the operation of the conventional example based on this firmware will be described below.

First, when fetching a macro instruction based on the firmware, whether the macro instruction exists in iB7 or in the main memory in the main storage device 2 depends on the value of iA4 at that time.

That is, iA4 indicates the address of the macro instruction to be fetched next, and if the lower two bits of that address are, for example, '11', the macro instruction to be fetched next is stored on the main memory in the main memory 2. Yes, and if it is other than '11', the macro instruction to be fetched next exists in iB7.

Note that iB7 is a latch that sets an instruction at a word boundary (an address within a storage area specified by an integral multiple of the word length).

As mentioned above, in order to know the value of the lower 2 bits of iA4, and also to count up and change iA4, the output of iA4 is output from one side of ALU3, for example.
Connected to the input side of MPX8b.

Therefore, for example, the logical operation of ALU3 ('00...
011') to find the value of the lower two bits.

In this way, as a result of judgment based on the value of the lower 2 bits of iA4, if an instruction exists in iB7, a microinstruction (hereinafter referred to as this) for fetching a macro instruction to fetch an instruction from iB7 is determined.
If no instruction exists in the iB7, an RQF instruction is issued in order to fetch the instruction from the main memory in the main memory device 2.

Note that when reading an instruction from the main memory in the main memory device 2 described above, the output is turned on when the RQF instruction is set at a predetermined position in the MiR6.
The RQF command turns on the memory request signal from MiR6, and the main memory in the main memory device 2 is accessed using the address from the SAR5 (carried through the address bus).

Similarly, when an instruction jumps, starts an instruction, or crosses a page, the TQF instruction also
is set at a predetermined position within the
The TLB reference signal turns on, and a request for address translation is made to the TLB 10 after setting the logical address in the SAR 5.

The resulting physical address is set to SAR5 via MPX8c. The subsequent macro instruction fetch operation using the physical address is as described above.

[Problem that the invention seeks to solve]

In the case of the above operation processing, the firmware is aware of how far the data in iB7 is used, so if the instruction fetch addresses are consecutive, the lower two bits of the instruction fetch address are '11'. ' to '00', it is determined that the instruction at the address '00' is not in the iB7, and the microinstruction for fetching the macroinstruction (i.e.,
A new RQF Order) had to be issued.

Furthermore, after issuing a TQF instruction that performs address translation at the time of an instruction jump or the start of an instruction, even if an instruction exists in the iB7, it must be determined that there is no instruction. Therefore, the operations of these firmwares have been a factor in increasing the number of program steps and slowing down the processing speed.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the principle of the invention.

As shown in FIG.
and a central processing unit 50 that accesses the main memory 2 using a microprogram, a first microinstruction for fetching a macroinstruction and an address of an instruction fetch address. a second microinstruction that refers to the conversion table 10 that performs conversion; an instruction buffer 7 that stores an instruction consisting of a predetermined number of bytes defined by a word boundary; an address storage means 5 for storing an address; an instruction fetch address holding means 11 having an address count-up means and for sending an access address to the address storage means 5 for the next macro instruction fetch; flag creation means 12 for creating a flag indicating whether the contents of 7 are valid or invalid from the contents of the instruction fetch address holding means 11 and also from the sending of the second microinstruction;
and when the content of the instruction fetch address holding means 11 indicates a predetermined value and the flag indicates invalidity, the first microinstructions continuously sent out cause the main memory to be read. A predetermined number of bytes defined by the word boundary are read from the instruction buffer 7.
When the content of the instruction fetch address holding means 11 indicates a value other than the predetermined value and the flag indicates that the flag is valid, the instructions of the predetermined number of bytes stored in the instruction buffer 7 are Select the desired instruction specified by the instruction fetch address holding means 11 from the address storage means 5, and when the second microinstruction is sent, refer to the conversion table 10 and select the address stored in the address storage means 5. and converting the flag output from the flag creation means 12 upon sending of the second microinstruction to a flag indicating invalidity, and outputting it from the flag creation means 12 when the second microinstruction is stopped. This is achieved by an instruction fetch control method characterized in that the flag is returned to a flag indicating valid.

[Effect]

Because the firmware fetches macro instructions,
When the RQF instruction for instruction fetch is issued, if the flag generated by the flag generation unit (flag generation unit) 12 is invalid, the word boundary data containing the desired instruction is read up to the main memory 2, and the iB
7, and if the flag is valid, select the desired instruction from iB7.

Next, the contents of iA4 are counted up by the plus 1 circuit 11a in preparation for the next RQF command, and then
It is determined whether there is an instruction valid for the RQF instruction in iB7, and the flag is updated for the next RQF instruction.

Furthermore, by configuring the system to turn off a flag when a TQF instruction is issued to convert the logical address of an instruction for a macro instruction fetch, the load on the firmware can be reduced with a simple hardware configuration. , and the processing speed can be increased.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a block diagram illustrating an embodiment of the present invention, and FIG. 3 is a diagram illustrating a processing situation in the embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

The iA section 11 of this embodiment is the iA unit 11 explained in FIG.
Plus 1 circuit 11 that adds 1 to the value of 4 and iA4
It consists of a.

Further, the flag creation unit 12 includes a NAND circuit 12a that takes the NAND condition of the lower two bits in the iA4,
FF circuit 1 that latches the output of NAND circuit 12a
2b, an inverter 12c that inverts the output of the FF circuit 12b, and an OR 12d that performs an OR operation on the conditions of the TQF reference signal.

It should be noted that the output of the FF circuit 12b is a flag indicating whether or not a valid macro instruction exists in iB7, and is hereinafter indicated by iBV. Furthermore, CLK input to this CK terminal indicates a system clock generated by a circuit not shown.

In this embodiment, for example, when the value of the lower two bits in iA4 becomes '11', the value in the flag creation unit 12 is
Turn off iBV, which is the output of the FF circuit 12b,
If the value of the lower 2 bits in iA4 is other than '11',
Turn on iBV.

Furthermore, when the TQF command is set in MiR6,
IBV will be turned off unconditionally.

This iBV signal is passed through the inverter 12c.
A signal is input to one input terminal of AND13, and a signal that turns on when the RQF command is set to MiR6 is input to the other input terminal.
The output of is sent as a memory request signal.

Note that RQF commands are continuously issued to MiR6 as shown in FIG. Also, in Figure 3, iA
Only the value of the lower two bits of 4 is shown.

According to the time chart in Figure 3A, (1)
If the value of iA4 is 2 (iA4=2) when the RQF instruction is executed, then iA4=3 when the RQF instruction (2) is executed.
Also, when executing the RQF instruction in (3), iA4 = 0, and (4)
iA4 becomes 1 when the RQF instruction is executed.

Here, since iA4=3 when the RQF instruction (2) is executed, iBA is turned off when the next RQF instruction (3) is executed. That is, (3)
This indicates that the macro instruction for the RQF instruction does not exist in iB7.

Therefore, since the RQF instruction (3) goes to the main memory in the main memory device 2 to read the desired macro instruction, the memory request signal is turned on. or,
The RQF instruction drives MPX8c so that the value of iA4 is automatically set to SAR5.

Next, the process when issuing a TQF command will be explained based on FIG. 3B.

When the TQF instruction is set at a predetermined location in MiR6, the iBV is turned off, and the RQF instruction (1) turns on the memory request signal regardless of the value of iB7.

The main memory address in the main memory device 2 of the RQF instruction in (1) is the physical address converted by the TLB 10. However, the logical in-page address is set in the lower bit of iA4, and the in-page address of iA4 indicates the correct memory address.

Therefore, MPX indicated by the lower two bits of iA4
Selecting 8d will select the correct macroinstruction. For example, as shown in Figure 3B, since iA4 = 2 when issuing the RQF command in (1), iBV is off for only one cycle, but if iA4 = 3 when issuing the RQF command in (1), For example, the iBV is turned off for two consecutive cycles.

In this way, the Uharuware in this embodiment can be used regardless of whether or not there is valid data on the iB7.
Since it is only necessary to issue the RQF command, efficient firmware can be realized.

Furthermore, since no extra microsteps are required, processing speed can be improved.

〔Effect of the invention〕

According to the present invention as described above, the load on firmware can be reduced with a simple hardware configuration, and the processing speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the principle of the present invention.
FIG. 2 is a block diagram explaining an embodiment of the present invention;
Fig. 3 is a diagram explaining the processing situation in the embodiment of the present invention, and Fig. 4 is a block diagram explaining the conventional example. iA, 5 is SAR, 6 is MiR,
7 is iB, 8a to 8d are MPX, 9 is register, 1
1 is the iA section, 11a is the plus 1 circuit, 12 is the flag creation section, 12a is the NAND, 12b is the FF circuit,
12c is an inverter, 12d is an OR, 13 is an
AND, respectively.

Claims (1)

[Scope of Claims] 1. In a computer comprising a main memory 2 and a central processing unit 50 that accesses the main memory 2 using a microprogram, a first processor for fetching a macro instruction is provided. and a second microinstruction that refers to a conversion table 10 that performs address conversion of an instruction fetch address, and an instruction buffer 7 that stores an instruction consisting of a predetermined number of bytes defined by a word boundary. , an address storage means 5 for storing an address for accessing the main memory 2, and an address count-up means, and an instruction for sending an access address to the address storage means 5 for the next macro instruction fetch. fetch address holding means 11; and a flag that creates a flag indicating whether the contents of the instruction buffer 7 are valid or invalid from the contents of the instruction fetch address holding means 11 and also from sending out the second microinstruction. Creation means 12
and when the content of the instruction fetch address holding means 11 indicates a predetermined value and the flag indicates invalidity, the first microinstructions continuously sent out cause the main memory to be read. A predetermined number of bytes defined by the word boundary are read from the instruction buffer 7.
When the content of the instruction fetch address holding means 11 indicates a value other than the predetermined value and the flag indicates that the flag is valid, the instructions of the predetermined number of bytes stored in the instruction buffer 7 are Select the desired instruction specified by the instruction fetch address holding means 11 from the address storage means 5, and when the second microinstruction is sent, refer to the conversion table 10 and select the address stored in the address storage means 5. and converting the flag output from the flag creation means 12 upon sending of the second microinstruction to a flag indicating invalidity, and outputting it from the flag creation means 12 when the second microinstruction is stopped. An instruction fetch control method characterized in that the flag is returned to a flag indicating validity.