JPS6235694B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention has one or more instruction buffer registers, and stores instructions following the currently executed instruction in the instruction buffer register in advance. Prohibition of instruction retrieval in an information processing apparatus in which instruction retrieval access is prohibited and the prohibition is canceled during execution of any instruction or in any instruction based on data read from control memory. and the method for revoking the prohibition.

[Prior art and problems]

FIG. 1 is a diagram showing the instruction execution process of a pipeline computer that uses the advance control method. In Figure 1a, each section of instructions 1 to 3 is 1 CPU
Represents a cycle. The individual instruction execution process is the first
As shown in FIG. b, the signal is divided into seven phases, which are six phases consisting of phases A to F, plus an instruction fetch phase. A pipeline computer that uses a proactive control system has one or more instruction buffer registers, performs a series of ordered operations as described above, and does not finish storing the result of instruction 1 that was started earlier. At home,
When the next instructions 2 and 3 are fetched and decoded, and the operands and registers used are different, the steps that are different from the previous instruction 1, such as fetching the operands, executing, checking, and storing the results, are performed in parallel. It will be done. In this way, each phase is 1 or
It can accept new input every 2 CPU cycles. However, if an instruction that rewrites the PSW (Program Status Word) comes during the execution of a certain instruction, the PSW (Program Status Word) will be rewritten from then on.
Must be performed by PSW. Therefore, the previously fetched instruction must be canceled and the instruction must be fetched again according to the new PSW. In this way, depending on the type of command,
There are instructions that require re-fetching, such as instructions that change the contents of system control masks and control registers, and instructions that jump to other areas, such as LOAD PSW. When these instructions are executed, it becomes unnecessary to prefetch the instruction connected to the instruction into the instruction buffer register. For example, if the LOAD PSW is at address 100, it is unnecessary to prefetch the instruction at address 101 into the instruction buffer register. An instruction fetch access results in a conflict between the instruction fetch and the operand access of the instruction currently in progress. If an operand access currently in progress is delayed due to an unnecessary instruction fetch access, it is also a factor that hinders performance improvement. Conventionally, prohibition of instruction fetching and cancellation of prohibition have been performed in hardware, and therefore prohibition of instruction fetching and cancellation of prohibition cannot be freely changed.

[Purpose of the invention]

The present invention solves the above-mentioned problems, and provides a method for prohibiting and canceling the prohibition on fetching instructions in an information processing device, which allows the prohibition on fetching of unnecessary instructions and the cancellation of the prohibition. The purpose is to

[Structure of the invention]

For this purpose, the method for prohibiting instruction fetching and canceling the prohibition in the information processing device of the present invention includes a plurality of instruction buffer registers for storing prefetched instructions, and a method for disabling instructions stored in the plurality of instruction buffer registers. A selector for selection, a pipeline control unit for controlling execution of instructions output from the selector, and an instruction control unit for controlling fetching of instructions, and the instruction control unit is configured to prefetch instructions. , the pipeline control unit stores phase information indicating the work to be processed in the phase.
In an information processing device having a plurality of tags and configured so that control information of a phase tag is transmitted to a subsequent phase tag, the pipeline control section is provided with a latch circuit and a control memory, The instruction control unit is configured to prohibit or cancel instruction fetching in accordance with the output of the latch circuit, and the control memory contains a plurality of control words including instruction fetch prohibition information and next address information. The control memory is read and accessed by the operation code of the instruction input to the pipeline control unit or the next address information, and the control word read from the control memory is the first one. This is characterized in that the instruction fetch prohibition information in the control word is set in the phase tag and latched in the latch circuit.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention;
FIG. 3 is a diagram showing an outline of a phase tag, FIG. 4 is a diagram showing a detailed example of a phase A tag, and FIG. 5 is a diagram showing an example of the configuration of a CS (control memory) to which the present invention is applied. , FIG. 6 is a diagram showing an example of pipeline processing in the present invention, and FIG. 7 is a diagram showing an example of the configuration of the instruction control section in the present invention. In the figure, 1 is a storage device, and 2 to 4 are instruction buffers.
Register, 5 is a selector, 6 is a pipeline control section, 7 is an instruction control section, 8A is a phase A tag, 8
B is Phase B tag, 8C is Phase C tag, 8
D is Phase D tag, 8E is Phase E tag, 9
is a latch circuit, 10 is a CS (control memory), 11 is a B register, 12 is an X register, 13 is a D register, 14 is a work 1 register, 15 is a work 2 register, 16 is a selector, 17 is an ADDER (adder) ), 18 is a register, 19 is an instruction fetch request generation circuit, 20 is an instruction buffer register clock control circuit, and 21 is an interlock control circuit for instruction fetch requests.

In FIG. 2, instructions are read from storage device 1 and stored in instruction buffer registers 2 to 4, and the instructions stored in instruction buffer registers 2 to 4 are sent to pipeline control unit 6 through selector 5. The instruction control section 7 performs instruction fetch control, and the pipeline control section 6 performs control for processing instructions in a pipeline manner. In the pipeline control unit 6, information is read from the CS 10 to the phase A tag 8A in phase A of the instruction execution process. Phase A tag 8A is CS10
This is a register that receives information read from CS1.
The contents read from 0 are always stored in this register once. This register is called the Phase A tag because it is stored within Phase A of the pipeline. Therefore, as shown in FIG. 3, as instructions flow from phase A to phase F of the pipeline, the output of phase A tag 8A also transfers information to a similar register (phase B tag 8B) in phase B. Then, in the same way, phase C tag 8C, phase D tag 8D, phase E
Shifting to tag 8E. The information in this tag (register) indicates the function (work) that must be processed in each phase. For example, in phase A, as shown in FIG. 4, input control of an ADDER 17 for operand address calculation is mainly performed. In FIG. 4, the selector 16 selects the
The contents to be input into inputs 1 to 3 of ADDER 17 are selected. For example, Phase A tag 8A
When BIT0 and 1 are “01”, the contents of the B register 11, when they are “10”, the contents of the work 1 register 14, and when they are “11”, the contents of the work 2 register 15 are determined by the selector 16. Selected and ADDER
17 input 1. Also, if BIT2 and 3 of phase A tag 8A are "01", the contents of X register 12, if "10", the contents of work 1 register 14, and if "11", the contents of work 2 register 15. The content is selected by the selector 16,
It is input to input 2 of ADDER17. Phase A
When BIH4 and 5 of tag 8A are "01", the contents of D register 13 are sent to the selector 16, when they are "10", the contents of work 1 register 14 are sent to the selector 16, and when they are "11", the contents of work 2 register 15 are sent to the selector 16. and input to input 3 of ADDER17. Register 18 stores the output of ADDER 17. In the present invention, when a specific bit of the phase A tag 8A, the INH IFCH LCH bit, is "1", the latch circuit 9 is set to "1", and the INH IFCH LCH bit of the phase A tag 8 is set to "0".
When this occurs, the latch circuit 9 is set to "0". The output of this latch circuit 9 is sent to the instruction control section 7. In the instruction control section 7, processing is performed to prohibit instruction fetching when the latch circuit 9 is set to "1". FIG. 5 shows an example of the configuration of CS. When the command LOAD PSW is input to the pipeline control unit 6, operation code X▼82▼ is input as address information.
Data is read from the CS 10, and this data is set as the phase A tag 8A. Phase A tag 8
AINH IFCH Has multiple control bits including the LCH bit and the next (NEXT) address field.
The next address part is used, for example, as follows.
Some of the instructions are executed in one flow, while others are executed in multiple flows, and the next address section indicates the storage address of the phase A tag 8A of the next flow. The instruction LOAD PSW is executed by multiple flows. INH IFCH of first phase A tag 8A associated with LOAD PSW
The LCH bit is set to "1", and the INHIFCH LCH bit of the last phase A tag 8A is set to "0". INH IFCH of intermediate phase A tag 8A
The LCH bit is also set to "1". FIG. 6 shows an example in which one machine language instruction is executed by multiple flows. As mentioned earlier, LCAD
An instruction called PSW is also executed by multiple flows. To explain the example of LOAD PSW, in the first flow, from CS10
LOAD PSW operation code X▼82▼
is read out. INH IFCH LCH bit is “1”
Therefore, the latch circuit 9 is set to "1". When the instruction control section 7 reads that the latch circuit 9 is set to "1", the instruction control section 7 performs a process of prohibiting subsequent instruction fetching. Then, as the processing by the LOAD PSW progresses and reaches the final nth flow, the INH IFCH LCH bit is set to "0", so the latch circuit 9 is set to "0". When the instruction control circuit 7 reads that the latch circuit 9 is set to "0", the instruction control section 7 cancels the inhibition of instruction fetching. In this way, the present invention provides the following features:
The prohibition of unnecessary instruction fetching and the cancellation of prohibition are performed based on the read data of the control memory. FIG. 7 shows an example of the configuration of the command control section. In FIG. 7, in the instruction fetch request generation circuit 19, if there is no instruction fetch prohibition condition, that is, if the output of the latch circuit 9 is "0", or if there is no interlock,
Issues an instruction read request to the S unit (storage control unit, not shown), and when an acceptance signal is sent from the S unit, notifies the instruction buffer register clock control circuit 20 of the S unit acceptance signal. . As a result, the instruction buffer register clock control circuit 20
Shifts the contents of a register. In the interlock control circuit 21 for instruction fetch requests, when an interlock signal due to memory wait is sent from the S unit, the instruction fetch request generation circuit 19
interlock. The instruction fetch request generation circuit 19 determines whether there is an interlock or an instruction fetch prohibition condition (the output of the latch circuit 9 is "1").
In this case, issuing an instruction retrieval request to the S unit is prohibited.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the prohibition of instruction retrieval or the cancellation of the prohibition during execution of an instruction or within an instruction is performed based on the read data of the control memory. It is possible to freely prohibit or cancel the prohibition of preemption, and it is possible to improve performance.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the instruction execution process of a pipeline computer that uses the advance control method, and FIG.
A block diagram showing an embodiment, FIG. 3 is a diagram showing an outline of a phase tag, FIG. 4 is a diagram showing a detailed example of a phase A tag, and FIG. 5 is a CS to which the present invention is applied.
(control memory); FIG. 6 is a diagram showing an example of pipeline processing in the present invention; FIG.
The figure is a diagram showing an example of the configuration of an instruction control section in the present invention. In the figure, 1...Storage device, 2 to 4...Instruction buffer register, 5...Selector,
6...Pipeline control unit, 7...Instruction control unit, 8A
...Phase A tag, 8B...Phase B tag, 8C
...Phase C tag, 8D...Phase D tag, 8E
...Phase E tag, 9...Latch circuit, 10...CS
(control memory), 11...B register, 12...X register, 13...D register, 14...work 1 register, 15...work 2 register, 16...selector,
17...ADDER, 18...Register, 1
9... Instruction fetch request generation circuit, 20... Instruction buffer register clock control circuit, 21... Interlock control circuit for instruction fetch requests.

Claims (1)

[Claims] 1. A plurality of instruction buffer registers that store prefetched instructions, a selector that selects the instructions stored in the plurality of instruction buffer registers, and execution of the instruction output from the selector. and an instruction control unit that controls the fetching of instructions, the instruction control unit is configured to prefetch instructions, and the pipeline control unit is configured to perform tasks to be processed in a phase. The phase/phase data containing control information indicating the
In an information processing device having a plurality of tags and configured so that control information of a phase tag is transmitted to a subsequent phase tag, the pipeline control section is provided with a latch circuit and a control memory, The instruction control unit is configured to prohibit or cancel instruction fetching in accordance with the output of the latch circuit, and the control memory contains a plurality of control words including instruction fetch prohibition information and next address information. The control memory is read and accessed by the operation code of the instruction input to the pipeline control unit or the next address information, and the control word read from the control memory is the first one. 1. A method for prohibiting and canceling prohibition of instruction fetch in an information processing apparatus, characterized in that instruction fetch prohibition information in the control word is set in a phase tag and latched in the latch circuit.