JPH01263727A - Data processor - Google Patents

Abstract

PURPOSE:To effectively use an external bus by preventing the execution of a wasteful instruction fetching and duding after an instruction to branch an execution stage and generate a jump surely and an instruction to generate the condition of a processor are inputted in a data processor to execute an instruction pipeline processing. CONSTITUTION:An E stage 35 executes the operation designated during the instruction code for an operand inputted from an F stage 34. An access request from an IF stage is always executed, and a bus interface circuit 38, when the access request from respective stages is not executed, executes the prefetching of the instruction. When a D stage 32 detects that an instruction to execute surely the branching with the E stage 35 is completely inputted to a D stage 32, the instruction prefetching after it is not executed until a pipeline initialization due to the E stage occurs.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention reduces unnecessary path accesses associated with pipeline initialization, efficiently operates the multi-stage pipeline processing machine IB, and achieves high processing capacity. The present invention relates to a data processing device.

[Conventional technology]

Figure 30 shows the conventional data processing f! An example of the pipeline processing mechanism used in the p device is shown below. 611 is an instruction fetch stage (IF stage), IIzi/i instruction decode stage (CD stage), 61-digit operand address calculation stage (A stage), 64-digit operand fetch stage (F stage), and 611 is an instruction execution stage (E stage). )5. Akira is the external bus interface section.

The 1F stage 311 issues an access request to the external bus interface city, fetches all instruction codes from the 5 memory, and outputs them to the D stage □□□.

D stage (2) is input from IF stage 60,
The instruction code is decoded and the decoded result is output to the iA stage β layer.

A stage Jun calculates the effective address of the operand specified in the instruction code, and requests access to the external bus interface 7 aids section if necessary. The address is indirectly referenced 4 times, and the calculated operand address is output to calculation stage 1 (2).

y stage l'4 is the operan input from A stage K)! According to the address, an access request is issued to the external bus interface section and the operand is fetched from the memory. The fetched operand is output to E stage '1. E stage i is a de stage; is the operation specified in the instruction code based on the operands input from the rumors? Execute. Furthermore, if necessary, an access request is sent to the external bus interface unit (to) and the result of the calculation is stored in the memory. If there is no access request from the stage to A or F, the external bus interface section (to)
Instructions are prefetched in response to an access request from the F stage.

With the pipeline processing mechanism described above, the process specified by each instruction is broken down into five parts, and the specified process is completed by executing all five processes in order. Each of the five processes can be operated in parallel on a different metal Vc, and ideally, five instructions can be processed simultaneously using the five-stage vibe line processing mechanism described in ``2'', and pipeline processing is possible. It is possible to obtain a data processing device that has up to five times the processing power as compared to the case where this is not performed.

[Problem to be solved by the invention]

As mentioned above, pipeline processing technology has the potential to significantly improve the @ processing capacity of data processing equipment.
Widely used in high-speed data processing equipment. but,
Pipelining also has some drawbacks, and instructions are not always executed in ideal conditions. One of the problems in pipeline processing is the execution of branch instructions that disrupt the instruction sequence. Vibration line treatment shown in Figure 30
In the conventional data processing J11 device, in which the branch instruction iBX stage t1 processes the branch destination instruction i1F stage 60, the branch instruction execution 1 (the pipeline is significantly disrupted and the branch instruction An instruction access request is also executed.FIG. 81 shows how a branch instruction is fetched and executed in a conventional data processing device, including all external bus operations.

The 31st ri-i instruction 3 is a branch instruction. When instruction 8 is executed, instructions 4 and 5 are already being processed in the pipeline.
．． Instruction 6 is canceled and instruction 7 is newly processed from IF stage 611.

Instruction 3 is executed at E stage (VC instruction 4,
What is the processing of instruction 5 and instruction 6 respectively? Stage 1, A stage I: 1 Progress is slow, the accompanying access requests are input to the external bus interface section (to), all unnecessary accesses are executed, and the 111 of the device on the system is
There are disadvantages in that the 11m register value t is corrupted and the system basketball is occupied meaninglessly. This is because the power Q share of execution that is canceled after the execution of this useless access branch instruction is performed as a branch instruction, and the problem is that the more stages of pipeline processing there are, the higher the possibility that this useless access will occur. arise.

Furthermore, as the operating speed of the logic elements that make up the pipeline increases and the processing time at each stage becomes shorter, the time taken by the external bus becomes a processing bottleneck, resulting in wasted access processing efficiency? It becomes a factor that makes things worse.

The present invention has been made in view of the above-mentioned circumstances, and aims to provide a data processing device that can easily cope with an increase in the number of stages in a pipeline mechanism and that does not perform unnecessary path accesses. .

[Means to solve the problem]

In order to reduce wasteful accesses caused by branch instructions, instructions are added to the rC%D stay cap. At the decoding stage, it is determined whether the instruction causes a branch or jump, and if a branch or jump occurs, the IF stage and D
A means for stopping the operation of the stage is provided.

[Effect]

In the data processing device of the present invention, when an instruction that always causes a branch or jump is decoded, the instruction fetch and decode processing is temporarily stopped, and the Vcm
Resume processing of Refufu Etch Code.

[Example]

t11 Instruction format of the data processing device of the present invention The instructions of the data processing device of the present invention have a variable length in units of 16 bits, and there are no instructions with an odd number of bytes.

The data processing device of the present invention has a particularly devised instruction format system in order to format frequently occurring instructions in a short format. For example, for a two-operand instruction, there are two formats: a general format that basically consists of 4 bytes + an extension and can use all addressing modes, and a shortened format that can only use instructions with high gradients and addressing modes. There is a format 0 FIGS. 4 to 18 show instruction formats in the data processing apparatus of the present invention. Figure 4 is a description sequence of the instruction format. Figure 5 shows the format of the abbreviated memory register operation instruction. FIG. 6 Fi = Format of compressed register-register operation command. FIG. 7 shows the format of a literal-memory operation instruction. FIG. 8 7-order of #'i immediate-memory operation instruction. Figure 9. General format of Fil operand instruction. FIG. 1O I/'i Wound - General Format of Instructions requiring Overland Memory Reads. Figure 11 shows the format of an instruction whose first operand is an 8-bit immediate value. Figure 12 shows the format of an instruction whose first operand is only address calculation. Figure 18 shows the format of a short branch instruction. The meanings of the symbols appearing in the diagram are as follows.

1: Part where the opcode is placed 4 #: Part where the literal or immediate value is placed Ka: 8 mini 8
Part Sh for specifying an operand in bit-type addressing mode: Part Rn for specifying an operand in 6-bit abbreviated addressing mode: Part for specifying an operand on a register using a register number The format is as shown in Figure 4. The right side is the LSB side and has a high address. The instruction format cannot be determined without looking at the two bytes of address N and address N+1, but this is because the instruction is always 16 bytes.
This is because it is assumed that data is fetched and decoded in units of bits (2 bytes).

In the data processing apparatus of the present invention, in any seven-order case, the extended part of the Paj ish of each operan F is always placed immediately after the halfword containing the basic part of its Ka or tish. This always takes precedence over immediate data implicitly specified by the instruction and the extended part of the 8-instruction. therefore,
For instructions of 4 bytes or more, the operation code of the instruction may be divided by the extension section of FXa.

Furthermore, as will be described later, in the multi-stage indirect mode, even if an extension part is added to the extension part in the vertical position, that part is given priority depending on the operation code of the next instruction. For example, the first halfword contains Kalr and the second halfword contains JC.
6-byte instruction IM including a2f and up to the third halfword,'? think of. Since the multi-stage indirect mode is used for mal, the multi-stage indirect mode extension part is included in addition to the normal extension part. At this time, the actual instruction bit pattern consists of the instruction halfword (including the basic part of Eal), the extension part of Pal, the multi-stage indirect mode extension part of F1a1, and the second half word of the instruction (including the basic part of PThafl). ], the extension of El, and the third halfword of the instruction.

t 1.1) White linear two-operand eT order Figures 5 to 8 14f': Shown in the condensed form of the two-operand eT order.

FIG. 5 shows the format of memory register @arithmetic command. This format includes TJ-f Or m a 1: where the source operand side is the memory, and S-f Or m a 1: where the destination operand side is the memory.
In L-format, sh is the source operand specification field, Rh is the destination operand register specification field, and IRRlj: sh operand size specification 5r. *-A on register
-The size of the destination operand is 82
Fixed to bit. 1/If the size of register side and memory side are different and the size of source side (1) is small, L(
Sign extension is performed , 1? is 8h Toy orma □ Destination operand specification field, Rh1d: Source operand register specification field l', RRFi, sh operand size specification field. The size of the source operand placed on the 1/register is fixed at 82 bits. If the size of the register side and the memory side are different, and the size of the source side is large, the overflow portion is truncated and overbroach check is performed.

FIG. 6 shows the format (R-format) of the register-register operation instruction. Rn is a designation field of the destination register; Rm is a designation field of the source register. The operand size is only 32 bits.

Figure 7 shows the format of literal-memory operation instructions (
Q-format). MM[Destination operand size specification field, she is a literal source operand specification field, she is a destination operan V specification field.

FIG. 8 is the format of the Vi-kushin-memory start command. MM is a specification field for the operand size (both 4 for the source and size) and a specification field for the destination operand. l-for
The immediate size of mat is 8, 16, 32 in common with the operand size on the -i'S'' staynation side.
Bit tonnage, zero extension, and sign extension are not performed.

(11 single-operand one-operand instruction Figure 9 shows the one-operand format of the one-operand instruction (G
l-format). This field specifies the MM operand size. Some GM-f Or
In the mat instruction (is 4, Eθ, there are extensions other than the extensions. Also, there are instructions that are not used. This is a single-layer format for operands.The 7-order format includes 1 and n2, which are instructions that have a maximum of two operands in the single-layer fretting mode specified by 58 bits. The number itself may be three or more.13 Figure 1O shows an instruction (1) in 7-way IG-format l whose first operand requires all memory reads. EaM is the specification field of the destination operand, MM is a destination operand size specification field, EaRij is a source operand specification field l-''%RR is a source operand size specification field.

In FIG. 11, the first operand is in 7-bit format (FX-format).

M is a field specifying the destination operand, MM is a field specifying the size of the destination operand, and element is the source operand value.

K-format and i-romat! :Is there something similar in terms of aai, or is there a big difference in terms of way of thinking? What is K-format? Operando membrane shape (
G-format), and is a derivative of source operan F
The size of the destination operand is fixed at 8 bits, and the size of the destination operand can be selected from 8, 16, or 82 bits. In other words, assuming an operation between different sizes, 2
The bit source operan F is zero-extended or sign-extended.

On the other hand, 1-format is a shortened form of the immediate value pattern that is frequently used especially in transfer instructions and comparison instructions.
7'-Size of operand and destination operand are equal.

FIG. 12 shows the format of an instruction whose first operand is only address calculation (GA-format).

EaW Id is the specified field of destination operan F. %WW is the specified field of destination operan F size, and KaA is the specified field of nonce operan F. The execution address calculation result itself is used as the source operand.

FIG. 13 shows the format of a short branch instruction. CCCC is a branch condition specification field, disp:
8 is a displacement specification field with respect to the jump destination; in the data processing device of the present invention, when specifying displacement with 8 bits, the specified flik in the bit pattern is multiplied by 2 to obtain the displacement jet (1.4) Addressing mode of the present invention How to specify the addressing mode of a data processing device using registers? There is an abbreviated form that is specified using 6 bits, and a general form that is specified using 8 bits.

If an undefined addressing mode is specified, or if a combination of addressing modes that is semantically incorrect is specified, a reserved 6th command exception will occur, similar to when an undefined instruction is executed. Invokes exception handling.

This applies when the destination is in immediate mode, or when immediate mode is used in the addressing mode specification field that should involve address calculation.

The symbols used in the formats shown in FIGS. 14 to 24 are as follows.

Rn Register designation (ah) Designation method in 6-bit abbreviated addressing mode (Ka) Designation method in 8-bit general addressing mode The portion surrounded by dotted lines in the format diagram is shown in expanded form s1.

(1,4,1) Basic Addressing Modes The data processing device of the present invention supports various addressing modes. Among these, the basic addressing modes supported by the data processing device of the present invention include register direct mode,
There are register indirect mode, register relative indirect mode, immediate value mode, absolute mode, PC relative indirect mode, stack pop mode y1 stack bush mode.

In the register 11 contact mode, the contents of the register are used as operands. The format is shown in number 14. Rn indicates the number of the general-purpose register.

Register indirect mode 'tf' takes the contents of the memory as the address and the contents of the register as the operand. The format is shown in FIG. Rn indicates the number of a general-purpose register.

There are two types of register relative indirection depending on whether the displacement value is 16 bits or 32 bits. Each operand is the contents of the memory, which is the value of the contents of the register plus the displacement value of 16 bits and Vi82 bits. The format is shown in FIG.

Rn indicates the number of a general-purpose register. disp: lfl
and disp:L2 ij indicate a 16-bit displacement value and an 82-bit displacement value, respectively. Displacement values are treated as signed.

In the immediate value mode, the bit pattern specified in the instruction code is treated as 24 numbers and used as an operand. The format is shown in FIG.

imm data immediately shows 1m. imm data
The size of is specified in the instruction as the operand size.

Absolute mode indicates whether the address value is represented by 16 bits or 3
There are two types depending on whether it is indicated by 2 bits. O format ij in which all operands are d in the memory whose address is the 16-bit or 32-bit bit pattern specified in the instruction iodine, respectively: f, , a as shown in FIG.
be: 16 and abs: 32 indicate 16-bit and 82-bit addresses, respectively.

abe: 16 Is the address indicated by the specified address value? Sign extend to 32 bits.

In PC#@pair indirect mode, whether the disk value is 16 bits or 2 bits: (There are two types depending on whether it is 2 bits or not.)17. −Sment value? Added value? Assume that an operation 27 is placed in 8 of the memories designated as 1/s. The format is shown in FIG. dj, sp: 115
and dj and 5p32 respectively indicate a 16-bit displacement value and a 2-bit displacement value. Disgraced values are treated as signed. The value of the program counter referenced in the PC indirect mode VC is the start address of the instruction including the operand. In the multi-stage indirect addressing mode, when the value of the program counter is referenced, it is similarly used as the base !$ value of the 1/kPc pair of the instruction-first application.

In stack pop mode, the contents of the memory addressed by the entire contents of the stack pointer (SP) are used as operands. After accessing the operand, Sp'ff is incremented by the operand size. Side to side.

When handling 32-bit data, after operand access, vcap is updated by (-4) Any specification of stack pop mode for operands of size 6B or H is possible, and hsF is updated by +1° +2. The format is shown in Figure 20.A reserved instruction exception occurs for operands for which the stack pop mode has no meaning.Specific examples of reserved instructions are:
write operand, reacl-mo+lfy-w
This is the stack pop mode specification for the rite operand.

In the stack bush mode, the contents of the memory that is Wk at 1/s after decrementing the contents of EP by the operand size are used as the operand. In the stack bush mode, SP is decremented before accessing the operand.

For example, 32 bit data? When handling 1/(, sp is updated by -4 in the operand access ml. It is also possible to specify the stacked button mode for operands of size B and H, and the h day P is -1° -2 respectively. The format is shown in FIG. 21, and a reserved program exception is generated for those that do not have stack mode for the f0 operand. Basically, the reserved instruction exception is the stack bush mode specification for the 'ij knee, rea (l operand, read-modj, fy-write operand).

(1, 4, 2) Multi-stage indirect attrend 1/twsing mode Complex atranging can also be fundamentally decomposed into combinations of addition and indirect reference.

Therefore, any complex addressing mode r can be realized by providing additions and indirect references as operation care addressing primitives and combining them arbitrarily. The multi-stage indirect addressing mode of the data processing apparatus of the present invention is addressing mode 1: based on this concept. Complex addressing modes are particularly useful for inter-module data references and AI language processing systems.

When specifying the multi-stage indirect addressing mode, in the basic AT 1/Tsing mode r specification field, select one of the eight methods of specification: register-based multi-stage indirect mode, PC-based multi-stage indirect mode, or absolute-based multi-stage indirect mode. Specify.

Register-based multi-stage indirect mode This is an addressing mode in which the value of the register 1/register is used as the base value for multi-stage peer addressing to be extended. Format ij: Shown in Figure 2z. Rn indicates the number of a general-purpose register.

The PC-based multi-stage indirect mode uses an addressing mode in which the value of the program counter is an extended multi-stage indirect addressing mode value.

The format is shown in Figure 23 VC.

Furnace-to-base multi-stage indirect mode)'' is an addressing mode in which zero is the base value of extended multi-stage indirect addressing.The format is shown in FIG. 24 VC.

The expanded multi-stage indirect mode specification field I read is used to add displacements, scale index registers (×1, ×2, ×4, × 8
), addition, and memory indirection.

The format of the multi-stage indirect mode is shown in FIG. Each field has the meaning shown below.

E-0: Multi-stage indirect mode Erin: Address calculation end tmp-a-) address of opera
ndl-0: No memory indirection tmp + disp + R1* SOa
le--m>tmpl-1: Memory indirect reference (tmp+disp+Rx*5ealθ)m-a
) t3111 pM-0: <Rx>k Used as index M-1: Special index <Rx>=0 IRx value not added to index value 0
) <RX> Use program counter as index value (RX-PCI <Rx>m9 ~ reserved D-0: 4-bit field d in multi-stage connection mode
4+if? Multiply r4 to correct the displacement,
Add this. d4 is treated as signed and is always multiplied by 1 (regardless of the size of the operand).

D-1: d specified in the extension part of multi-stage indirect mode
ispx (16/3 g pit) is the displacement saliva, and this is added.

The size of the extension part is specified in the d4 field.

d4-0001 dispx is ×2, ×4. for a 16-bit program counter. When x8 scaling is performed, an undefined value is entered as the intermediate value (tmp) after the processing of that stage is completed. Although the effective address obtained by this multi-stage indirect mode has an unpredictable value, no exceptions occur. Do not specify scheduling for the program counter.

The instruction format according to the multi-stage indirect mode is shown in Figure 16 and Figure 27. FIG. 26 shows variations on whether the multi-stage indirect mode continues or ends.

FIG. 27 shows variations in displacement size.

If a multi-stage indirect mode with an arbitrary number of stages could be used.

Since the compiler does not need to differentiate between cases based on the number of stages, it has the advantage of reducing the burden on the compiler. This is because even if the slope of multi-stage indirect references is less than M vc , the compiler must always be able to generate correct code. For this reason, the format
Any number of stages is possible.

(1,5) Exception processing In the processing device of the present invention, in order to reduce the software load,
In the data processing device of the present invention, which has abundant exception handling 5N capabilities, exception handling includes re-execution of instruction processing (exception),
They are divided into three types and are named: those that complete instruction processing (traps), and interrupts. Furthermore, in the data processing apparatus of the present invention, these three types of exception handling and system failure are collectively referred to as E/T.

(2) Structure of Functional Blocks FIG. 28 shows a block diagram of the data processing apparatus of the present invention. Functionally, the inside of the data processing device of the present invention can be broadly divided into an instruction fetch unit 5D.

Instruction decoding section 5, PC calculation section 63. It is divided into an operand address counter, a micro 10M multiplication unit, a data calculation unit, and an external path interface unit 5η. Second
In addition, in FIG. 8, an address output circuit for outputting addresses and cpn to the outside, and a data input/output circuit for inputting and outputting data to and from the outside of the CP port are shown separately from the orange function block section of m-.

(z, 1) Instruction fetch unit The instruction fetch unit 5Q includes a branch buffer, an instruction queue buffer, its control unit, etc., and determines the at 1/s of the instruction to be fetched next to the branch buffer and C
Rough fetch instructions from memory outside the PU. Also registers instructions to the branch buffer.

The branch buffer has a small scale 'T': Therefore, it is used as a separate branch cache.The branch buffer has a function very similar to the branch target buffer (BTB). Ganshofl
It is detailed in R=202041.

The address of the next instruction to be fetched is calculated by a dedicated counter as the address of the instruction to be input into the 6-instruction buffer. VC when a branch or jump occurs,
, a sassy and cool address was forwarded to me by PcIa4r Akirabe Mori and Deke Ensou1ou.

CP] ■When fetching instructions from external memory,
Address output circuit ii+9 for the instruction code to be fetched through the external bus interface 7 aids section bη
The instruction code is output from the CPU to the outside, and the instruction code is fetched from the data input/output circuit.

Among the buffered instruction codes, the instruction decode unit a1z''T: outputs the instruction code to be decoded next to the instruction decode unit.

(2, 2) Instruction decode section Instruction f code section In the 5 units, the operation code in the instruction is basically JV
It is decoded in units of C16 bits (halfwords).

This block has an FHW degogue 6 that decodes the opcode contained in the first halfword, an NFI (W decoder, and an addressing mode that decodes Contains a decoder.

In addition, there is a decoder 2 that further decodes the output of the F Also included is an address calculation conflict checking mechanism.

Instruction code input from instruction fetch section? 0 = 6 bytes per 2 drives? decode.

Among the decoding results, information related to the operation knowledge in the data calculation unit 1 is sent to the ROM unit 6, and information related to the operand address calculation is sent to the operand address calculation unit vc, PC agency 10WVc-related. Information ke PC calculation department D (to), 7h, zono 1. Output.

(N, 3) Micro ROM section The micro ROM section includes the main (t) data calculation section - micro program that controls everything.
, micro sequencer, micro instruction decoder, etc. Microinstructions are read out from the mic rJROM every 2 clocks i2. In addition to the sequence processing indicated by the microprogram, the microsequencer handles exceptions, interrupts, and playing cards (these three are casually called "J" 工T) in terms of hardware. The Amada micro ROM section also manages the store buffer.

Input to the micro ROM section are interrupts that do not depend on instruction codes, flag information based on arithmetic execution results, and outputs from instruction decoding such as the output of the decoder 2. The output of the micro-decoder is mainly output to the data operation register, but some information, such as other preceding hot press abort information due to the execution of the jump instruction, is also output to other blocks -\.

(2, 4) Operand address calculation section Operand address total '11. The block 541 is hard-wired frill (ill) by the ↑N information related to the operand address calculation output from the address decoder of Takorei Decode Jasakura, etc. This block performs most of the processing related to the operand address calculation. A check is also made to see if the address of the memory access for indirect memory addressing or the operand address falls within the memory pressure mapped I10 area.

The address calculation result is sent to the external bus interface hη. The values of general-purpose registers and program counters required for address calculation can be input from the data calculation section.

When performing memory indirect addressing, the address output circuit is connected to the CP through the external bus interface section.
σ Outputs the memory address to be referenced externally, and decodes the indirect address @ input from the data input/output section to the instruction F
Part 6 is passed through as is and fetched.

(16) PC calculation unit The pc calculation unit IS:l is under wired control by the information related to pc calculation output from the instruction decoder r unit 6, and calculates the pc value of the instruction. The data processing device of this patent has a variable length instruction set, and the length of the instruction cannot be determined until the instruction is decoded. The PC calculating section 61 creates the PCI of the next instruction by adding the instruction length t output from the instruction decoding section to the PC@ of the instruction being decoded. When the instruction decoding unit 54 decodes a branch instruction and instructs a branch at the decoding stage, the instruction decoder 54 adds the branch displacement to the PC@ of all branch instructions instead of the instruction length so that the PC of the branch destination instruction (iii In the data processing device of the present invention, branching to a branch instruction at the instruction decoding stage is called pre-branch.

It is.

The calculation results of the PC calculation unit are output as the PC of each instruction along with the instruction decoding results, and at the time of pre-branch, the calculation results are output as the instruction 7 as the address of the command to be decoded first.
Output to the construction section.

It is also used as an address for predicting the branch of the next instruction to be decoded by the instruction decoding unit Sakura. The branch prediction method is described in detail in Machihara Sho 62-8194.

(2, 6) Data calculation unit The data calculation unit 1 is controlled by a microprogram,
According to the output information of the micro ROM group, the registers and arithmetic unit execute the operations necessary to realize the function of each instruction. When the operand to be operated on is an address or an immediate value, the address or immediate value calculated by the operand address calculation section is obtained by passing through the external path interface section bη. In addition, if the operand to be operated on is data stored in the memory external to cpσ, the path interface unit 671 outputs the address calculated by the address calculation unit grab from between the at and address output circuits, and outputs the address from the memory external to cpσ. The fetched operand is transferred to the data input/output circuit 6 (
In some cases, it can be obtained from

Clearance devices include ALσ, barrel shifters, priority encoders, counters, and shift registers. The registers and the main arithmetic units are connected by 8 paths.%
One microinstruction that instructs one register-to-register operation? Processed in 2 clock cycles.

When it is necessary to access memory outside the CPσ during data calculation, the address ? Output to the outside of CPσ, data input/output circuit A
Fetch the desired data through I.

When storing data in the external memory cpσ, output the address from the address output circuit through the entire external bus interface, and at the same time output the data 1kcPσ externally from the data input/output circuit (to). Efficiently store operands. In order to do this, there is a 1lt4-byte store buffer in the data calculation section.

When the data operation section obtains a new instruction address by processing a jump instruction or handling an exception, it outputs this to the instruction fetch section 60 and the PC calculation section.

(g, 7) External path interface unit Does the external path interface unit 571 communicate with the external bus of the data processing device of this patent? Separately.

All memory accesses are performed in clock synchronization and can be performed in a minimum of two clock cycles.

Access requests to memory are made by the Kinei fetch unit fi11.
．． The address calculation unit 5 (and the data calculation unit (6) are generated independently from each other. The external bus interface unit arbitrates these memory access requests. Furthermore, the memory and CPσ
? The access data at the memory address that straddles the 32-bit (word) aligned boundary fr, which is the data bus size to be connected, detects that the data boundary crosses the word boundary once within this block. This is done by breaking it down into two identical memory accesses.

Conflict prevention processing when the operand to be briefly fetched and the operand to be stored overlap!・Also performs bypass processing from Aobeland to fetch operand.

(3) Pipeline Return The pipeline processing of the data processing apparatus of the present invention has the configuration shown in FIG. The instruction fetch stage (IP stage 6υ) performs a brief fetch, the decode stage (D stage (ri) performs instruction decoding, the operand address calculation stage (A stage C (3), performs operand address calculation), Microphone OR0M access (also called R stage) and operand glyfetch (
Especially called OF Steday (ro)? Perform operand blip etch stage CF stage ■), execution stage (Z
Stage c! 6) 5 membrane configuration? This is the basis of pipeline processing. In addition to the 1-stage store buffer at the E stage (up to), some high-performance models use a pipeline to execute instructions themselves, so there is actually a pipeline processing effect of 5 stages or more.

1F stage c3v is bus interface time N□□□
The OD status (to) which requests access to Kanayama, fetches the instruction code from memory and outputs it to D stage is I.
Decode the instruction code input from the F-steady Oη and complete the decode? A stage (to) [Output. A,
? Data (to) calculates the effective address of the operand specified in the instruction code, issues an access request to the bus interface circuit C if necessary, performs indirect address reference, and calculates the operand address calculation stage (to) Output to. The F stage [with] issues an access request to the bus interface circuit (to) according to the operand address input from the A stage Q, and fetches the operand from the memory.

The fetched operand ii' is output to the E stage (to). Chicken stage (to) i7: l' Is the operation specified in the instruction code for the operand input from the F stage [Yes]? Execute. Furthermore, if necessary, issue an access request to the bus interface circuit @ and check the calculation result? Store in memory. Aquias requests from the 1F stage are always issued, and the bus interface circuit @ does not issue instructions unless there is an access request from each stage.
Do Tsuchi 2. However, at D stage (end) and E stage (
If it is detected that the instruction that always performs branch 2 is completely input to the D stage (to), the pipeline initialization by the E stage occurs and no subsequent instruction prefetch is performed.

Each stage operates independently of the other stages (7. Theoretically, the five stages operate completely independently. Each stage can be performed in one process? Minimum of two clocks. Therefore, ideally Pipeline processing progresses one after another every clock.

The data processing device of the present invention includes memory-to-memory calculations,
Although there are instructions such as memory indirect addressing that cannot be processed with just one basic pipeline/processing, the data processing device of the present invention is designed to perform as balanced pipeline processing as possible for these processes. Ru. Multiple memory operands? For instructions with multiple memory operands, pipeline processing is performed by dividing the instructions into a plurality of pipeline processing units (step codes) at the VC and decoding stages based on the number of memory operands.

For an example of how to decompose a pipeline processing unit, see Japanese Patent Application No. 1983.
-236456.

1' The information passed from F stage 6η to D stage (to) is the instruction code itself. The information passed from the D stage (to) to the A stage a is related to the operation specified by the instruction (called the D code), and information related to the address calculation of the operand (A:7-de(6)). There are two types. From A stage Q? The information passed to stage ■ is two types: R code @3 (!-), which includes the entry address of the microprogram routine and parameters to the microprogram, and F code (!-), which includes the address of the operand and access method instruction information. .

The information passed from the F stage (to) to the E stage (7) is two: E code 4, which includes operation 1 tlla information and literals, and S2 1''-, which includes t such as operands and operand addresses.E stage The code detected at a stage other than Zeng is E stage (to) VC.
E/T processing will not be started until this point is reached. E stage (
Only the commands being processed in (to) are in the execution stage, and the soundproofing being processed in the IF stage taEl-F stage (2) has not yet reached the execution stage. Therefore, the fact that the E-engine Tfi detected at a stage other than the E-stage (7) is recorded is simply recorded in the step code and transmitted to the next stage.

(8,1) Pipeline Processing Unit (8,1,1) Classification of Instruction Code Fields The pipeline processing unit of the data processing device of the present invention is determined using the characteristics of the format of the instruction set. As stated in section (1), the instructions of the data processing device of the present invention are 2
It is a variable length instruction in byte units, and the basic VC is configured by repeating (2-byte instruction basic part - 4-byte addressing extension part) Th1 to 8 times.

The instruction basic part often has an opcode part and an addressing mode specification part, and when index addressing or memory indirect addressing is required, instead of the addressing extension part (2-byte multiple indirect mode specification part 〇 to 4-byte addressing Extension part) is attached on any side. Also, depending on the instruction, a 2 or 4-byte instruction-specific extension section is added at the end.

The instruction basic part includes instruction opcodes, basic addressing modes, literals, etc.

Addressing extensions can be displacements, absolute addresses, immediate values, or branch instruction displacements. Instruction-specific extensions include the immediate value specification of the register mappny i'ormat instruction. FIG. 29 shows the characteristics of the basic instruction format of the data processing device of the present invention.

(8, 11) Decomposition of instructions into step codes The data processing apparatus of the present invention performs pipeline processing that takes advantage of the characteristics of the instruction 7 omant described above. At stage D (end) (
2-byte instruction basic 1fls + 0-4 byte addressing extension 1! Is).

(Multi-stage indirect mode specification section + addressing extension section) - Processed as one decoding unit in the extension section 1 specific to the spanning instruction. The decoding result of each time is called step code,
After the A stage (end), this step code is used as the unit of pipeline processing. The number of step codes is unique for each instruction, and when multi-stage indirect mode is not specified, one instruction is divided into a minimum of 1 step code and a maximum of 3 step codes. If the multi-stage indirect mode is specified, the number of step codes increases accordingly. However, this is only the decoding stage, as will be described later.

(8, 1, 3) Program counter management Step code y existing on the pipeline of the data processing device of the present invention
B may all be for different instructions, and the value of the program counter is managed for each step code.

Every step code 1'' has the program counter value of the instruction that is the source of that step code.The program counter value that is attached to the step code and flows through each stage of the pipeline is the step program counter (S
PC).

SPC is passed through pipeline stages one after another.

C8, 2)? ! The processing pot pipeline stage input/output step codes of the pipeline stage are named for convenience as shown in FIG. Also, the step code)'' is a process related to the opcode? line-, Micro R
There are two series: a series that becomes an OM entry address and a parameter for the E stage (to), and a series that becomes an operand for the microinstruction in the E stage (to).・(
8, 8, 1) Instruction fetch stage Instruction fetch stage (process y stage 0υ) Fetch the tf instruction from memory or branch buffer, input it to the instruction queue, and output the instruction code to the D stage (to). Input to the instruction queue is done in units of aligned 4 bytes.When fetching an instruction from memory, a minimum of 2 clocks are required for each aligned 4 byte.When the branch buffer is hit, the aligned 4 bytes are input. Bytes can be fetched every 1 clock.The output unit of the instruction queue is variable every 2 bytes, and up to 6 bytes can be output during 2 clocks.In addition, immediately after a branch, the instruction queue is bypassed and the basic instructions are It is also possible to transfer part 2 byte 1 directly to the instruction decoder.

Control of registering and clearing instructions in the branch buffer,
Management of prefetch destination instruction addresses and control of instruction queues are also performed in the engineering F stage 9p.

1F stage 0] There are path access exceptions when fetching the TKfl instruction from memory and address translation exceptions due to memory protection violations.

(8, 2, 2) Instruction decoding F stage The instruction decoding stage (D stage (to)) decodes the instruction code input from the IF steady C3
It is performed once per clock, and with one decoding p process, 0
~6 bytes of instruction code is consumed (instruction code is not consumed in output processing of step code including the return destination address of RKT#f6 instruction, etc.). A code, which is the address calculation information for the A stage (to), in one decode.
Approximately 85-bit control code and maximum 82-bit address 1, about 50-bit control code as D code (product) which is intermediate decoding result of 1 moxibustion information and operation code F and 8
Outputs bit literal information.

The D stage (2) also performs separate processing of the PC calculation unit for each instruction, branch prediction processing, prebranch processing for prebranch instructions, and instruction call output processing from the instruction queue.

Furthermore, the instruction that causes a branch or jump is decoded at the Be sure stage, and when it is confirmed that the instruction is completely taken into the D stage, the instruction is decoded? The operation is then stopped until a pipeline initialization signal from the E stage is input.

Ill detected at D stage (end)! There is an ITKfl reserved instruction exception and an odd address jump trap during pre-branch. Also, the process f to be encoded in the various E engineering Tfl step codes transferred from IF Steady 3η.
! p and transfer to A stage (toward). When E/T is detected, the D stage interrupts instruction decoding and thereafter stops operating until a pipeline initialization signal from the E stage is input.

(8, L3) Operand address calculation stage Operand address calculation stage (A stage @) t-1 processing is broadly divided into two.

One is a process in which the decoder 2 of the instruction decoding section 62 is used to perform a subsequent decoding F of the obecode F, and the other is a process in which an operand address is calculated using the operand address counter IE block diagram.

Post-stage decoding of the operation code) 'processing ff takes the D code ■ as input, and the register or memory t! It outputs an R code including the input pre-1'J, microprogram entry address, and parameters for the microprogram. Note that register and memory write reservations are based on whether the contents of the register or memory referenced in address calculation are on the pipeline? This is to prevent an incorrect address line from being rewritten by a preceding instruction. To avoid deadlocks, register and memory enrichment reservations are made for each instruction rather than for each step code. Regarding write reservations for registers and memory, please refer to the patent application 1986-14.
4394.

The operand address calculation process takes the A code 12 as input, performs a total of 1L addresses by combining addition and memory indirect reference between the operand address calculation sections according to the A code, and outputs the calculation result as an F code. At this time, a conflict check is performed when reading a register or memory in conjunction with address calculation, and if a conflict is indicated before the preceding instruction has finished writing to the register or memory, the preceding instruction will move to the E stage.
Is there any reason to include it? Wait until it finishes. It also checks whether the operand address or the address of memory indirect reference is included in the I10 area VC mapped to memory.

The E-TK detected at the A stage (toward) is outside the reserved instruction, outside the privileged instruction, outside the bus access sequence, address conversion exception, and deno (lag trap) due to an operand break point hit during memory indirect addressing.D code (6) Did the A code itself cause the E engineering Tl? If it indicates, the A stage a will not perform address calculation processing for that code and will notify the E engineering T code master and the F code. (81,4) The micro ROM access stage operand fetch stage (F stage) also has a large processing time.
Divided into two. One is the micro ROM access process, which is particularly called the R stage. The other is operand prefetch processing, especially called OF steady (b). The R stage (end) and the OF stage (2) do not necessarily operate at the same time, but operate independently depending on whether memory access rights can be acquired or not.

The micro ROM access process, which is the process of the R stage (up to), executes the R code to be used for execution in the next E stage. These are micro ROM access and micro instruction decoding processing to create E:I-do f, which is the lla code. When processing for one R code (2) is decomposed into two or more microprogram steps, the micro ROM is used for one time at the second stage, and the older R code waits for access to the micro ROM.

Micro ROM access to R code gH is performed at the time of execution of the last micro instruction in the previous E stage. In the data processing device of the present invention, most of the basic instructions are executed in one microprogram step, so in reality, micro ROM accesses to the R code are often executed one after another.

There is no E-engine Tfl that can be detected in the analysis at the R stage (end).

When the R code indicates a soundproofing process re-execution type EIT, the microprogram for that E/T heat press is executed, so the R stage (to) fetches the microinstruction according to the R code. R stage (to) when the R code indicates an odd address jump trap
It tells 1kE code 4. This is for a pre-branch, and if a branch does not occur at the E code (2) at the Z stage (end), the pre-branch is made valid and an odd address jump trap is generated.

(81,5) Operand Fetch Stage Operand Fetch Stage (OF Steady@) HaF Stage (Foundation)
Of the above two processes performed in , perform operand prefetch processing mk ◇ Operand prefetch? It takes the code ■ as input and outputs the fetched operand and its address as the Is code. One F code - specifies an operand fetch of 4 bytes or less regardless of the decoder F boundary. F code)'■ also includes the specification of whether or not to access the operand.Q, when transferring the operand address itself or immediate value calculated in A stage Q to E stage (to), operand prefetch is not performed. First, the contents of F code I are transferred as S code ■. When the operand to be prefetched and the operand to be written by the E stage (7) match, the operand prefetch is not performed from the memory, but is performed by bypass.

Further, for the VO area, operand prefetch is delayed, and operand fetch is performed after all preceding instructions are completed.

There are debug traps caused by a breakpoint hit for an E/T11-j path access exception, an address translation exception, and an operand prefetch that are detected in the OF steady state. ? E where the code (goods) is other than debug traps
When the code is displayed, transfer it to the day code),
Operand prefetch is not performed. When the F code r14 indicates a debug trap, the S code (7) is transferred to the F code (■), no operand fetch is performed, and the debug trap is transmitted to the C code (■).

(8, 2, 8) Execution stage Execution stage (to E stage) E code-1S code-yH2 Operates manually. This E stage (up to) is the stage for executing instructions, and all processes performed in the stages before F stage (2) are prerequisites for stage (up to). When a jump instruction is executed or PIT processing is started at the E stage (toward), the I
All processes from F stage 61 to F stage are invalidated. The E stage (to) is controlled by a microprogram and executes instructions by executing a series of microprograms starting from the microprogram entry address indicated by R code 4.

Reading of the micro ROM and execution of micro instructions are performed in a pipelined manner. Therefore, when a branch occurs in a microprogram, one microstep becomes available. Furthermore, the E stage (toward) can also store operands within 4 bytes and process the next microinstruction execution key line by using the store buffer in the data operation section.

At the E stage (end), the write reservation for the registers and memory made at the Ir1k stage a is canceled after the operand is written.

Furthermore, when a conditional branch instruction causes a branch at the E stage (end), the branch prediction for that conditional branch instruction was incorrect, so the branch history is rewritten.

Bus access exception, address conversion exception, debug trap, odd address jump trap, reserved function exception, invalid operand outside column, reserved stack format exception, division by zero trap, unconditional There are traps, condition traps, delayed context traps, external interrupts, delayed interrupts, reset interrupts, and system failures.

All EiITs detected at E stage (end)
Processing is the R code threat and S code (
The E-technical process reflected in (to) is not necessarily processed as an E-technical process. Detected between IF status 61 and F stage (to), but the preceding jump instruction or stage (to)
All Fli r T,' that did not reach the E stage (toward) due to reasons such as execution were canceled. This means that the instruction that caused KITi was never executed in the first place.

External interrupts and delayed interrupts are placed at the E stage (up to) at the end of the soundproofing.
Direct reception is made, and the necessary processing is executed by the microprogram. Processing of other various types of E/T is also performed by microprograms.

(8, 8> State control of each pipeline stage Each stage of the pipeline has an input latch and an output latch, and basically operates independently from other stages.The processing performed one stage before each stage tri Once completed, the processing result is transferred from the output latch to the input latch of the next stage, and when the input latch of the own stage has all the input signals necessary for the next process, the next process starts.

In other words, in each stage, all input signals for the next processing output from one or both stages are valid, and when the current processing result is transferred to the input latch of the subsequent stage and the output latch becomes empty, the next start processing.

Does each stage work? All input signals must be available at one clock timing before starting. If the input signal is not ready, the stage goes into a waiting state (waiting for input). When transferring from the output latch to the input latch of the next stage, the input latch of the next stage must be in an empty state, and even if the input latch of the next stage is not empty, the pipeline stage will wait until the fall. (Waiting for output). If the necessary memory access rights cannot be obtained, if a wait is inserted into the memory access being processed, or if other pipeline conflicts occur, the processing itself at each stage will be delayed.

141 Execution of Instructions with Branches Execution of instructions with transitions from one stage to another, such as a jump in the execution stage, in the pipeline processing of the data processing device of the present invention will be described in detail in accordance with the description in 131. These instructions include a jump instruction (, TMP instruction) that specifies the jump destination address in any addressing mode, a subroutine return instruction (RTB instruction) that requires reading the jump destination address from external memory, and an instruction that changes the state of the processor ( LDC command) is included.

Is figure 8g JM? Indicates the bit pattern of the instruction.

The type of instruction is determined from the first 1 byte, and the first 1 byte
The type of addressing mode used in the instruction is determined by e. This instruction can use all addressing modes mentioned in (1, 4), so
The instruction length becomes zero for each addressing mode used. If the jump destination address is specified in one of the basic addressing modes described in (1, 4, 1), register indirect, stack pop, or stack bush, the instruction length is 4'byte, immediate value. , absolute, and indirect displacements are 16 bits, the instruction length is 7141 flbytes.

Similarly, if the displacement is 82t)it, the instruction length is 5 bytes. The destination address is (1
, , 4, and 2), the instruction length differs depending on how many times the multi-stage indirect reference is performed.

FIG. 88 is a flowchart showing the operation of the 7 MP instruction. After the instruction decoding is completed, the jump destination address is calculated according to the addressing mode shown in FIG.
Stage, and based on the calculation result, jump at E stage. If the addressing mode F is a multi-stage indirect mode F, address calculation is repeated until the multi-stage indirection is completed.

FIG. 34 shows the bit pattern of the 1/(RT8 instruction. This instruction is always the 2b) rte instruction. FIG. 35 shows the entire operation of the command. After instruction decoding F, I! ! Fetch the current stack top on the stage and jump to the destination address indicated by its contents.

FIG. 36 shows the bit patterns of the LDC instruction (2) specified by the first operand 1EaA, and the bit pattern of the KLDC instruction (2) in FIG. 87. Although these instructions do not directly branch, they do change the state of the data processing unit, so subsequent instructions are carried over in the pipeline and some processing needs to be overridden. There is. This is because changing the I-i control register may change the preconditions of the process executed as the preceding process.

These preconditions include conditions for ring protection, changes in the designation of the 110 area, and the like.

Processing when execution of this instruction causes a problem in pipeline processing will be described using a change in ring protection conditions as an example.

7. When an LDC instruction that changes w2 is executed, is the operand fetch such that the following instruction causes a ring protection a exception?
The accompanying command was seven.

When an LDC instruction is input on the pipeline shown in Figure 2, at the same time as the LDC instruction step code advances to the execution stage: Prefetching of the operand is performed by the step code of the next instruction input to the F' stage. will be started. At the start of prefetch, the ring protection designation field in the PSW is ring protection 1g! Since the prefetch is not executed, the prefetch is executed.

When the execution of the LDC instruction is completed, the ring protection designation field in the psw is in a state where the ring is protected, so the operand prefetch of the next instruction should originally be treated as an error. However, since it is not possible to determine whether an error has occurred at the time of operand prefetching, the error will not be detected and the inappropriate access will continue to be executed. So D stage (towards)
When an LDC instruction is decoded in V, inappropriate accesses included in the following instructions are performed by not processing instructions after 1 in the IF stage (B) and D stage (To). That will no longer be the case. Furthermore, a function is added to initialize the pipeline by branching to the next instruction after the completion of data transfer to the separate register as part of the processing of the LDC instruction. By doing this, the LDC command can be processed correctly.

FIG. 38 shows the operation of the LDC instruction (2) which specifies the first operand in core aA. After instruction decoding.

Address calculation of the first operand is performed in the A stage as described in Th(t, 4), and ? Prefetch operands on stage. In parallel with this, the destination address is calculated.

The fetched operand is transferred at the Hz stage to the l1ldll register designated by the destination address calculated at the A stage. The pipeline is initialized by executing a branch to the next instruction in the transfer tank.

At 151 m, in Figure 39, the first operand is lb.
The operation of the LDC instruction ■, which is ytelpm, is shown.

After the instruction is decoded, the immediate data that becomes the second operand is sent to the original stage as a literal. Subsequently, the destination address is calculated in the A stage, and the immediate value sent earlier is transferred to the control register indicated by the specified address. After the transfer, the pipeline is initialized by fully executing the branch to the next instruction.

Figure a1 shows the data processing device IF stage according to the present invention and D
A block diagram of the stage is shown.

In the figure... is the instruction queue, (2! is the instruction fetch program counter % (31 is the IIF stage control circuit, 141 is the instruction fetch program counter %)
is an instruction decoder, , 61 is a D stage separate circuit, (6
1 is an engineering F stage stop signal, (7) is a pipeline initialization signal by the E stage, (8) is a decode stop instruction detection signal, (9) is an instruction end signal, and 110+ is an access request signal.

From the instruction fetch stage (F stage C11) to the instruction queue Ill 51: via the instruction decode stage (
If an instruction that involves a branch or jump is sent to the instruction decoder 14+ in the D stage (toward), and as a result of decoding V it is found that the instruction is an instruction that causes a branch or jump in the E stage, the instruction decoder sends the instruction to the D stage. A decoding stop command detection signal (8) is sent to the control circuit +61, and it is confirmed by the command end signal (9) that the entire command has been completely taken in by the command decoder 14), and the D stage changes to the IP stage. Send an IP steady stop signal (61 signals) indicating that instruction fetch access *request tap is stopped.Furthermore, the D stage itself also outputs step codes t- for instructions that involve branches or jumps.
After sending it to the A stage, the operation is stopped. These instructions may be specified by the multi-stage indirect addressing mode mentioned in the jump address 1k (1°, 2), so the processing will not proceed until it is confirmed that the entire instruction has been completely captured in the instruction decoder +41. One stage of instruction prefetch cannot be stopped. Instruction prefetch V
IE instruction fetch program counter (to access the memory at address 21,
An access request signal (10) is output from the m circuit 131. As a result of decoding F, if it is found that an instruction including a branch or jump in the Z stage uses the multi-stage indirect addressing mode, the D stage 1llal path 1) sends the multi-stage indirect addressing mode in addition to the decoding stop instruction detection signal (8). After confirming that this is the final part of the addressing mode designation using the command end signal (9), the machine F stage stop signal (61) is output.

An example of a Jup instruction that uses a two-stage multi-stage indirect reference shade?
This is shown in FIG. 40, and will be specifically explained.礪4
In Figure 0, the jump destination address of Fi and TMP command I-i is specified by two-stage multi-stage indirect reference. The second stage multi-stage indirection has a displacement of 16t)it as an extension part. This instruction is fetched and the first 2 bytes are D
When decoded at the stage, the E stage branch instruction detection signal (81) is output, indicating that the instruction is to jump at the E stage. Specifying the addressing mode [
Since it is clear that this is a multi-stage indirect reference, the D stage is input from the next 2-byte f instruction key. Since the calculation is performed in the A stage, the decoding F result is sent from the iD stage to the A stage. Since the multi-stage indirect reference has not ended in these 2 bytes, the new [5 from the instruction queue]
Enter byte. This Gbyte is decoded F and the same processing as in the first stage is performed. As a reminder, it becomes clear that the multi-stage indirect reference is completed by the second-stage decoding, and that a displacement meeting of 16t)it occurs. The D stage inputs the next i'byte to input the displacement.
input from the instruction queue, check the input, and send the join end signal (
9) is output. Destination [1 stage branch instruction detection signal 18
) has been detected, the D stage outputs the instruction end signal (
9) outputs the F-stage stop signal (6)r.

After this, the F stage stops prefetching instructions, and the D stage also stops operating after sending the displacement to the A stage.

As a result, instructions following an instruction that involves a branch are not processed in the D stage, and the F stage and D stage are used until the pipeline mechanism is initialized by executing a branch or jump, that is, the pipeline is initialized by the Heron stage. The process is stopped until the signal +71 becomes valid, and useless access requests included after instructions involving branches and jumps are no longer issued.

FIG. 3 shows how a branch or jump instruction is fetched and executed in the data processing device of the present invention, including the operation of the external path.

In FIG. 3, instruction 3 is a jump instruction. When instruction 3 is decoded in the D stage, prefetching and decoding of subsequent instructions are not performed. When instruction 3 is executed in the E stage, instruction 7 is newly processed from the F stage.

Until instruction 3 is executed in the E stage (2), no accesses will be wasted due to the jump.

When the processing of instruction 7 is restarted, the address where instruction 7, which is the jump destination, is stored is sent to F-stage C3p when execution of instruction 3 ends, and at the same time, a signal is sent to restart the stopped F-stage and D-stage operations. send. A stage? Since the step code F is stopped without being input, the F stage starts fetching the instruction for the sent address, and the pipeline resumes normal operation from then on. ] As described above, according to the present invention, in a data processing device that performs instruction pipeline processing, instructions that always cause a branch or jump in the execution stage or the state of the processor WI4''f:
After an instruction is input, no wasted instruction fetch or decoding is performed. This makes it possible to effectively utilize external paths and perform efficient processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an instruction fetch stage and an instruction decode stage in a data processing device according to an embodiment of the present invention. FIG. 2 is a diagram showing an example of a pipeline processing mechanism in a data processing device of the present invention, and FIG. 8 is a conceptual diagram of instruction execution in a program including a jump instruction in the pipeline mechanism of the present invention. FIG. 5 is a diagram showing a description example of an instruction format in the data processing device of the present invention, FIG. 5 is a diagram showing a format of an operation instruction between memory registers, and FIG. 6 is a diagram showing a format of an operation instruction between registers. , FIG. 7 is a diagram showing the format of a literal-memory operation instruction, FIG. 8 is a diagram showing the format of a literal-memory operation instruction, and FIG. 9 is a diagram showing the l-operand soundproof monolayer format? , 410 is a diagram showing the format of an instruction in which the first operand is a 2-operand instruction and requires memory access, and Figure 11 is a diagram showing the instruction format in which the first operand is an 8-bit wholesale value in an 8-operand instruction.
Figure 2: Male-operand in 2-operand instruction - A diagram showing the 7th option of an instruction where the operand is only address calculation, Figure 13 is a diagram showing the format of short branch combination, Figure 14 is a diagram showing the register 11 contact mode, Figure 15 Figure 16 shows the register indirect mode, Figure 17 shows the register relative indirect mode, Figure 17 shows the immediate value mode, and Figure 18 shows the register relative indirect mode.
Figure 19 shows the absolute mode, Figure 19 shows the PC relative indirect mode, Figure 20 shows all the stack pop modes, and Figure 21 shows the stack button mode. Figure 22
The figure shows the register-based multi-stage indirect mode, Fig. 23 shows the PO pace multi-stage indirect mode #:, Fig. 24 shows the absolute-based multi-stage indirect mode v2, and Fig. 25 shows the expanded multi-stage indirect mode. Figure B6 is a diagram showing the bit pattern when the multi-stage indirect mode continues, and Figure 27 is a diagram showing the bit pattern 2 when the multi-stage indirect mode ends.
FIG. g8 is a block diagram of the data processing f#I device of the present invention,
FIG. 29 is a diagram showing the basic instruction format of the data processing device of the present invention, FIG. 80 is a diagram showing an example of a pipeline processing mechanism in a conventional data processing device, and FIG. 81 is a diagram showing an example of a pipeline processing mechanism in a conventional data processing device. FIG. 8g is a diagram showing the bit pattern of the jump instruction in the present invention, FIG. 88 is a 70-chart showing the operation of the jump instruction, and FIG. FIG. 35 is a flowchart showing the operation of the subroutine return instruction; FIG. 36 is a diagram showing the bit pattern of the subroutine return instruction; FIG. 36 is a flowchart showing the operation of the subroutine return instruction; FIG. Diagram showing bit pattern, No. 8
Figure 7 shows that the first operand in the present invention is an 8-bit immediate value! Figure 38 is a flowchart showing the operation of a control register load instruction that specifies the first operand in single-layer addressing mode; Figure 89 shows the bit pattern of the register load instruction 'lIa; Figure 89 shows the first operand is 81)
The flowchart shown in Operation 1 of the it immediate value control register load instruction, FIG.
1 is an engineering F stage control circuit, 141 is an instruction decoder,
51 is the D stage system subcircuit, (B) is the engineering? Stage stop signal, (7) is pipeline initialization signal by E stage, (81 is decode stop instruction detection signal, (9) is instruction end signal, Hotd7 access request signal, C11) is instruction fetch stage, C (3 is instruction decode stage,
g3 is the operand address calculation stage, trout is the operand fetch stage, G35 is the instruction execution stage, (to) is the R stage, @ is the OF status, @babus interface circuit, (6) is the D code, @2 is the A code, -
is the R code, 14 is the F code, F%■ is the E code, ■ is the 8 code F, 15+1 is the alloy fetch section, -121 is the instruction decode section, 抉 is the PC calculation section, the chest is the operand address calculation section, and the number is Microphone ClROM section, - instruction fetch stage in a processing device, hook is an instruction decoding stage in a conventional data processing device, connection is an operand address calculation stage in a conventional data processing device, 81;
: The operand fetch stage in a conventional data processing device, and the conventional data processing f! #The instruction execution stage in the device is a path interface circuit in a conventional data processing device.

Claims (2)

[Claims] (1) Equipped with an external bus control mechanism that fetches instructions and inputs/outputs data, and pipes instructions through multiple stages, including a first stage that decodes instructions and a second stage that executes instructions. line processing, and after the jump instruction is processed in the first stage, a stop process is performed to temporarily suspend instruction fetching and/or instruction decoding, and when the jump instruction is processed in the second stage, the jump instruction is processed in the second stage. A data processing device characterized in that the pipeline processing is restarted by jumping to an instruction at an address specified by the instruction. (2) Equipped with an external bus control mechanism that fetches instructions and inputs/outputs data, and pipes instructions through multiple stages, including a first stage that decodes instructions and a second stage that executes instructions. line processing, and after the processor status change instruction is processed in the first stage, a stop process is performed to temporarily suspend instruction fetching and/or instruction decoding, and the processor status change instruction is processed in the second stage. When this occurs, the data processing device restarts the pipeline processing from an instruction at an instruction address following the instruction address of the processor status change instruction.