JPS61286930A - Instruction prefetching control system - Google Patents

Abstract

PURPOSE:To suppress useless prefetch of instruction, to reduce a load and to improve performance in an instruction control device by suppressing a reading request from a main storage device at the detection of a branch instruction and releasing said suppression at the completion of the execution of the branch instruction. CONSTITUTION:When prefetch of instruction inputted to an instruction buffer 2 is decoded by a decoder 8 and the existence of a branch instruction is detected, an FF 10 is turned on and OR between an output signal of the decoder 8 and an output signal of the FF 10 is found out by an OR circuit 12. The output signal of the OR circuit 12 is functioned as a suppressing signal to a NAND circuit 13 to suppress an instruction prefetch request signal 7. At the completion of the execution of the branch instruction, the suppressing status is released.

Description

Detailed Description of the Invention [Summary] In an instruction control device having an instruction prefetch mechanism, a detection circuit (DEC) is provided to detect the presence of a branch instruction in the prefetched instruction, and the detection circuit (DEC) detects the presence of a branch instruction. When the presence of an instruction is detected, a main memory (MS) read request for prefetching the instruction is suppressed, and the suppressed state is released when the execution of the branch instruction is completed.

[Industrial application field]

The present invention relates to an instruction prefetch control method when a branch instruction exists among the prefetched instructions in an instruction control device having an instruction prefetch mechanism.

With the recent remarkable progress in semiconductor technology, processors (
Although there is a trend toward faster speeds of CPUs (CPUs), the reality is that main memory devices (MSs) are not faster than processors (CPUs).

On the other hand, instruction control devices are often equipped with a mechanism for pre-fetching instructions prior to their execution in order to improve the processing performance of the device.

In this case, if a two-branch instruction exists among the prefetched instructions, a part of the prefetched instructions may become invalid, which poses a problem that causes a reduction in the processing performance of the instruction processing device.

Particularly, as described above, when the machine cycle of the processor (CPU) is faster than the access time to the main memory (MS), the influence is large.

Under these circumstances, in an instruction control device having an instruction prefetch mechanism, a prefetch control method that prevents invalid instructions from being prefetched as much as possible has been required.

[Conventional technology]

FIG. 5 is a diagram showing an example of a conventional instruction prefetch control circuit, in which an IB
It is equipped with four instructions up to O-IR3.

Now, according to the instruction prefetch request signal 7, the main memory (
MS) 1 is accessed, 2 instructions are read at once, and any 2 of the instruction buffers (IBO to (B3) 2) is accessed.
When the instruction is stored in one instruction buffer (IBo, 1. or IR2, 3), the instruction valid flag of the instruction buffer is set at the same time.
The corresponding flag from 0 to 33 is set to 'on'.

The instruction buffer (
IBo, 1. or IR2, 3) 2 is on, the contents of the instruction buffer (IBo, 1. or IR2, 3) 2 selected by the selection signal 4 are passed through the next execution instruction selection circuit 5. Instruction register (IR
) 6, execution of the instruction is started, and at the same time, the corresponding flag among the instruction valid flags 30 to 33 is reset.

In this way, the instruction valid flag for two instructions, for example 30.3
1 becomes the "off" state, the corresponding NOR circuit 13 is energized, and the main memory (MS) is connected through the OR circuit 4.
1, the instruction prefetch request signal 7 for prefetching an instruction is turned on to prefetch the instruction, and the same operation is repeated thereafter. 1 In this way, the processing ability of the instruction control device is improved by instruction prefetch control.

[Problem that the invention seeks to solve]

In the above conventional method, when executing a branch instruction, the instruction buffer (IBo, 1. or IR2, 3') is cleared and a new instruction is prefetched, a prefetch request that occurs before the execution of the branch instruction , main memory (MS)
1 is in a read cycle, there is a problem in that prefetching of the branch destination instruction must wait until the read cycle is completed.

FIG. 6 is a time chart showing the instruction prefetching operation according to the conventional method, in which the instruction buffer (IBO)
When the execution of the instruction B is completed and the execution of the instruction B of the instruction batch (IBI) is started, the instruction valid flags 30 and 31 are turned off, so the NOR circuit 13 is activated and the instruction Preemption request signal ■7 becomes ``on'',
At the timing shown in the figure, the main memory (MS) read cycle (2) is entered.

As a result, the execution of the branch instruction C stored in the instruction buffer (IR2) is delayed, for example, by two machine cycles, and is executed at the timing (2).

In view of the above conventional drawbacks, the present invention eliminates the waiting time for execution of branch instructions by prefetching useless instructions by confirming the existence of a branch instruction with respect to the prefetched instructions, thereby improving the performance of the instruction control device. The purpose is to provide a method for improving the

[Means for solving problems]

FIG. 1 is a block diagram of the principle of instruction preemption control according to the present invention.

The prefetch instruction read into the instruction buffer (IBi) 2 is decoded by the decoder (DEC) 8 to detect a branch instruction and stored in the flip-flop (hereinafter referred to as FP) 10. The logical sum signal (OR circuit 1) of the output signal 9 of the FF 10 and the output signal of the FF 10
2 output signal) to suppress the instruction prefetch signal 7.

[Effect]

That is, according to the present invention, an instruction control device having an instruction prefetch mechanism is provided with a detection circuit (DIIC) that detects the presence of a branch instruction in the prefetched instruction, and the detection circuit (DIIC) detects the presence of a branch instruction in the prefetched instruction. When the presence is detected,
The main memory (MS) read request for prefetching the instruction is suppressed, and the suppressed state is released when the execution of the branch instruction is completed, thereby preventing unnecessary prefetching of instructions. This has the effect of reducing the load on the main memory (MS) and improving the performance of the instruction control device.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention, and FIG. 4 is a block diagram showing another embodiment of the present invention, and the same reference numerals as in FIG. 5 are the same. The branch preemption control mechanism (8 to 12) shown in FIG. 1 and described in FIG. 1 is a necessary functional block to implement the present invention.

First, the instruction buffer (IBo, 1. or IR2, 3)
One of the prefetched instructions read out in step 2 is selected from the next execution instruction selection circuit 5 by the next execution instruction selection signal 4,
At the timing when the instruction register (IR) 6 is set, when it is decoded by the decoder (DEC) 8 and a branch instruction is detected, the flip-flop (FF) 10 that stores instruction prefetch request prohibition is turned on. The output signal of the decoder (DEC) 8 and the F
An OR circuit 12 performs a logical sum with the output signal of F10, and the output signal functions as an inhibit signal for the NAND circuit 13, thereby inhibiting the instruction prefetch request signal 7.

FIG. 3 is a time chart showing the instruction prefetch inhibiting operation according to the present invention, in which the instruction prefetch request signal 7 is inhibited by the output signal of the OR circuit 12, and the execution of branch instruction C is It is understood that it can be executed following the completion of execution of B.

Since the reset of the FF 10 is performed by the execution signal 11 of the branch instruction C, after the branch instruction is executed, the prefetch request is allowed again.

In this embodiment, all instruction buffers (BIO to B
Although it is not possible to detect a branch instruction for an instruction within I3) 2, there is an advantage in that it can effectively prevent unnecessary prefetching of instructions with a small amount of hardware.

In contrast, in the embodiment shown in FIG. 4, branch instructions can be detected for all instruction buffers (BIO-BI3).

That is, a decoder (DEC) 8 is provided to detect a branch instruction for prefetched data (for two instructions) of instructions from the main memory (MS) 1, and if there is a branch instruction in the prefetched instruction. If exists, the aforementioned FF 10 is set through the OR circuit 12, which functions to block the NAND circuit 13 and suppress the next instruction prefetch request signal 7. It is also possible to prevent unnecessary instructions from being prefetched.

In this way, in the present invention, a decoder (DEC) 8 detects the presence of a branch instruction among prefetch instructions.
is provided, and when it is detected that a branch instruction exists among the prefetch instructions, the detection signal is stored in the FF 10,
The feature is that the next instruction prefetch request signal 7 is suppressed until the execution of the branch instruction is completed.

〔Effect of the invention〕

As described above in detail, the instruction prefetch control method of the present invention includes, in an instruction control device having an instruction prefetch mechanism, a detection circuit (DEC) that detects the presence of a branch instruction in the prefetched instruction; When the detection circuit (DEC) detects the existence of a branch instruction, it suppresses the main memory bag W (MS) read request for prefetching the instruction, and when the execution of the branch instruction is completed, the suppressed state is turned off. Since the command is released, unnecessary prefetching of instructions can be suppressed, the load on the main memory (MS) can be reduced, and the performance of the command control device can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of instruction preemption control according to the present invention. FIG. 2 is a block diagram showing an embodiment of the present invention. FIG. 3 is a time chart showing the instruction prefetch inhibiting operation according to the present invention. FIG. 4 is a block diagram showing another embodiment of the present invention. FIG. 5 is a diagram showing an example of a conventional instruction prefetch control circuit. FIG. 6 is a time chart showing the instruction prefetching operation according to the conventional method. It is. In the drawings, 1 is a main memory (MS). 2 is an instruction buffer (IBO to IB3). 30 to 33 are instruction valid flags, and 4 is a next execution instruction selection signal. 6 is an instruction register, and 7 is an instruction prefetch request signal. 8 is a decoder (DEC). 10 is a prefetch request prohibition flip-flop (FF); ■～■ are command execution or control signals. are shown respectively. C0 stinging sound (Niyoru q4 cut 0 hot goose showed 12L timer yard)

Claims (1)

[Claims] It has a plurality of instruction buffers (IBi) (2), and prior to execution of the instruction, the instruction is read from the main memory (MS) (1) and the instruction buffer (IBi) ( In an instruction control device having an instruction prefetch control mechanism stored in 2), a circuit (DEC) (8) for detecting the existence of a branch instruction in the prefetched instruction is provided, and the detection circuit (DEC) (8) When the existence of a branch instruction is detected, the read request signal (7) to the main memory (MS) (1) for instruction prefetching is suppressed until the branch instruction is executed, and An instruction prefetch control method, characterized in that, after execution of the instruction, control is performed to cancel the prohibition state (10) of a read request of a main memory (MS) for the instruction prefetch.