JP2572821B2 - Operation processing method by instruction re-execution - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to an arithmetic processing method in which a dedicated arithmetic unit for a floating-point arithmetic instruction is provided in an arithmetic processing unit of a general-purpose instruction processing device. In some cases, processing of delayed addition execution may be required,
Pre-processing is required for the detection, and post-processing may be required depending on the operation result. The purpose is to solve the problem that high-speed floating-point operation could not be achieved due to the inspection. When the operand data of the floating-point operation instruction to be executed is supplied to the operation control unit, the floating-point operation unit is immediately started, and the detection processing of the delayed addition execution processing is performed in parallel. The arithmetic control unit is configured to issue an instruction re-execution request interrupt to the instruction control unit when it is detected, or when the result of the arithmetic execution requires post-processing.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing method in an arithmetic control unit of a general-purpose instruction processing device, and more particularly to an arithmetic processing method in a case where a dedicated arithmetic unit for floating-point arithmetic is provided in the arithmetic control unit.

[Prior art] General-purpose instruction processors have the ability to execute a large number of instructions at high speed. Among them, four arithmetic operations are particularly required for high-speed operation. Power is important, and the ability to execute floating-point arithmetic instructions at high speed is required.

For this reason, a large-scale machine is provided with a dedicated floating-point arithmetic unit, and data processing is performed at high speed by an advanced pipeline processing method.

In some floating-point operation instructions, it is necessary to perform delayed addition execution depending on the contents of operand data. Further, when the floating-point arithmetic unit outputs an exceptional intermediate result in the operation, special post-operation processing may be required to obtain the final result.

In a conventional arithmetic processing unit, an arithmetic control unit includes a micro-program processing in which a micro-program controls a general-purpose arithmetic unit to execute an instruction, and a special-purpose arithmetic unit such as a floating-point arithmetic unit. Execution is performed at high speed by a special-purpose arithmetic unit, and micro programs are divided into cases such as starting the arithmetic unit, processing special operand data, and processing exceptional intermediate results output from the arithmetic unit. In general, a method is used in which the data is optimally used depending on the contents of the operand data.

In the conventional arithmetic processing method, if the instruction to be executed can determine whether it is necessary to perform special processing only by decoding the instruction, the instruction control unit decodes the instruction and starts the arithmetic control unit. By modifying a command code for the arithmetic control unit, it has been performed to instruct the arithmetic control unit that an instruction to be executed needs to perform a special process.

However, some floating-point operation instructions require special processing depending on the operand data. In this case, since the judgment by the instruction control unit is impossible, the arithmetic control unit is activated, and when the operand data of the instruction to be executed is supplied from the storage control unit or the instruction control unit,
The arithmetic control unit is configured to determine the necessity of the delayed addition execution process by analyzing the operand data. If the floating-point arithmetic unit outputs an exceptional intermediate process due to the execution of the operation and special post-processing may be required to obtain the final result, the operation is performed until the verification of the operation result is completed. The control unit is configured to stop the instruction execution pipeline of the instruction control unit without notifying the instruction control unit of the completion of the operation.

[Problems to be Solved by the Invention] The conventional arithmetic processing method described above has the following problems.

(1) Since a high-speed floating-point operation instruction is required, even if a dedicated floating-point operation unit is provided to increase the processing speed of the operation, if the delayed addition execution processing depends on operand data, the detection is performed. Is uniformly added to the instruction processing execution time, so that it becomes an overhead, and even if the operation unit itself is sped up, the execution time is not directly improved.

(2) It is not possible to notify the instruction control unit of the completion of the operation until the check as to whether the post-operation processing is necessary is completed based on the operation result. Particularly in the high-speed pipeline processing method, the operation end signal is used as a notice signal of the actual operation end, so if the operation end signal is delayed, the start of execution of the next instruction by the operation control unit is delayed by that amount. Min overhead.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide an arithmetic processing method by instruction re-execution that achieves high-speed floating-point arithmetic.

[Means for Solving the Problems] According to the present invention, the above-mentioned object is achieved by the means described in the claims. That is, the present invention
A general-purpose instruction processing device having an instruction control unit, a storage control unit, and an arithmetic control unit, wherein a general-purpose arithmetic unit and a dedicated arithmetic unit for floating-point arithmetic are provided in the arithmetic control unit; When the operand data of the floating-point operation instruction to be executed is supplied to the operation control unit, the preprocessing for detecting the delayed addition execution processing is not performed, and the floating-point operation unit is immediately executed. A first procedure for detecting whether or not the delayed addition execution processing is necessary in parallel with the execution of the operation of the floating-point arithmetic unit. A second procedure for always notifying the instruction control unit at a constant cycle of an arithmetic end signal for operating the arithmetic cycle of the decimal point arithmetic instruction at a constant processing speed; Required for additional execution processing The third step is to issue an instruction re-execution request interrupt to the instruction control unit when the post-processing is required according to the result of the operation performed by the floating-point arithmetic unit. If the instruction control unit receives an instruction re-execution request interrupt, it modifies the instruction code for the operation control unit to cancel the subsequent instruction and then re-execute the instruction that requested the instruction re-execution request interrupt. A fourth procedure for designating an instruction re-execution exclusive entry to the instruction control unit and notifying the instruction re-execution mode to the arithmetic control unit, using the above-described first to fourth procedures, and Is an arithmetic processing method by instruction re-execution for providing an instruction processing entry corresponding to a predetermined case that can occur and executing a floating-point instruction.

[Operation] In the present invention, a floating-point operation instruction is executed according to the following procedure.

(1) Operands of floating-point operation instructions to be executed
When the data is supplied, the floating point arithmetic unit is immediately started without performing the preprocessing for detecting the delay type additional execution processing. The detection of the delay type additional execution process is performed by, for example, a microprogram or the like in parallel with the execution of the operation of the floating point arithmetic unit.

(2) In order to move the operation cycle of the floating-point operation instruction including the delay type additional execution processing in the operation control unit at a constant maximum processing speed, an operation end signal is always notified to the instruction control unit in a constant cycle.

(3) For example, when the necessity of the delay type additional execution process is detected by micro program processing or the like, or when the execution result of the arithmetic operation of the floating point arithmetic unit requires post-processing, the arithmetic control unit sends the instruction control unit a To send an instruction re-execution request interrupt.

(4) When receiving the instruction re-execution request interrupt, the instruction control unit cancels the subsequent instruction and then re-executes the instruction requesting the instruction re-execution request interrupt. At this time, the instruction code for the arithmetic control unit is modified to designate a dedicated entry for instruction re-execution. Further, the instruction re-execution mode is notified to the arithmetic control unit. This signal is used inside the arithmetic and control unit to suppress detection of an instruction re-execution request interruption member.

The instruction is executed according to the above procedure, and the dedicated entry for instruction re-execution of the arithmetic control unit is capable of supporting delayed addition execution processing depending on operand data. To cope with the case where post-processing is required. In other words, the instruction re-execution dedicated entry is an instruction processing entry corresponding to all possible cases.

Embodiment FIG. 1 is a block diagram showing the configuration of a general-purpose processing apparatus according to an embodiment of the present invention, wherein 1 is an instruction control unit, 2 is a storage control unit, 3 is an arithmetic control unit, and 4 is an operation control unit. (Micro sequencer) 5 is status port, 6 is data port, 7
Denotes a general-purpose operation unit, and 8 denotes a floating-point operation unit.

 The contents of each signal line on the figure are as follows.

10 to 11: data bus for operand data from instruction control unit 1 (mainly a bus for transferring data obtained by reading the contents of general registers) 12: operation result data bus to instruction control unit 1 (mainly general registers 13: Operand data bus from the storage controller (mainly a bus for transferring main storage read data or cache read data) 14: Operation result storage data bus to the storage controller 2 15: Command code from command control unit 1, command code valid signal 16: Status information bus from command control unit 1 (mainly used for program interrupt mask, etc.) 17: Status information bus from operation control unit 3 (mainly program 18a, 18b, 19: input / output buses of the general-purpose arithmetic unit 7 20a, 20b, 21: input / output of the floating-point arithmetic unit 8 Power bus 22: General computing unit 7 of the result status signal 23: the operation result status signal 24a of a floating point unit 8, 24b, 24c, 24d: micro program various computing units,
Control signal for controlling status port and data port 25: Status information used for branch condition of micro sequencer The operation control unit 3 intervenes the instruction code of the instruction to be executed from the instruction control unit 1 through the signal line 15. The operand data is supplied from the register in the instruction control unit 1 via the data buses 101 and 11 or the memory operand is transmitted from the storage control unit 2 according to the format and contents of the instruction. If supplied via the data bus 13, execution of the operation is performed, the operation result is returned to the instruction control unit 1 or the storage control unit 2 via the data buses 12 and 14, and an operation end signal is transmitted via the status information bus 17. To the instruction control unit 1 to notify the end of the operation.

However, in the instruction execution pipeline of this embodiment, most of the basic instructions can be executed in 1τ which is the basic unit time, and the operation end signal is not used in the advance control of the pipeline.

Since the floating-point operation instruction of this embodiment has a variable cycle in which the number of executions τ is 2τ or more, it is necessary to control the pipeline in advance using an operation end signal.

When the preceding instruction or the instruction being executed is a variable cycle instruction, the instruction control unit 1 recognizes the end of the operation of the operation control unit 3 and inputs the next instruction processing to the operation control unit 3.

Further, when the preceding instruction or the instruction being executed has a variable cycle, the instruction control unit 1 cannot input the next instruction processing to the arithmetic control unit 3 until the operation control unit 3 notifies the completion of the operation. , The instruction execution pipeline is stopped. In the pipeline processing method of the present embodiment, a notice signal indicating the end of processing in the operation control unit 3 is used as an operation end signal in order to efficiently perform the pipeline processing. Therefore, the arithmetic control unit 3 sets the instruction control unit 1 to use the advance processing notice signal as an arithmetic end signal 1τ before the last cycle of the arithmetic processing.
Must be sent to

Further, the arithmetic control unit 3 executes a process of executing an instruction mainly by controlling a microprogram using the general-purpose arithmetic unit 7 and executes a high-speed instruction mainly by hardware control using the floating-point arithmetic unit 8. The processing is optimally used depending on the contents of instructions and operand data.

When performing the delayed addition execution processing, the instruction code 15 to the arithmetic control unit 3 is modified. In the entry of the corresponding micro sequencer 4, a micro program corresponding to a predetermined case that can occur with the command code 15 is registered.

In the case of the delayed addition execution processing, the microprogram controls the general-purpose operation unit 7, the floating-point operation unit 8, and the data port 6 with the signals 24a, 24b, 24c to execute the operation processing. The microprogram sets the status information of the operation result of each operation unit in the status port 5 by the signal 24d.

This microprogram performs a conditional branch using the status information (signal 25) from the status port 5, and corresponds to a predetermined case.

Hereinafter, the operation of the arithmetic processing system of the present invention will be described with reference to FIG.

FIG. 2 is a diagram showing a flow of pipeline processing by the arithmetic processing method of the present invention.
A, T, B, E, and W represent each processing stage of the instruction processing pipeline, and one instruction can be executed from the D stage to the W stage.

 The general operation of each stage is as follows.

D: Decode stage The execution instruction is loaded on the instruction buffer and becomes valid, and the execution instruction is decoded.

A: Operand address calculation stage T: Address conversion stage Accesses the address conversion buffer. If a hit occurs, the operand buffer is accessed next. If there is no hit, the subsequent instruction is stopped and the address translation is performed.

B: If the operand buffer access stage hits, the read data is supplied to the arithmetic control unit or the instruction control unit. If no hit occurs, the subsequent instruction is stopped and the main memory is accessed.

The instruction control unit 1 reads a general-purpose register or the like and supplies it to the operation control unit 3 as an operand.

E: Calculation execution stage of the calculation control unit 3 W: Stage for storing the rating result In this W stage, various interrupts are further attached.

FIG. 2A shows the normal case, that is, the operand data of the floating-point operation instruction is not special, the operation continues smoothly using the floating-point operation unit, and the post-processing is also performed on the operation result. This is an example of when it is not required. In the figure, the A instruction and the B instruction are executed by pipeline processing, operation end signals 30 and 31 are obtained before the execution of each instruction is completed, and the pipeline processing is continued.

FIG. 2 (b) shows a case of operation by instruction re-execution, that is, an example in which operand data of a floating-point operation instruction requires delayed addition execution processing, or an operation result requires post-processing. It is.

In the figure, an instruction A is executed from an operation stage D to an operation stage E. At a stage W, a detection processing result and an operation result of the operand data are checked, and it is determined that the instruction A needs to be re-executed. This is an example of the case where the operation is performed.

In this case, the arithmetic control unit 3 immediately sends the instruction re-execution request interrupt signal 33 to the instruction control unit 1.

When the instruction control unit 1 receives the instruction re-execution request interrupt signal 33, the B instruction and all subsequent instructions are canceled,
The A instruction that has requested the instruction re-execution request interrupt is re-executed.

In other words, the operation completion signal 32 of the already transmitted A instruction becomes invalid, and after the stage of the instruction re-execution pre-processing 34, the cycle of the instruction re-execution processing of the A instruction (stages indicated by D 'to W' in the drawing) is started. Then, before the execution of the A instruction is completed, the operation end signal 35 is transmitted, and the processing of instruction re-execution is completed.

The functions of the instruction control unit 1, the storage control unit 2, and the operation control unit 3 in the instruction processing pipeline according to the embodiment of the present invention in FIG. 2 are as follows.

The instruction control unit 1 reads an instruction and decodes an execution instruction in a D stage.

In the case of a memory access operand, an operand address is calculated and an operand access to the control storage unit 2 is issued in the A stage. The storage controller 2 accesses the address exchange buffer at the T stage.

If there is no data in the address exchange buffer,
Perform address translation processing. If there is no data in the operand buffer, the memory operand data is transferred from the main storage device (not shown) to the operand buffer. Both processes remain at the B stage until this process ends.

In the case of a command to start the arithmetic unit, a command code and a command code valid signal (signal 15) are sent from the command control unit 1 to the T stage.
Is issued.

The operation control unit 3 receives the register read data (signals 10 to 11) or the memory operand data from the storage control unit 2 at the data port 6 in the B stage.

The arithmetic control unit 3 receives the instruction code from the instruction control unit 1 and B
The arithmetic processing is executed in the E stage according to the operand data received in the stage. If a plurality of cycles are required for the arithmetic processing, the operation stays at the E stage until the arithmetic processing ends.
In this case, the operation control unit 3 notifies the instruction control unit 1 of the operation end signal from the status port 5 via the status information bus 17.

The operation result of the operation control unit 3 is stored in the data port 6. If the instruction is a register storage instruction, the operation result of the data port 6 is stored in the register of the instruction control unit 1 using the operation result data bus 12 to the instruction control unit 1 at the W stage. If the instruction is a memory storage instruction, the operation result of the data port 6 is written to the operand buffer of the storage control unit 2 using the operation result storage data bus 14 for the storage control unit 2 at the W stage.

[Effects of the Invention] The present invention rarely requires delayed addition execution processing depending on operand data and post-processing depending on the operation execution result of a floating-point arithmetic unit. Focusing on the fact that there is no particular problem in the execution performance of the operation, and on the other hand, that the normal operand data of the floating-point operation needs to be executed at high speed,
Data achieves improved execution performance of operations through advanced pipeline processing, and when processing of delayed addition execution of instructions is required, the instruction re-execution function is mainly used to control micro-programs, etc. Since the mechanism of the instruction control unit for re-execution can almost utilize the mechanism (interrupt handler) used for normal interrupt processing, there is an effect that the hardware for the delayed additional execution processing can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a general-purpose processing device according to an embodiment of the present invention, and FIG. 2 is a diagram showing a flow of pipeline processing by the arithmetic processing system of the present invention. 1 ... Command control unit, 2 ... Storage control unit, 3 ... Operation control unit, 4 ... Operation control unit (micro sequencer), 5 ...
Status port, 6 data port, 7 general-purpose operation unit, 8 floating-point operation unit, 10, 11 data bus for operand data from instruction control unit, 12 operation result to instruction control unit Data bus 13, data bus for operand data from storage control unit 14, data storage bus for operation results to storage control unit 15, command code and command code valid signal from instruction control unit 16, Status information bus from the instruction control unit, 17 ... Status information bus from the operation control unit, 18a, 18b, 19 ... I / O bus of general-purpose arithmetic unit
20a, 20b, 21… I / O bus for floating point arithmetic unit, 22…
Operation result status signal of general-purpose operation unit, 23 ... Result operation status signal of floating-point operation unit, 24a, 24b, 24c, 24d
…… Control signals for the microprogram to control various arithmetic units, status ports, and data ports. 25 ……
Status information used for branch conditions of the micro sequencer, 30, 32, 35... A instruction end signal, 31... B instruction end signal, 33... A instruction re-execution request interrupt signal by A instruction, 34. Instruction re-execution pre-processing

Claims (1)

(57) [Claims] 1. A general-purpose instruction processing device having an instruction control unit, a storage control unit, and an operation control unit, wherein the operation control unit includes a general-purpose operation unit and a dedicated operation unit for floating-point arithmetic. When the floating-point operation instruction is executed, when the operand data of the floating-point operation instruction to be executed is supplied to the operation control unit, the pre-processing for detecting the delay type additional execution processing is not performed, but immediately. Activate the floating point arithmetic unit, and in parallel with the execution of the operation of the floating point arithmetic unit,
1st processing for detecting whether or not the delay type additional execution processing is necessary
The operation control unit always notifies the instruction control unit of an operation end signal for operating the operation cycle of the floating-point operation instruction including the delay type additional execution process at a constant processing speed to the instruction control unit at a constant cycle. In the procedure, when the necessity of the delay type additional execution processing is detected in the detection processing of the delay type additional execution processing, and when the post-processing becomes necessary due to the calculation execution result of the floating point arithmetic unit,
A third step of issuing an instruction re-execution interrupt to the instruction control unit; if the instruction control unit receives the instruction re-execution request interrupt, cancel the subsequent instruction and then execute the instruction re-execution request. A fourth procedure for modifying the instruction code for the arithmetic control unit to specify an instruction re-execution dedicated entry in order to re-execute the instruction requested by the interrupt, and for notifying the instruction control unit of the instruction re-execution mode; An instruction re-execution characterized by using the first to fourth procedures and providing an instruction processing entry corresponding to a predetermined case which can occur in a dedicated entry for instruction execution of the arithmetic control unit to execute a floating-point operation instruction. Arithmetic processing method by execution.