JPS57193843A - Pipeline computer - Google Patents

Pipeline computer

Info

Publication number
JPS57193843A
JPS57193843A JP7771881A JP7771881A JPS57193843A JP S57193843 A JPS57193843 A JP S57193843A JP 7771881 A JP7771881 A JP 7771881A JP 7771881 A JP7771881 A JP 7771881A JP S57193843 A JPS57193843 A JP S57193843A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
th
instruction
pre
fetch
predecoders
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7771881A
Inventor
Jiro Suzaku
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802Instruction prefetching

Abstract

PURPOSE:To prevent useless prefetch operation, by predecoding if there is an instruction which makes the instruction prefetch ineffective in either one of a plurality of prefetched instructions. CONSTITUTION:Predecoders 20a-20d input the 63rd the 65-th, the 47-th the 40-th, the 31st-the 24-th and the 15-th-the 8-th out of 64 bits of pre-fetch bus (5) and detect if this bit patterns in 8 bits are coincident with the specified bit pattern (a bit pattern of an instruction making the pre-fetch of the OP and succeeding instruction ineffective). When a signal of logic (1) is outputted from either one of the predecoders 20a-20d, an F//F22 is set via an OR gate and the pre-fetch operation is inhibited while the F//F22 is set.
JP7771881A 1981-05-22 1981-05-22 Pipeline computer Pending JPS57193843A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7771881A JPS57193843A (en) 1981-05-22 1981-05-22 Pipeline computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7771881A JPS57193843A (en) 1981-05-22 1981-05-22 Pipeline computer

Publications (1)

Publication Number Publication Date
JPS57193843A true true JPS57193843A (en) 1982-11-29

Family

ID=13641662

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7771881A Pending JPS57193843A (en) 1981-05-22 1981-05-22 Pipeline computer

Country Status (1)

Country Link
JP (1) JPS57193843A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6077241A (en) * 1983-10-05 1985-05-01 Hitachi Ltd Information processor
EP0180725A2 (en) * 1984-10-31 1986-05-14 International Business Machines Corporation Instruction prefetch operation for branch instructions
JPS61286930A (en) * 1985-06-13 1986-12-17 Fujitsu Ltd Instruction prefetching control system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6077241A (en) * 1983-10-05 1985-05-01 Hitachi Ltd Information processor
EP0180725A2 (en) * 1984-10-31 1986-05-14 International Business Machines Corporation Instruction prefetch operation for branch instructions
JPS61286930A (en) * 1985-06-13 1986-12-17 Fujitsu Ltd Instruction prefetching control system

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