JPS63148329A - Instruction prefetch control system - Google Patents

Abstract

PURPOSE:To improve the use efficiency of a bus to increase the processing speed of a system by stopping to prefetch instructions from a queue register when it is detected that a specific instruction is stored in the queue register. CONSTITUTION:Instructions are fetched from an instruction storage part 1 to a queue register 3 through a bus 8 and instructions are transferred to an instruction executing part 4 in the order of fetching. In this stream, a decoder 10 always decodes a decode information signal 12 to monitor instructions fetched in the queue register 3. If a branch instruction is fetched, the decoder 10 reports it to a bus control part 5A by a detection signal 13. The bus control part 5A stops the following fetch operation by a control circuit 11. When the branch instruction is executed by the instruction executing part 4 thereafter, the bus control part 5A starts fetching on the basis of the branch address.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an instruction preemption control system in parallel operation of a control device.

[Conventional technology]

A conventional instruction prefetching method of this type will be explained with reference to FIG. 1 is an instruction storage circuit that stores instructions; 2 is a data storage circuit that stores data; 3 is a queue register that stores fetched instructions; 4 is an instruction execution unit that decodes and executes the instructions taken out from the queue register 3; 5 is a bus control unit that controls bus use requests from the instruction execution unit 4 and the queue register 3; 6 is a bus use request signal from the queue register 3; 7 is a bus use request signal from the instruction execution unit 4; 8
94 is a bus for transmitting addresses for controlling the memory circuits 1 and 2 and data write/read signals;
This is a signal to send to.

The bus control unit 5 first takes in an instruction to the queue register 3 via the bus 8. When an instruction is fetched into the queue register 3, the instruction execution section 4 takes in the signal 9, decodes the instruction, and if data exchange with the data storage circuit 2 is necessary, sends a signal to the bus control section 5 to send the instruction to the bus controller 5. A use request signal 7 is sent. In the initial state, the queue register 3 is in a state where there are no valid instructions, and each time an instruction is fetched, it is filled with valid instructions. A fetch is requested, but once the queue register 3 is filled with valid instructions, no further fetch requests are made.

On the other hand, the instruction execution unit 4 receives instructions in the order in which they are fetched, and the queue register 3 becomes empty each time the instructions are received.

The bus control unit 5 receives a bus use request signal 7 from the instruction execution unit 4 in response to the bus use request signal 6 from the queue register 3.
However, if there is no bus use request signal 7 from the instruction execution unit 4, the bus use request signal 6 from the queue register 3 is accepted. In this way, the bus use request signal 7 from the instruction execution unit 4 is given priority, but once a bus use request from the queue register 3 is received and that bus cycle has started, the bus use request signal 7 from the instruction execution unit 4 is given priority. In this case, a bus use request from the instruction execution unit 4 is not accepted.

FIG. 4 shows the timing in the conventional example. First, at timing T1, the first bus use request EXRQ is sent from the instruction execution unit.
There is a bus cycle EXI of the instruction execution unit between T1 and T3 based on the request. There is a bus use request PFRQ from the queue register at timing T2.
The instruction fetch cycle PF is executed from 3 to T5. There was a second bus use request EXRQ2 from the instruction execution unit at timing T4, but since the instruction fetch cycle was being executed, the second bus use request from the instruction execution unit was made to wait until T5, and from T5 to T7. Bus cycle EX2 is executed.

If the instruction fetched by bus cycle PF for instruction fetch is a useless instruction, bus cycle EX2 is meaningless and has to wait until T5.

[Problem that the invention seeks to solve]

In the conventional instruction prefetch control method described above, even if the prefetched instruction is a branch instruction, instructions are continued to be prefetched as long as there is space in the queue register, resulting in unnecessary bus accesses and The disadvantage is that it slows down the processing speed of the entire system.

[Means for solving problems]

The instruction prefetch control method of the present invention is an instruction prefetch control method having a storage means for storing instructions, a queue register for storing the prefetched instructions, and an instruction reading means for prefetching the instructions and storing them in the queue register. means for detecting that the instruction stored in the queue register is a specific instruction; and means for stopping prefetching of instructions from the queue register when the detection means detects the specific instruction. It is characterized by having.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

Components that are the same as those in the conventional structure shown in FIG. 1 are given the same numbers as in FIG. 3, which shows the conventional example. 10 is a decoder for detecting that the fetched instruction is a branch instruction;
Reference numeral 11 denotes a control circuit that adds a function to stop fetch to the conventional bus control unit function to form the control unit 5A. Reference numeral 12 indicates that a branch instruction is included in the valid instruction group stored in the queue register 3. The decoder information signal 13 necessary for the determination is a detection signal that notifies the bus control unit 5A that a branch instruction has been detected by the decoder 10. In a series of steps in which instructions are fetched from the instruction storage unit 1 to the queue register 3 via the bus 8 and transferred to the instruction execution unit 4 in order from the instruction fetched first, the decoder 10 receives the decode information signal 12. By constantly decoding, the instructions fetched into the queue register 3 are monitored, and if a branch instruction is fetched, the decoder 10 notifies the bus control unit 5A with a detection signal 13. The bus control unit 5A uses the control circuit 11 to stop subsequent fetch operations.

After that, when the branch instruction is executed by the instruction execution unit 4,
The bus control unit 5A starts fetching based on the branched address.

The relationship between the bus use request signal and the bus cycle according to this embodiment will be explained with reference to the timing diagram of FIG.

According to the timing diagram of this embodiment shown in FIG. 2, since the bus use request signal PFRQ from the queue register is stopped, the second bus use request EXR from the instruction execution unit
Bus cycle EX2 for Q2 starts from T4,
Compared to the conventional example, bus usage efficiency is clearly improved.

Although this embodiment has been described using a branch instruction as the specific instruction shown in the claims, any instruction to stop subsequent fetches will have the same effect as this embodiment.

〔Effect of the invention〕

As explained above, in the present invention, when the instruction fetched into the queue register is meaningless to fetch at consecutive addresses after the instruction, such as a branch instruction, the subsequent fetches are stopped. This has the effect of increasing usage efficiency and improving system processing speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a block diagram of a conventional example, and FIG. 4 is a timing diagram showing the operation of FIG. 3. 1... Command storage circuit, 2... Data storage circuit, 3.
... Queue register, 4... Instruction execution unit, 5... Bus control unit, 6, 7... Bus use request signal, 8... Bus, 9... Signal for instruction transfer, 10 ... decoder, 11 ... control circuit, 12 ... -decode information signal, 13 ... detection signal. Agent Patent Attorney Uchihara Oto to Bo, Ro1ji〈−

Claims (1)

[Claims] In an instruction prefetch control system having a storage means for storing an instruction, a queue register for storing a prefetched instruction, and an instruction reading means for prefetching an instruction and storing the prefetched instruction in the queue register, An instruction prefetch control comprising: means for detecting that the received instruction is a specific instruction; and means for stopping prefetching of instructions from the queue register when the detecting means detects the specific instruction. method.