JPS61133439A - Instruction advance fetch control system - Google Patents

Abstract

PURPOSE:To decrease the data access wait time by providing a pre-decoder to an internal instruction buffer and giving an intermission request of fetch when a decoded instruction is a branch instruction so as to minimize the instruction fetch which would be useless by the execution of the branch instruction. CONSTITUTION:The pre-decoder 220 is provided to the pre-stage of the internal instruction buffer 202, and when the pre-decoder 220 detects that the fetched instruction if a branch instruction and all instruction bytes constituting the branch instruction are stored in the internal instruction buffer 202, a fetch intermission signal line 221 is brought into a low level to request the intermission of fetch. That is, the branch instruction is detected much earlier by the pre-decoder to the pre-stage of the internal instruction buffer 202, and when it is confirmed that all the instruction bytes constituting the branch instruction are stored to the internal instruction buffer 202, the intermission of the fetch is requested immediately to a bus control section 213 to minimize ineffective fetch.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an electronic computer, and particularly to an instruction preemption control system.

(Prior Art) One of the techniques for speeding up computers is an instruction preemption control system. One of the characteristics of the Neumann type combiner is that the next instruction to be executed has a very high probability of being the instruction following the currently executing instruction. The instruction prefetch control method utilizes this feature to sequentially fetch instructions during free time on the external bus and store them in the computer's internal instruction buffer in advance, thereby reducing the time required to fetch instructions. The purpose is

FIG. 4 is a block diagram of a CPU having a conventional instruction prefetch mechanism.

The CPU 2 exchanges data with the external bus 1. If the fetch request signal line 119 is at the no-y level, the bus control unit 113, which receives the fetch request signal line 119 as an input, issues a request to the external memory for instructions to be sent. When a fetch request is issued, the bus control unit 113 outputs the address of the instruction to be fetched onto the address/data bus 115, and as a result, the instruction held at the address in the external memory is transferred to the address/data bus 115. The signal is input to the bus control unit 113 through the bus control unit 113. Further, an internal instruction buffer 77102 stored in the internal instruction buffer 102 through the internal data bus 101 is an FIFO (First In F
irst Out ) structure, and the fetched instructions enter the decoder 106 through the instruction bus 105 in the order they are fetched. Queue write counter #≠104 indicates the position where the instruction fetched from the external memory is written to the internal instruction buffer 102, and the key read counter 103 indicates the position where the instruction stored in the internal instruction buffer 102 is written to the decoder 106.
It shows the position to read to.

That is, the queue write counter 104 and the queue
The difference between the read counters 103 becomes the total number of bytes of instructions currently stored in the internal instruction buffer 102. The output of decoder 106 informs the start address of microprogram 108 via microinstruction address bus 107. The control signal group 109 is output to the execution unit 110 by the execution by the micro programger, and the execution unit)
At 110, the bus control unit 11 according to the control signal group 109
3, data read/write operations are performed with the external memory. The 7th instruction is stored in the internal instruction buffer 1 during the free time of the external bus 1 when there is no data read/write.
However, if a data read/write request is generated from the execution unit 110 while the external bus 1 is fetching an instruction, the read/write request is The command currently being executed.

You will have to wait until the end of the game.

A fetch request is issued when the queue control unit 116, which receives the queue read counter 103 and the queue write counter 104 as input, determines that there is an empty buffer in the internal instruction buffer 102.

The fetch request signal line 117 becomes the I level. However, when there is no fetch request, the fetch request signal line 117 is assumed to be at a low level. here,
Fetching instructions is valid under the assumption that most of the instructions are executed sequentially, but
If there is a branch instruction such as a call or return instruction that disturbs the flow of the program, all instructions after the branch instruction stored in the internal instruction buffer 102 must be erased, and a new branch destination instruction must be re-fetched. Must be.

As a result, the erased instruction fetches become invalid. Here, there is no problem if the invalid instruction 7 fetch is performed during a completely free time on the external bus 1 with no memory access such as data read/write, but if the invalid instruction 7 is fetched while the memory is being fetched, When an access request occurs, the memory access request is forced to wait until the invalid instruction fetch cycle is completed, and during this time the CPU 2 wastes time due to the invalid fetch. As a result, the overall execution time of the computer is slowed down by wasted time. Therefore, as a method of instruction prefetch control, in order to reduce instruction fetches that become wasteful traps due to one branch instruction, all instruction bytes constituting a branch instruction are transferred to the decoder 1.
The method used was to interrupt subsequent instruction fetches after decoding with 06.

The instruction prefetch control method described above is based on the IEE Spec-tru
m), March 1979 issue, pages 28-34.

The above method has the disadvantage that all bytes constituting the branch instruction are completely decoded and an invalid instruction is fetched before an instruction fetch interrupt request is issued, slowing down the execution time of the conbeater.

The purpose of the present invention is to detect branch instructions earlier.
An object of the present invention is to provide an instruction prefetch control method for realizing high-speed converter operation by interrupting the fetch operation at an earlier stage and minimizing invalid fetches.

(Means for Solving the Problems) The instruction prefetch control method of the present invention includes a storage means for storing a prefetched instruction, and a storage means for storing the prefetched instruction in the instruction prefetching method for an information processing device. a detection means for detecting the instruction word length of the prefetched instruction before the prefetched instruction is stored in the storage means; a decoding means for detecting that the prefetched instruction is at least a branch instruction before the prefetched instruction is stored in the storage means; and control means for requesting suspension of instruction prefetching as soon as all bytes constituting the branch instruction are stored in the storage means, according to control information from the decoding means.

(Example) Next, embodiments of the present invention will be described using the drawings.

FIG. 1 is a schematic diagram of an embodiment of the present invention.

This embodiment includes an internal instruction buffer 202 as a storage means for storing prefetched instructions, and a detection means for detecting the instruction word length of the prefetched instruction before the prefetched instruction is stored in the internal instruction buffer 202. A decoder built into the Buri decoder 201 as a decoding means for detecting that the prefetched instruction is at least a branch instruction before the prefetched instruction is stored in the internal instruction buffer 202; 2 as a control means that requests interruption of instruction prefetching as soon as all bytes constituting the branch instruction are stored in the internal instruction buffer 202 according to control information from the branch decoder 201;
It is configured to include a driver AND circuit 218.

Next, the operation of this embodiment will be explained.

The CPU 4 exchanges data with the external data bus 3, and if the fetch request signal 219 is at a high level, the bus control unit 213 issues an instruction 7 fetch request to the external memory. When a fetch request is issued, the bus control unit 213
outputs the address of the instruction to be fetched from the external bus 3 through the address/data bus 215, and outputs the address of the instruction to be fetched in the external memory from the external bus 3 via the address/data bus 215 again. 215 to the bus control unit 213. Furthermore, instructions input to the bus control unit 213 are stored in the internal instruction buffer 202 via the internal data bus 201. The internal instruction buffer 202 has a FIFO structure, and the fetched instructions are passed through the instruction bus 205 to the C decoder 206! 'C enters. Ki, - Light Color/
Reference numeral 204 indicates the location where nine instructions should be fetched from the external memory and written to the internal instruction bar, file 202, and the key
- Read counter 203 indicates the position at which instructions stored in internal instruction buffer 202 are read to decoder 206. That is, the difference between the queue write counter 204 and the queue read counter 203 is the total number of bytes of instructions stored in the internal instruction buffer 202.

Further, the output of the decoder 206 informs the start address of the microprogram 208 through the microinstruction address bus 207, and outputs a group of control signals 209 to the execution unit 210 upon execution of the microprogram. In accordance with the control signal group 209, the execution unit 210 performs data read/write operations to/from the external memory via the bus control section 213.

Fetching of instructions is performed in accordance with a seven-way request signal 217 from the queue control unit 216 during idle time on the external bus 3 when there is no data read/write cycle. The fetch request is sent to the queue control unit 216 which receives the queue write counter 204 and queue read counter 203 as inputs.
This is issued when it is determined that there is an empty buffer in the internal instruction buffer 202, and the command 7 from the queue control unit 216
The etch request signal 217 goes high and generates a 7 etch request from the internal instruction buffer 202.

However, if there is no 7-etch request, 7-etch request compensation number 21
7 is assumed to be a low level. As mentioned in the conventional example, instruction fetch is effective on the premise that most instructions are executed sequentially, but it is effective when there are branch instructions that disturb the program flow, such as jump, call, or return instructions. In some cases, internal instruction buffer 2
All instructions after the branch instruction stored in 02 must be deleted, and a new branch destination instruction must be re-fetched. Therefore, in this embodiment, the internal instruction buffer 202
When the 71J decoder 220 detects that the fetched instruction is a branch instruction and that all instruction bytes constituting the branch instruction have been stored in the internal instruction buffer 202, the 71J decoder 220 The interrupt signal line 221 is set to low level to request suspension of fetch. However, it is assumed that the normal fetch interrupt signal line 221 is at a high level. If the fetch interrupt signal line 221 is at low level, the output signal line 2 of the two-man AND circuit 218
19 becomes low level and notifies the bus control unit 213 of the suspension of instruction fetch. On the other hand, the fetch interrupt signal line 22
1 is at a high level, and there is an empty buffer in the internal command bar 77202, and the fetch request signal line 217 from the queue control unit 216 is at a high level (fetch request), the output line 219 of the two-man AND circuit 218 becomes the NO-I level and requests the bus control unit 213 to perform 7 etchings.

The present invention has the configuration described above, and by providing the predecoder 220 in front of the internal instruction buffer 202, a branch instruction can be detected earlier, and the internal instruction buffer 202 can be detected more quickly.
As soon as it is confirmed that all the instruction bytes constituting the branch instruction are stored in 02, the bus controller 213 is requested to interrupt the 7-etch, thereby providing a means for minimizing invalid fetches.

FIG. 2 is a detailed circuit diagram of the Buri decoder shown in FIG. 1.

The decoder 305 detects the length of the instruction word currently being fetched from the data input from the signal line [303, and
It is output to the counter 309 through the counter 309.

The decoder 306 detects whether the currently fetched instruction is a branch instruction from the data input through the signal line 304, and if it is a branch instruction, sets the control signal line 308i to a high level. The counter 309 inputs the instruction word length of the instruction currently being fetched from the signal line, and when the control signal 223 from the bus control unit 213 becomes high level, the counter 309 decrement/decrement once.
performs an operation to decrement the held contents by -1, and at the same time outputs the decremented contents to the latch circuit 310. Here, when the value of the counter 309 reaches 10", the control signal 311 is set to high level, and the latch circuit 31
0 sets the control signal 312 to a high level when its value becomes %%o #K. Furthermore, in the initial state (at the time of reset), the color/receiver 309 and child circuit 310 have a value of "O#".The control signal line 222 from the bus control unit 213 is connected to This is a control signal that becomes high level when is a fetch cycle, and the control signal line 223 is one cycle lower than the control signal line 222
This is a control signal that becomes high level with a delay corresponding to the amount of time. The two-man AND circuit 313 connects the control signal line 222 and the control signal! 1
312 as an input, the control signal line 222 is at high level, that is, the fetch cycle, and the control signal line 3
12 is at a high level, that is, when the value of the child circuit 310 is ゝゝo〃, the control signal line 314 is set to a high level,
Both gate 1301 and gate 302 are turned on.

game) 301 and 302 are on internal data bus 2.
The values on 01 are output to data bus 303 and data bus 304, respectively. The two-person AND circuit 315 receives the control signal line 311 and the control signal line 308 as input, and the control signal line 311 is at a high level, that is, the value of the counter 309 is "O", and the control signal line 308 is at a high level, that is, the current When the instruction being fetched is a branch instruction,
Control signal line 316 is set to high level. U, child circuit 31
7 sets the control signal line 221 to low level when the control signal line 316 becomes high level, and outputs a low level until the control signal line 318 becomes low level. Control signal line 318
The branch destination address is determined and becomes low level by the 7th etching restart request. When the control signal line 318 becomes low level, the latch circuit 317 makes the control signal line 221 high level, and the control signal line 221 outputs a high level until the control signal line 316 becomes high level again.

Next, the operation of the Buri decoder 220 shown in FIG. 2 will be explained using the timing chart shown in FIG. Here, it is assumed that the first instruction to be fetched after reset is a 3-byte instruction A, which is not a branch instruction, and the next instruction to be fetched is a 3-byte instruction B.

First, immediately after reset, the counter 309 and the latch circuit 31
0 are both ``0'', and the latch circuit 310 is ``O''.
", so the control signal line 312 is at a high level.

Next, when the 7th etching cycle of the first byte of the first 3-byte command occurs, the control signal line 222 becomes high level, and while the control signal line 222 is at the no-low level, the output of the two-man AND circuit 313 The signal line 314 becomes high level.

When the control signal line 314 is at a high level, both the gates 301 and 302 are turned on, and the internal data bus 20
The first byte on data bus 304 enters decoders 305 and 306 through data bus 303 and data bus 304.

The decoder 305 starts with the instruction A from the input first byte.
The instruction word length (=3) is decoded and the instruction word length (=3) is output to the counter 309 through the signal line 307. On the other hand, the decoder 306 starts with the instruction A from the input first byte.
It is determined whether or not it is a branch instruction. In this case, since it is not a branch instruction, the control signal line 308 outputs a low level. The counter 309 receives input through the signal line 307 and inputs nine instruction word lengths (
=3) and control signal line 2 from the bus control unit 213
When 23 becomes high level, the held value is decremented and the decremented value (=2) is output to the latch circuit 310. At this time, since the value of the latch circuit 310 becomes 12'', the control signal line 312 becomes low level, and even if the control signal line 222 becomes high level thereafter, the output signal line 314 of the two-man AND circuit 313 remains at low level. Since the gates 301 and 302 are off, the data on the internal data bus 201 is transferred to the data bus 30.
3 and 304 are not input. The counter 309 is decremented and holds 900 million (=2), but since the control signal line 223 becomes high level every fetch cycle, the held value is decremented by 1 and each time the control signal line 223 becomes high level. The latch circuit 310 outputs the incremented value.

As shown in FIG. 3, when the control signal 223 reaches the 1 level in the 7th etching cycle of the 3rd byte of the instruction A, the counter 309 decrements the value (=1) held by the counter 309 and the decremented value ( =O) is output to the latch circuit 310. Here, the content of the latch circuit 310 becomes 10'' again, so the control signal line 312 becomes a no-repel, and when the control signal line 222 becomes high level at the 7th etch cycle of the first byte of the next instruction B, the The output signal line 314 of the driver AND circuit 313 becomes /.level.

Gates 301 and 302 are turned on, and the first byte of instruction B on internal data bus 201 is read by decoder 305.
and 306. The decoder 305 decodes the instruction word length (=2) of instruction B from the input first byte, and sends the instruction word length (=2) to the counter 309 through the signal line 307.
=2) is output. On the other hand, the decoder 306 determines whether instruction B is a branch instruction from the input first byte,
In this case, if it is a branch instruction, the control signal line 30
8 outputs a high level. The counter 309 holds the instruction word length (=2) of the instruction B, and when the control signal line 223 becomes high level, it decrements the held value and transfers the decremented value (=1) to the latch circuit 310.
Output to.

Next, when the control signal 223 becomes high level in the fetch cycle of the second byte of instruction B, the counter 309 decrements the held value (=1) and transfers the decremented value (20) to the latch circuit. Output to 310. Here, since the value of the latch 310 is 10'', the control signal line 311 becomes a no-repel. On the other hand, the decoder 30
Since the control signal line 308 of No. 6 is at a high level,
The output signal line 316 of the two-man AND circuit 315 also becomes a /1 level. When the control signal line 316 becomes high level, the latch circuit 317 sets the control signal line 221 to low level. The control signal line 221 outputs a low level until the control signal line 318 becomes low level. Since the control signal line 221 is at low level, even if the fetch request signal line 217 becomes high level and a fetch request occurs, the control signal line 221 is at low level, so the two-man AND circuit 2
The output signal line 219 of No. 18 remains at a low level and does not issue a fetch request to the path control 213. For the fetch request, the branch destination address is determined and the control signal line 3
18 becomes low level and the control signal line 221 becomes high level before it is accepted.

As in the above embodiment, a BRI decoder is provided before an instruction is taken into the processor from an external path, and the instruction currently being taken in is a branch instruction, and all instruction bytes making up the branch instruction are taken into the processor. By detecting this, it is possible to output a 7-etch interrupt request at an earlier stage, thereby minimizing invalid instruction fetches.

(Effects of the Invention) As explained above, the present invention provides a BRI decoder in the internal instruction buffer before fetching an instruction from an external data bus, decodes the first byte of the instruction to be fetched, and reads the decoded instruction. In the case of a branch instruction, when it is detected that all the instruction bytes that make up the branch instruction have been fetched, a fetch interrupt request is immediately issued to interrupt the instruction fetch, and the instruction fetch that would be wasted due to the execution of the branch instruction is stopped. This has the effect of minimizing data access latency, reducing data access latency, and increasing computer speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
Figure 3 is a detailed circuit diagram of the Buri decoder shown in Figure 2. Figure 3 is a timing diagram of the operation of the Buri decoder shown in Figure 2.
The figure is a block diagram of a CPU having a conventional instruction prefetch mechanism. 1...External data bus, 2...CPU
% 3...External data bus, 4...-CP
U, 101.201...Instruction path, 102,2
02...Internal command rose 47a, 1
03,203...Cue lead fist counter,
104.204...Queue write φ counter, 105.205...Instruction no(s), 106°2
06...Decoder, 107,207...-
・Microinstruction address bus, 108, 208...
microprogram, 109,209...°control signal group, 110.210...°°゛°execution unit,
111, 221...Fetch interrupt signal line, 11
3,213...path control unit, 114,115.
2141215・°°°°. Address data path, 116.216...
Queue control unit, 117,217°°°°°°F, fetch request signal line, 118,218°--Two-person AND circuit, 119,219...Fetch request signal line,
220... Buri decoder, 222, 223.
...Hue. cycle signal line, 301.302...gate, 303.304...data bus, 305.3
06...Decoder, 307-°"・°°instruction length signal line, 308...Branch instruction signal line, 309.
... Counter, 310 ... Latch, 31
1,312...-° control signal line. 313°“°・°°2 person Kaakaand circuit 14...
・・Control signal line, 315・・・・°・Two-person circuit, 316・・・・Control signal line, 317・°°°°°
Latch circuit, 318 °“. Fetch resume signal line.

Claims (1)

[Claims] In an instruction prefetching method for an information processing device, there is provided a storage means for storing a prefetched instruction, and an instruction word length of the prefetched instruction is detected before the prefetched instruction is stored in the storage means. a detecting means, a decoding means for detecting that the prefetched instruction is at least a branch instruction before the prefetched instruction is stored in the storage means, and control information from the detecting means and the decoding means to detect the branch An instruction prefetch control system comprising: control means for requesting interruption of instruction prefetch as soon as all bytes constituting the instruction are stored in the storage means.