JPS61133439A - Instruction advance fetch control system - Google Patents

Instruction advance fetch control system

Info

Publication number
JPS61133439A
JPS61133439A JP25608684A JP25608684A JPS61133439A JP S61133439 A JPS61133439 A JP S61133439A JP 25608684 A JP25608684 A JP 25608684A JP 25608684 A JP25608684 A JP 25608684A JP S61133439 A JPS61133439 A JP S61133439A
Authority
JP
Japan
Prior art keywords
instruction
fetch
pre
decoder
intermission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25608684A
Inventor
Akira Kuwata
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP25608684A priority Critical patent/JPS61133439A/en
Publication of JPS61133439A publication Critical patent/JPS61133439A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To decrease the data access wait time by providing a pre-decoder to an internal instruction buffer and giving an intermission request of fetch when a decoded instruction is a branch instruction so as to minimize the instruction fetch which would be useless by the execution of the branch instruction.
CONSTITUTION: The pre-decoder 220 is provided to the pre-stage of the internal instruction buffer 202, and when the pre-decoder 220 detects that the fetched instruction if a branch instruction and all instruction bytes constituting the branch instruction are stored in the internal instruction buffer 202, a fetch intermission signal line 221 is brought into a low level to request the intermission of fetch. That is, the branch instruction is detected much earlier by the pre-decoder to the pre-stage of the internal instruction buffer 202, and when it is confirmed that all the instruction bytes constituting the branch instruction are stored to the internal instruction buffer 202, the intermission of the fetch is requested immediately to a bus control section 213 to minimize ineffective fetch.
COPYRIGHT: (C)1986,JPO&Japio
JP25608684A 1984-12-04 1984-12-04 Instruction advance fetch control system Pending JPS61133439A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25608684A JPS61133439A (en) 1984-12-04 1984-12-04 Instruction advance fetch control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25608684A JPS61133439A (en) 1984-12-04 1984-12-04 Instruction advance fetch control system

Publications (1)

Publication Number Publication Date
JPS61133439A true JPS61133439A (en) 1986-06-20

Family

ID=17287696

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25608684A Pending JPS61133439A (en) 1984-12-04 1984-12-04 Instruction advance fetch control system

Country Status (1)

Country Link
JP (1) JPS61133439A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63148329A (en) * 1986-12-11 1988-06-21 Nec Ic Microcomput Syst Ltd Instruction prefetch control system
JPH01263727A (en) * 1988-04-13 1989-10-20 Mitsubishi Electric Corp Data processor
US6934829B2 (en) 1991-07-08 2005-08-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63148329A (en) * 1986-12-11 1988-06-21 Nec Ic Microcomput Syst Ltd Instruction prefetch control system
JPH01263727A (en) * 1988-04-13 1989-10-20 Mitsubishi Electric Corp Data processor
US6934829B2 (en) 1991-07-08 2005-08-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US6986024B2 (en) 1991-07-08 2006-01-10 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution

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