JPH0752402B2 - Data processing device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and more specifically, it is equipped with a pipeline processing mechanism, and variable length instructions are provided one by one for program debugging and the like. The present invention relates to a data processing device capable of executing a trace mode executed by a pipeline processing mechanism.

[Conventional technology]

A pipeline processing mechanism is generally adopted for the purpose of increasing the processing speed of a data processing device.

FIG. 2 is a block diagram showing a configuration of a main part of a data processing device having a conventional general pipeline processing mechanism.

In the figure, reference numeral 1 is an instruction fetch unit, which fetches an instruction code from an instruction memory (not shown) via the data bus 6.

The instruction fetch unit 1 includes an instruction queue 11 that temporarily stores the fetched instruction code, and an instruction fetch control circuit 12 that executes control for instruction fetch.

An instruction decoding unit 2 decodes the instruction code stored in the instruction queue 11 and outputs the result to the instruction executing unit 3
Give to.

The instruction execution unit 3 actually executes the instruction according to the decoding result of the instruction code.

The operation of such a conventional data processing device is as follows.

Under the control of the instruction fetch control circuit 12, the instruction fetch unit 1 fetches an instruction code from an instruction memory (not shown) via the data bus 6 and stores it in the instruction queue 11.

The instruction decoding unit 2 fetches and decodes the instruction code stored in the instruction queue 11, and outputs the decoding result to the instruction executing unit 3.

The instruction execution unit 3 executes an operation in accordance with the decoding result given from the instruction decoding unit 2, and outputs the operation result to the address bus 7 as the storage destination address and the operation result data to the data bus 6 as necessary. By doing so, the data is written in the memory or the like.

As described above, in the data processing device having the pipeline processing mechanism, the processing specified by each instruction is decomposed into three steps of fetch, decode, and execute, and the processing is executed by sequentially processing each step. To be done. Since the processing in each step can be executed in parallel, for example, while the first instruction is being processed by the instruction execution unit 3, the second instruction is processed by the instruction decoding unit 2.
And the third instruction is decoded in the instruction fetch unit 1
Is fetched from the instruction memory at
It becomes possible to simultaneously execute a plurality of instructions in parallel by the pipeline processing mechanism.

Therefore, the three-step pipeline processing mechanism shown in FIG. 2 generally exhibits a processing capacity three times as high as that of the data processing apparatus having no pipeline processing mechanism.

Further, memory access, that is, reading of instructions and data from the memory and writing of data to the memory are generally slower than the processing by the pipeline processing mechanism. Therefore, in order to absorb the difference between the speed of fetching the instruction code from the memory by the instruction queue 11 and the speed of processing the instruction code in the instruction decoding unit 2, the instruction queue 11
Then, as much as possible, specifically, as long as the instruction queue 11 has a free space and the data bus 6 can be used, the instruction code is prefetched (prefetched) from the instruction memory.

By the way, in the data processing device having the above pipeline processing mechanism, only one instruction may be fetched into the pipeline processing mechanism and executed sequentially for the purpose of program debugging. The processing state of such an instruction is called a trace mode, while the state in which pipeline processing by each step of the pipeline processing mechanism described above is performed is called a normal mode.

In the trace mode, the instruction fetch unit 1 fetches the instruction code from the instruction memory and stores it in the instruction queue 11 as in the normal mode.

The instruction decoding unit 2 takes out the instruction code stored in the instruction queue 11, decodes it, and outputs the decoding result to the instruction executing unit 3. After that, the instruction decoding unit 2 does not perform decoding processing of other instructions until the processing of the decoding result of this instruction by the instruction executing unit 3 is completed.

The instruction execution unit 3 executes the designated operation according to the decoding result of the instruction code given from the instruction decoding unit 2,
Writing the operation result to the memory as needed is the same as in the normal mode.

[Problems to be Solved by the Invention]

In the data processing device having the conventional pipeline processing mechanism as described above, when handling an instruction (variable length instruction) in which the instruction code length is not constant, the instruction length must be decoded by the instruction decoding unit 2. Is not known.
Therefore, the fetching of the instruction code into the instruction queue 11 is performed in the trace mode as in the normal mode.

As described above, in the conventional data processing device in which the instruction code is fetched into the instruction queue 11 in the trace mode in the same manner as in the normal mode, there is a bug in the program and the result executed by the instruction execution unit 3 is erroneous. If the error occurs, the memory access is being performed to the instruction that is not executed, so it is not easy to identify the instruction that caused the error, and it is difficult to debug the program.

The present invention has been made in view of such circumstances,
In the trace mode, only one instruction executed on the pipeline processing mechanism is stored in the instruction queue 11 and unnecessary memory access is not performed to debug the program when an error occurs in the instruction execution unit. An object is to provide an easy data processing device.

[Means for Solving the Problems]

In the trace mode in which instructions are processed one instruction at a time by the pipeline processing mechanism, the data processing apparatus controls the instruction fetch section to fetch an instruction code for each unit of instruction fetch according to the decoding result in the instruction decoding section. It has a circuit.

[Action]

In the data processing device of the present invention, in the trace mode, as many instruction codes as necessary are fetched according to the decoding result in the instruction decoding unit, so only the instruction code corresponding to one instruction is fetched and stored in the instruction fetch unit. To be done.

Example of Invention

Hereinafter, the present invention will be described in detail with reference to the drawings showing an embodiment thereof.

The instructions handled by the data processing device of the present invention have a variable length in halfword units. One word is a unit of a certain length (for example, 16 bits = 2 bytes) for indicating the length of the instruction code.

Further, each instruction is composed of an operation code for designating an operation to be executed and an operand representing information regarding data to be operated.
The operation code can specify 1 halfword and the operand can specify 0 to 2 halfwords. Therefore, the instruction length is between 1 halfword and 3 halfwords.

FIG. 1 is a block diagram showing a configuration example of a main part of a data processing device according to the present invention.

In the figure, reference numeral 1 is an instruction fetch unit, which fetches an instruction code from an instruction memory (not shown) via the data bus 6.

The instruction fetch unit 1 stores the fetched instruction code in 4
An instruction queue 11 that can temporarily store up to 8 words (8 half words), an instruction fetch control circuit 12 that executes control for instruction fetch, and an instruction fetch switching circuit 13 are included. The instruction queue 11 is divided into eight equal parts by a broken line, which means that each partition has a capacity of storing one half word.

The instruction fetch unit 1 starts processing when an instruction processing start signal 32 output from an instruction execution unit 3 described later is given.

The instruction fetch switching circuit 13 is supplied with a normal fetch request signal 15 from the instruction queue 11, a trace mode signal 31 from the instruction executing section 3, and a trace mode fetch request signal 14 from the instruction decoding section 2 which will be described later. The instruction fetch control circuit 12 is instructed according to these signals.

Specifically, the instruction fetch switching circuit 13 has two 2-input ANs.
It is composed of D gates 21 and 22 and one 2-input OR gate 23.

The normal fetch request signal 15 is applied to one input of the first AND gate 21, and the inverted signal of the trace mode signal 31 is applied to the other input. The trace mode fetch request signal 14 is applied to one input of the second AND gate 22, and the trace mode signal 31 is applied to the other input. The outputs of the AND gates 21 and 22 are given to both inputs of the OR gate 23, and the output of the OR gate 23 is given to the instruction fetch control circuit 12.

Therefore, when the trace mode signal 31 is invalid (low level), the first AND gate 21 is enabled. Therefore, when the normal fetch request signal 15 is valid (high level), this is sent to the instruction fetch control circuit 12. Given. On the other hand, when the trace mode signal 31 is valid, the second AN
Since the D gate 22 is enabled, when the trace mode fetch request signal 14 becomes valid, it is given to the instruction fetch control circuit 12.

An instruction decoding unit 2 decodes the instruction code stored in the instruction queue 11 and outputs the result to the instruction executing unit 3
Give to. Further, the instruction decoding unit 2 is also provided with a trace mode signal 31 and an instruction processing start signal 32 from the instruction executing unit 3, and the instruction fetch unit 1 is supplied to the instruction fetch unit 1 in the trace mode according to these signals and its own decoding processing state. On the other hand, the trace mode fetch request signal 14 for requesting fetch in 1-word units is output.

The instruction execution unit 3 actually executes the instruction according to the decoding result of the instruction code. It also outputs a trace mode signal 31 and an instruction processing start signal 32 to the instruction fetch unit 1 and the instruction decoding unit 2.

The operation of the data processing apparatus of the present invention thus configured is as follows.

When the instruction processing start signal 32 is output from the instruction execution unit 3,
This is given to the instruction fetch unit 1 and the instruction decode unit 2 to start the processing.

In the normal mode, the trace mode signal 31 is disabled. Then, under the control of the instruction fetch control circuit 12, the instruction fetch unit 1 fetches an instruction code from an instruction memory (not shown) via the data bus 6 and stores it in the instruction queue 11. This instruction fetch unit 1 fetches an instruction code as long as the instruction queue 11 has a free space.
It is repeated word by word using the time when the data bus 6 is idle.

Specifically, if there is a free space in the instruction queue 11, the instruction queue 11
Outputs the normal fetch request signal 15 to the instruction fetch switching circuit 13, but since the trace mode signal 31 is invalid, the instruction fetch switching circuit 13 outputs the normal fetch request signal.
15 is selected and given to the instruction fetch control circuit 12. As a result, the instruction fetch control circuit 12 fetches the instruction code in units of one word and stores it in the instruction queue 11 every time the normal fetch request signal 15 is output from the instruction queue 11. At this time, if there is more free space in the instruction queue 11, the instruction queue 11
Outputs the normal fetch request signal 15 again, the instruction fetch control circuit 12 further fetches one word.

The instruction decoding unit 2 fetches and decodes the instruction code stored in the instruction queue 11, and outputs the decoding result to the instruction executing unit 3.

Decoding of the instruction code by the instruction decoding unit 2 is
First, one halfword is fetched from the instruction queue 11 and decoded to determine the number of words in the operand. Next, the necessary operands are fetched from the instruction queue 11, decoded, and output to the instruction execution unit 3 together with the decoding result of the previous operation code.

The instruction execution unit 3 executes an operation in accordance with the decoding result given from the instruction decoding unit 2, and outputs the operation result to the address bus 7 as the storage destination address and the operation result data to the data bus 6 as necessary. By doing so, the data is written in the memory or the like.

As described above, in the data processing device of the present invention, the instruction fetch unit 1, the instruction decoding unit 2, and the instruction execution unit 3 independently execute the processing in the normal mode, so that, for example, the first instruction is executed by the instruction execution unit 3. A plurality of instructions in the pipeline processing mechanism such that the second execution is decoded in the instruction decoding unit 2 while the third instruction is fetched from the instruction memory in the instruction fetching unit 1 while being processed in. It becomes possible to execute simultaneously.

Therefore, the three-step pipeline processing mechanism shown in FIG. 1 generally exhibits a processing capacity three times as high as that of a data processing apparatus having no pipeline processing mechanism.

In the trace mode, the trace mode signal 31 output from the instruction executing section 3 becomes valid. When the trace mode signal 31 becomes valid, the instruction fetch switching circuit 13 selects the trace mode fetch request signal 14 output from the instruction decoding unit 2 to select the instruction fetch control circuit.
Give to 12.

The instruction fetch unit 1 fetches an instruction code from the instruction memory and stores it in the instruction queue 11 as in the normal mode. The control at this time is controlled by the trace mode signal 31, and the trace mode fetch request signal 14 Each time it becomes valid, the instruction fetch control circuit 12 fetches only one word and stores it in the instruction queue 11.

The instruction decoding unit 2 takes out and decodes one halfword corresponding to the operation code portion of the instruction code stored in the instruction queue 11. The decoding result is 2
When requesting a halfword operand, only one halfword remains in the instruction queue 11 (the first fetched is one word, from which one halfword for the operation code has already been instructed). The instruction decoding unit 2 outputs the trace mode fetch request signal 14 again.

When the trace mode fetch request signal 14 is output again, the instruction fetch unit 1 fetches the next one word and stores it in the instruction queue 11.

Now, since three halfwords are stored in the instruction queue 11, the instruction decoding unit 2 extracts and decodes two halfwords of the halfwords, and the instruction execution unit 3 along with the decoding result of the previous operation code. Output to.

When the trace mode signal 31 output from the instruction executing unit 3 is valid, the instruction decoding unit 2 completes the decoding of one instruction, and then the processing of the decoded result by the instruction executing unit 3 is completed. Until this is done, the decode processing of other instruction codes is not performed.

The instruction execution unit 3 executes the designated operation according to the decoding result of the instruction code given from the instruction decoding unit 2,
Writing the operation result to the memory as needed is the same as in the normal mode.

When the execution process for one instruction is completed, the instruction processing start signal 32 is output. This instruction processing start signal
When 32 is output, the instruction fetch unit 1 and the instruction decoding unit 2 execute the processing in the trace mode as described above again.

In the above embodiment, the pipeline processing mechanism is composed of the instruction fetch unit 1, the instruction decoding unit 2 and the instruction execution unit 3 in three steps. The present invention is also applicable.

〔The invention's effect〕

As described above, in the data processing device of the present invention, in the normal mode, the instruction fetch unit, the instruction decoding unit, and the instruction execution unit independently operate in parallel to pipeline a plurality of instructions. In the trace mode, only the instruction code of one instruction is fetched, decoded, and executed. For this reason,
Since only necessary memory accesses are executed and unnecessary memory accesses are not performed, program debugging becomes easy.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a data processing device according to the present invention, and FIG. 2 is a block diagram showing a configuration example of a data processing device having a conventional pipeline processing mechanism. 1 ... Instruction fetch section, 2 ... Instruction decode section, 3 ...
Instruction execution unit, 11 ... Instruction queue, 12 ... Instruction fetch control circuit, 13 ... Instruction fetch switching circuit In the drawings, the same reference numerals indicate the same or corresponding portions.

Claims (1)

[Claims] 1. An instruction fetch unit that divides a variable-length instruction into predetermined units and prefetches it, a storage unit having a plurality of units of capacity for temporarily storing the instructions prefetched by the instruction fetch unit, and the storage unit. In an instruction decoding unit for decoding an instruction stored in the instruction processing unit and an instruction execution unit for executing the instruction according to the decoding result of the instruction decoding unit, In the trace mode in which the processing of the next instruction is started after the processing of one instruction is completed by the line processing mechanism,
The memory means stores one unit of an instruction, and the instruction fetch unit is provided with a control circuit that causes the instruction fetch unit to fetch the continuation of the instruction one unit at a time according to a decoding result of the stored content of the instruction decoding unit. And data processing device.