JPH0812601B2 - Data processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a stored program control data processing device, and more particularly to a mechanism for updating a program address value corresponding to the word length of an instruction being executed.

[Background of technology]

A stored program controlled data processing device addresses a memory with the contents of a counter that holds program address information, reads an instruction word from the memory, decodes the instruction word, and executes corresponding data transfer / arithmetic operation. are doing.

The factors that control the processing speed of the apparatus are the instruction word read (hereinafter referred to as instruction fetch) time and the memory access time for reading / writing processing data. Therefore, when processing the internal register information of the data processing device, the instruction word to be executed next is fetched in advance from the memory without processing data access, thereby improving the efficiency of memory access and increasing the processing speed. A so-called preceding instruction fetch method is adopted.

In the above-described speed-up method, the prefetched instruction word is stored in the buffer register, and predetermined processing such as instruction decoding, data transfer, and arithmetic operation is executed based on the instruction word in the buffer. However, if the instruction to access the memory as the processing data is frequently executed, the above method cannot fetch the instruction word from the memory.
Depending on the type of instruction to be executed and the program, the prefetchable state of the instruction word changes. In order to improve the efficiency of memory access and realize high-speed processing without being affected by this state change, it is effective to increase the buffer storage capacity of the instruction word that is fetched in advance. A device has been proposed.

In a data processing device equipped with an instruction buffer having a plurality of word capacities, a pointer (hereinafter referred to as a fetch pointer) for designating a memory address from which an instruction word is read and an instruction word address in an execution process corresponding to inputs and outputs of a buffer storage. A counter that holds (hereinafter referred to as program counter)
It is customary to have two types of hardware registers:

The former fetch pointer control is linked to the operation of prefetching an instruction word and storing it in the instruction buffer, and updates the address value of the instruction to be fetched next, and can be realized by a simple logic circuit. However, the latter program counter control is simple addition such as updating the counter information corresponding to the instruction word length, loading the branch address value in the execution of the branch instruction, and saving / returning to the stack in the subroutine call / return instruction. Complex processing that cannot be performed by processing is required.

[Conventional technology and problems]

A block configuration of a data processing device of basic prefetch control will be described with reference to FIG. The apparatus of FIG. 1 stores a memory 20 for storing programs and processing data, an instruction register 40 for holding an instruction word to be executed, and an instruction word of the instruction register 40 for decoding a control signal 500 to each part of the apparatus. An instruction decoder 50, an arithmetic circuit 60 for processing an arithmetic logic operation, a program counter 70 for holding a program address, a general-purpose register 80 for storing processing data such as data transfer and operation, and a multipurpose register 80, processing In addition to a temporary register 90 for temporarily storing data and the like, a fetch pointer 10 for holding a fetch address for prefetch control, and an instruction buffer 30 for storing instruction word information for prefetch, and via a data bus 100. Data is transferred between each part of the device.

Generally, in a data processing device, a general-purpose register operation instruction has many advantages as compared to memory operation instructions, i) there are many kinds, ii) instruction word length is short, and iii) processing time is short. Often used to do data processing.

In the execution of the general-purpose register operation instruction, data is transferred between the arithmetic circuit 60 and the general-purpose register 80 via the data bus 100, the memory 20 is accessed, and the memory data is not transferred via the input / output line 202. Instead, the memory 20 is addressed by the fetch pointer 10 and the instruction word is sent to the data line 20.
1 can be stored in the read instruction buffer 30, and instruction execution and subsequent instruction fetch can be processed in parallel to shorten the instruction processing time of the data processing device.

If the storage capacity of the instruction buffer 30 is increased, the preceding fetch works effectively and the instruction buffer 30 can be kept sufficiently stored with the instruction word to be executed. However, in this state, the execution time of the instruction processing sequence for performing data transfer / arithmetic operation among the various parts of the device such as the memory 20, the arithmetic circuit 60, the program counter 70, the general-purpose register 80, and the temporary register 90 is the instruction processing time. If a mechanism that can shorten the instruction processing sequence is provided, the instruction processing time can be further shortened.

Here, the instruction processing sequence is classified into execution of processing defined as an instruction function such as data transfer / operation and updating of program address linked to instruction execution. The present invention relates to the latter. The address control will be mainly described.

In the command words of the data processing device, there are plural word length commands including processing constants and address specification parts in addition to word length commands that only specify operations, and all of them execute the process by reading one word from the command buffer. .

In the device shown in FIG. 1, the operation command part, which is the first word of the command, is transferred from the command buffer 30 via the data line 301 and stored in the command register 40. The units are transferred from the instruction buffer 30 to the temporary register 90 and the memory 20 via the read data line 302 and the data bus 100, respectively. Here, in synchronization with the reading from the instruction buffer 30, i) the contents of the program counter 70 are transferred to the arithmetic circuit 60 via the data bus 100, and ii) the arithmetic circuit 60 adds 1 to the next instruction. An address value is generated, and iii) the operation result is transferred via the data bus 100, stored in the program counter 70, and a series of program address update processing is performed.

In i) and iii) of the address update process, the transfer is performed via the data bus 100, and during this period, the command word information cannot be transferred from the command buffer 30 to the memory 20 or the temporary register 90, and the data is transferred in different periods. Since the command word information is transferred, the processing sequence and its processing time increase.

Therefore, if the number of times of processing for updating the program address can be reduced, the instruction processing time can be shortened, and in particular, an instruction having a plurality of word lengths is effective.

Next, the program address control in the call instruction of the subroutine processing will be described by showing the processing sequence below.

i) The first word of the instruction is transferred from the instruction buffer 30 to the instruction register 40.
Then, the instruction decoder 50 decodes the subroutine call instruction and updates the contents of the program counter 70 to the address value corresponding to the second word of the instruction.

ii) The second word of the instruction indicating the subroutine address is transferred from the instruction buffer 30 to the temporary register 90, and the content of the program counter 70 is updated to the start address value of the next instruction word.

iii) Transfer and store the contents of the program counter in the stack area of the memory 20 and save it in preparation for the return from the subroutine.

iv) Program counter the contents of temporary register 90
Transfer to 70 and the fetch pointer 10 to start the instruction fetch of the subroutine program.

In this way, even in processing based on call instructions,
The processing sequences i) and ii) are required to update the address of the program counter 70, and there is a problem that the processing sequence and the processing time thereof increase.

[Object of the Invention]

It is an object of the present invention to provide a data processing device capable of processing the update of the content of the program counter according to the instruction word length at the optimum timing of the instruction processing sequence in a short time.

[Configuration of Invention] That is, according to the present invention, in order to determine whether the data processing device that fetches an instruction in advance and stores it in the buffer register can process the instruction, it is asked whether or not there is valid instruction word information in the buffer register. Control information is required, and this information is positively used, and the contents of the program counter are updated by also serving as an arithmetic circuit for executing instructions.

Example of Invention

FIG. 2 shows a block diagram of a data processing device according to an embodiment of the present invention, and a detailed description thereof will be given. In FIG. 2, fetch pointer 10, memory 20, instruction buffer 30, instruction register 40, instruction decoder 50, arithmetic circuit 60, program counter 70, general-purpose register 80, data bus 100 and control signal 5
00 is the same as the basic device in FIG. 1, and detailed description thereof will be omitted, and the description will focus on the relationship with instruction processing.

First, when the instruction processing is completed, the instruction decoder 50 generates a control signal 500 indicating that the instruction processing is completed and informs the instruction buffer 30 of the operation data of the instruction designation information of the instruction word to be executed next from the instruction buffer 30. Store in instruction register 40 via line 301. Next, the stored operation designation information is decoded by the instruction decoder 50 to determine whether or not the instruction is a plural word length instruction including a processing constant and an address designation section, and a control signal 501 is generated to generate the instruction word. Command to determine whether all are stored in the instruction buffer 30,
The determination result signal 303 from the instruction buffer 30 is determined to determine the subsequent control.

When it is confirmed that the information necessary for executing the process is stored in the instruction buffer 30 in the determination, the instruction decoder 50 determines that the control signal corresponding to the processing of the instruction to be executed for each unit of the data processing device. 500 is generated to start instruction processing such as data transfer and calculation. In the previous instruction processing, all the instruction information may not be stored in the instruction buffer 30 when the processing data is frequently accessed to the memory 20, and if the state is detected by the judgment result signal 303, the instruction processing is performed. Is suspended and the instruction fetch operation is continued until the necessary instruction word information is gathered. In this data processing device, at the same time as the state determination of the buffer storage, the control signal 501 instructing the determination is sent to the word length register 1
Information is stored in 10, and the word length register 110 holds information indicating how much word length the instruction for starting the process has. Therefore, the contents of the program counter 70, which is the instruction word start address value in the execution process, are added to the word length register
By adding the stored information of 110, the start address information of the instruction word to be executed next can be generated. Further, at the optimum timing of the instruction processing sequence, the contents of the program counter 70 and the word length register 110 are transferred to the arithmetic circuit 60 via the data bus 100 to calculate the next instruction address, and the arithmetic result is sent to the program counter 70. After storing, the program address is updated.

The transfer and arithmetic operation of the data stored in the memory 20 and the general-purpose register 80, which are defined as the instruction function, are processed by performing data transfer with the arithmetic circuit 60 as in the device of FIG.

The information stored in the instruction buffer 30 is unnecessary when the operation designation information of the instruction word is transferred to the instruction register 40 and when the processing constants and addressing information in the instruction word are derived via the data line 302. Become. In the embodiment shown in FIG. 2, the storage status of information that is unnecessary when the above condition is satisfied in the execution process is cleared to set the storage area to an empty state, and the instruction buffer 30 becomes empty in the buffer storage area. When this is detected, the empty area is clogged to align the buffer storage information, and at the same time, the preceding fetch control signal 304 is generated to notify the fetch pointer 10. In the data processing device of the embodiment, the preceding fetch control signal 304 indicating that the buffer storage area has a space is output, and the control signal 500 generated by the instruction decoder 50 detects that there is no processing data access to the memory 20. At this time, the memory 20 is addressed by the fetch pointer 10 to store the instruction word in the read instruction buffer 30, and the content of the fetch pointer 10 is updated to the address value for the next instruction fetch.

A circuit configuration of the instruction buffer circuit 30 and the instruction register 40 in the embodiment of the present invention shown in FIG. 2 is shown in FIG. 3 that are the same as those in FIG. 2 are given the same numbers. The circuit shown in FIG. 3 can store the instruction information having a length of 4 words including the instruction register 40. Registers 311, 312, 313 store the instruction words in a buffer and perform a first-in-first-out shift. The flip-flops 321, 322, 323, 324 hold the status of whether valid instruction information is stored in the corresponding registers 311, 312, 313 and the instruction register 40, respectively, and the set state indicates that the valid information is stored in the corresponding register, and the The state indicates an empty state in which valid information is not stored. Gate circuit 331,332,333,
334 controls the first-in-first-out shift when the instruction buffer write signal 341, the buffer read signal 342, and the instruction processing end signal 343 become active. The status selection circuit 350 has flip-flops 321 to 3 indicating the states of the registers 311 to 313 and the instruction register 40 according to the designation of the control signal 501 generated by the instruction decoder 50.
Buffer status judgment signal by selecting one of 24 signals
It is transmitted to the instruction decoder 50 as 303. When the flip-flop in the reset state is selected by the status selection circuit 350, the determination result signal 303 indicating that there is no valid information in the corresponding register is transmitted, the data processing device suspends and suspends the instruction processing, and sets the data in the set state. When the flip-flop is selected, the determination result signal 303 indicating that there is valid information is transmitted, and the instruction processing is continued.

First, when the instruction decoder 50 generates the instruction processing end signal 343, the flip-flop 324 is reset and the corresponding instruction register 40 becomes empty. Gate circuit 334
Command register 40 based on the values of flip-flops 323 and 324.
When it is empty, it is determined that valid information is stored in the register 313, and the stored information in the register 313 is transferred to the instruction register 40 via the data line 301. At the same time as the operation, the flip-flop 324 corresponding to the instruction register 40 is set, the flip-flop 323 corresponding to the register 313 is reset, the instruction register 40 enters a storage state of valid information, and the register 313 has no valid information, that is, an empty state. Becomes When the register 313 becomes empty, the adjacent register 3
The gate circuit 322 determines whether valid information is stored in 12 and transfers the information to the register 313. When the register 313 stores valid information (the flip-flop 323 is set), the register 312 is empty (the flip-flop 322 is reset)
To

Similarly, the state of adjacent registers 312 and 311 is gated.
The determination is made in 331, the information in the register 311 is transferred to the register 312, and the states of the flip-flops 321 and 322 are set.

As a result of continuously performing the above operation between the adjacent registers one after another, the register 311 becomes empty (the flip-flop 321 is reset), the signal 304 indicating the state is transmitted to the fetch pointer 10, and instruction fetch is prompted, An instruction word is read from the memory 20 and control is performed to maintain the state in which valid information is buffer-stored in the registers 311 to 313.

When the information after the second word, that is, the information stored in the instruction buffers 311 to 313 is used as a processing constant or addressing information in the process of processing an instruction, an instruction decoder
Generate buffer read signal 342 from 50 to register 313
Information is derived to the data bus 100 via the data line 302. At the same time, the flip-flop 323 is reset based on the buffer read signal 342 through the gate circuit 333, and the register 313 is set to the empty state.

After that, as described above, the presence or absence of valid information is determined between the adjacent registers, information is transferred, and the buffer storage is aligned.

To determine whether an instruction with multiple word lengths has been fetched,
Based on the operation designation information of the instruction decoder 50, the instruction decoder 50 generates the control signal 501 and the status selection circuit 3
This is done by instructing 50 to select the flip-flop signals shown in the table below and determining the state of the selected flip-flop.

Since the registers 311 to 313 and the instruction register 40 are always controlled to pack the register information when an empty state occurs in the middle register, the flip-flop 321 is selected and the valid information is stored in the register 311. If it is determined that the valid information is also stored in the register 312, the register 313, and the instruction register 40, it can be determined that all of the 4-word length instructions have been fetched. Similarly, it is possible to determine the completion of fetching the 3-word length instruction, the 2-word length instruction, and the 1-word length instruction, respectively, corresponding to the selection of the flip-flops 322, 323, and 324. Here, the control signal 501 is a coded signal of a plurality of bits, and the fetch completion determination word length is determined corresponding to the code. In other words, the control signal 501 is a signal indicating the instruction word length, and in the embodiment shown in FIG. 2, this information is stored in the word length register 110, the stored information is added to the content of the program counter 70, and the next execution is performed. The start address value of the instruction to be generated is generated.

FIG. 4 shows the circuit configuration of the word length register 110 of the embodiment. The word length register 110 receives the control signals 501-0, 501-1 and 501-2, which are 3-bit information, as input, and sets the OR gate 40 in a state in which the control signals are not in operation.
1, the values of the control signals 501-0, 501-1, 501-2 are stored in the latch circuits 402, 403, 404, respectively, and when the data processing device operates the program address modification operation, the constant generation circuit 405 outputs the latch circuits 402-403. Is added to generate data corresponding to the bit width of the address and the data is sent to the data bus 100.

In the apparatus of the embodiment, an instruction having a length of 1 to 4 words is assumed, the binary code of the control signal 501 is associated with the number of determination word lengths, and stored in the 3-bit latch circuit as it is. A constant 0 generated by the constant generation circuit 405 is added to the upper bits to generate word length information for address modification.

〔The invention's effect〕

As described above, according to the present invention, even if the instruction has a plurality of word lengths, the start address of the instruction to be executed next can be generated by one arithmetic operation, and the processing time for updating the program address can be shortened to achieve high-speed processing. A data processing device can be provided. Furthermore, it is possible to update the program address at any timing during the instruction execution process, such as when the instruction word information is unused and stored in the buffer register. It is possible to reduce the amount of hardware required for the data processing device and to provide a data processing device with excellent cost performance.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a data processing device which performs basic prefetch control, FIG. 2 is a block configuration diagram of a data processing device of one embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. Instruction buffer and instruction register circuit configuration diagram,
FIG. 4 is a circuit configuration diagram of a word length register in one embodiment of the present invention. 10 ... Fetch pointer, 20 ... Memory, 30 ... Instruction buffer, 40 ... Instruction register, 50 ... Instruction decoder, 60
...... Arithmetic circuit, 70 …… Program counter, 80 …… General purpose register, 90 …… Temporary register, 100 …… Data bus, 110 …… Word length register, 201,202,301,302 …… Data line, 303,304,341,342,343 …… Signal line, 500,501,501-
0,501-1,501-2 ... Control signal line, 311,312,313 ... Register, 321,322,323,324 ... Flip-flop, 331,3
32,333,334 …… Gate circuit, 350 …… Selection circuit, 401 ……
OR gate, 402,403,404 …… Latch circuit, 405 …… Constant generation circuit.

Claims (1)

[Claims] 1. A program counter for storing a program address, an arithmetic circuit for performing arithmetic processing on supplied data and coupled to the program counter via a data bus, a memory for storing instruction word information, and a plurality of memory cells. A buffer register having a register for storing instruction word information read word by word from the memory prior to execution of an instruction; an instruction register for temporarily storing instruction word information output from the buffer register; and the buffer A plurality of flip-flops provided corresponding to the plurality of registers and the instruction register, respectively, which are in a set state when valid instruction word information is stored in the corresponding registers, and stored in the instruction register An instruction including the instruction word information is required by decoding the generated instruction word information. Control information for instructing whether or not the instruction word information to be stored in the buffer register is generated, and the control information for selecting one of the plurality of flip-flops is generated according to the instruction word length of the instruction. And a selection circuit that selects one of the plurality of flip-flops based on the control information and transfers the state of the selected flip-flop to the instruction decoder. A data processing device that holds execution of an instruction until necessary instruction word information is available in the buffer register when the selected flip-flop is not in the set state, and holds the control information in the data bus. A combined word length register is provided, and the arithmetic circuit is connected to the program counter and the program counter via the data bus. Data processing apparatus, wherein a content of Kigocho register updates the receive said program address transferred to the program counter.