JPH07120281B2 - Information processing equipment - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus that controls and processes instruction processing in advance by a pipeline processing method.

[Conventional technology]

Conventionally, an information processing apparatus that adopts this type of pipeline processing system is disclosed in, for example, Japanese Patent Laid-Open No. 58-96345.
Provide multiple instruction buffers and execute the branch instructions before execution.
When the processing stream of the branch target instruction (a series of instruction strings read from the storage device) is read and it is determined that the branch is taken, the input to the instruction decode circuit is input from the stream (main stream) in which the branch instruction appears. By immediately switching to the branch target instruction processing stream, the overhead of reading the branch target instruction is reduced.

In addition, in the address buffer corresponding to each instruction buffer,
The read address of the instruction processing stream is held, and when the instruction is executed, the instruction length of the instruction is added to the address of the address buffer corresponding to the stream being processed to obtain the next consecutive instruction address.

When a branch instruction is executed, the next instruction address is obtained, and the instruction read address of the address buffer corresponding to the target stream of the branch destination is selected.
Seeking the branch destination instruction address.

These next instruction address and branch destination instruction address are used as a return address when an interrupt or failure occurs during execution of the instruction.

The instruction address during the execution of this processing is stored in the instruction counter register and used for management of the instruction processing execution.

The instruction count value (address of the instruction being executed) that manages the execution of such instruction processing is referred to as an instruction counter here.

FIG. 3 is a block diagram showing a main part of an example of a conventional pipeline processing type information processing apparatus.

In FIG. 3, 31 is a first instruction buffer, 32 is a second instruction buffer, 33 is a third instruction buffer, 34 is a selector, 35 is an instruction decoding circuit, 36 is a branch judging circuit, and 37 is an execution waiting instruction. Queue, 38 is a selector for selecting instruction information from the pending instruction queue 37, 39 is an instruction address adder,
40 to 42 are instruction address adder 39 or instruction decode circuit
A selector for selecting an instruction counter from 35, 43 is a first instruction counter buffer, 44 is a second instruction counter buffer, 45 is a third instruction counter buffer, and 46 is a selector.

In this information processing apparatus, instruction processing is processed by a pipeline processing method.

That is, the execution of each instruction process forms a stream of a series of instruction sequences, and in the stream, each processing stage (instruction read stage, decode stage, operand read stage, operation execution stage, etc.) is sequentially advanced and piped. It is executed in line processing.

The instruction sequence 1 is stored in each of the instruction buffers 31 to 33 for each stream of instruction processing.
It corresponds to 43 to 45 respectively.

The instruction to be executed next is selected by the control signal from the branch determination circuit 36, for example, selected from the first instruction buffer 31 by the selector 34, supplied to the instruction decoding circuit 35, and decoded.

When the instruction decoding circuit 35 decodes the instruction, it stores the instruction length and the instruction stream number in the execution-waiting instruction queue 37 together with the setup information necessary for executing the operation of the instruction.

The command processing information stored in the pending command queue 37 is
Selected by the selector 38, the setup information 2a, the instruction length 2b, and the instruction stream number 2c are output to each.

When entering the operation execution stage, the instruction counter buffer 43
From among 45 to 45, the instruction counter corresponding to the stream of the instruction processing is selected and output by the selector 46 according to the instruction of the instruction stream number 2c.

Further, the instruction address adder 39 adds the instruction length 2b to the instruction counter and selects the selector 40 as the next instruction counter.
~ 42 to the original instruction counter buffer.

When the branch instruction is decoded by the instruction decode circuit 35, a branch destination instruction address is output from the instruction decode circuit 35 and a stream for the branch destination instruction is formed. Therefore, the instruction is read from the instruction sequence 1 and is empty. It is stored in any of the instruction buffers 31 to 33.

At this time, the branch destination instruction address output from the instruction decoding circuit 35 is held in the corresponding instruction counter buffers 43 to 45.

As a concrete example of the instruction processing operation in such an information processing apparatus, the case where the processing of the instruction sequence including the branch instruction is executed is taken as an example, and a state in which a stream corresponding to the instruction processing is generated and the instruction processing is performed explain.

FIG. 4 is a diagram showing an example of an instruction stream for explaining the instruction processing operation of the information processing apparatus of FIG.

It should be noted that all the branch instructions shown in FIG. 4 are decoded by the decode circuit 35 before the instruction operation is executed at the operation execution stage of the pipeline processing, and the branch decision circuit 36
Is a branch instruction whose branch establishment is determined by.

When the information processing device executes instruction processing of an instruction sequence, it generates a stream of instruction processing and executes instruction processing by pipeline processing.

First, the stream of instructions to be executed is stored in the first instruction buffer 31, and the instruction counter is set in the first instruction counter buffer 43.

As a result, the first stream # 0 serving as the main stream is generated, and the instruction processing of the instruction string by the pipeline processing is executed.

When the instruction processing 50 of the stream # 0 proceeds and the branch instruction 51 appears, the branch instruction 51 generates the stream # 1 for the instruction processing 52 of the branch destination.

Therefore, the second instruction buffer 32 that stores the instruction of the branch destination instruction string is secured, and the branch destination instruction address is set in the second instruction counter buffer 44.

Here, since the branch instruction 51 is a branch instruction for which the branch determination circuit 36 determines that the branch is taken when it is decoded by the decode circuit 35, the instruction processing of the preceding control performed by the pipeline processing is performed on the stream # 1. Then, the flow proceeds to the execution of the instruction processing 52 of stream # 1.

When the instruction processing 52 proceeds, the branch instruction 53 appears next in the processing in the stream # 1.

In this case also, similarly to the above, the branch instruction 53
In order to generate the stream # 2 corresponding to the instruction processing 54 of the branch destination, the third instruction buffer 33 that stores the instruction of the instruction sequence of the branch destination is secured, and the branch destination instruction address is set to the third instruction counter buffer 45. Set to.

Here again, since the branch instruction 53 is a branch instruction whose branch is determined by the branch determination circuit 36 when it is decoded by the decoding circuit 35, the instruction processing of the preceding control performed by the pipeline processing is performed on the stream # 2. Then, the flow proceeds to the execution of the instruction processing 54 of stream # 2.

In this case, the branch instruction 55 again in the stream # 2.
When appears, a stream for instruction processing of a branch destination is newly generated in the same manner as described above.

At this time, since the first instruction buffer 31 corresponding to the stream # 0 is not used, the branch instruction 55 tries to secure the first instruction buffer 31, but the operation execution stage of the branch instruction 51 is still in progress. If it is not running,
The first instruction counter buffer 43 cannot be released.

Therefore, the decoding of the branch instruction 55 is delayed until the branch instruction 51 is executed.
The flow of pipeline processing is disturbed, and the processing speed of instructions decreases.

[Problems to be Solved by the Invention]

As described above, in the conventional pipeline processing type information processing device, a branch instruction is taken at the time when it is decoded by the decode circuit before the operation of the instruction is executed in the operation execution stage of the pipeline processing. Even if the instruction in the instruction buffer from which the branch instruction was read is unnecessary, the instruction counter buffer that stores the read address in the instruction processing stream is Since it corresponds to, until the branch instruction is executed and the instruction counter is obtained,
The corresponding instruction buffer cannot be released.

Therefore, when the branch instructions appear consecutively, there is a problem that it is difficult to improve the performance of the instruction processing because the instruction reading of the subsequent branch instruction in the branch destination stream is waited.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a branch instruction in which a branch instruction is determined to be taken at a decode stage in an information processing apparatus that performs instruction processing by a pipeline processing method. In the case of an instruction, the instruction buffer in which the unnecessary instruction is stored and the branch instruction is read is promptly released, and the stream of the branch destination stream of the subsequent branch instruction can be read. is there.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems]

In order to achieve the above object, in the present invention, information processing of a pipeline processing method is performed in which each processing stage of instruction reading, decoding, operand reading, and execution is sequentially performed, and processing for each instruction is overlapped. In the apparatus, a plurality of instruction buffers that store a series of instructions of an instruction sequence to be processed as a stream, an address buffer that holds the instruction read addresses of the respective streams in correspondence with the streams, and instructions read from the streams. Is a branch instruction, stores a new branch destination stream in the instruction buffer, and stores the instruction read address of the new stream in the address buffer, and manages the execution of instruction processing. An instruction counter register for storing an instruction count value, and When executing an instruction other than the branch instruction read from the stream, a first means for adding the instruction length of the instruction and the contents of the instruction counter register and storing the result in the instruction counter register, and reading from the stream When the branch instruction is executed, the instruction read address of the stream of the branch destination is output from the address buffer, set in the instruction counter register, and the instruction read address of the stream from which the branch instruction is read is stored. The second means for releasing the address buffer, and the first means or the second means when the branch stage of the branch instruction read from the stream is determined in the decode stage. And a means for releasing the instruction buffer from which the branch instruction has been read. Characterized in that it has.

[Action]

According to the means, in the information processing apparatus of the pipeline processing system, a plurality of instruction buffers for storing a stream of a series of instructions of an instruction sequence to be processed, and instruction read addresses of each stream are held, and the instruction buffer is An address buffer that can be controlled independently is provided.

The read address of each stream is stored in an address buffer controlled independently of the instruction buffer, and the instruction counter is obtained by the address buffer.

When the branch destination stream is read, the read address is stored in the address buffer.

When it is determined in the decode stage that the branch of the branch instruction is taken, the instruction processing of the preceding control performed in the pipeline processing moves to the branch destination stream, and the instruction buffer from which the branch instruction is read is released.

When an instruction other than a branch instruction is executed, the next successive instruction address is obtained by adding the instruction length to the instruction counter stored in the address buffer corresponding to the instruction stream.

When a branch instruction is executed, the address buffer corresponding to the branch destination stream is selected to obtain the branch instruction address.

Thus, the address buffer storing the instruction counter is released when the branch stream is switched from the main stream to the branch destination stream by executing the branch instruction.

Since the instruction counter is calculated independently of the instruction buffer in this way, it becomes possible to immediately release the unnecessary instruction buffer when the branch instruction is determined.

〔Example〕

An embodiment of the present invention will be specifically described below with reference to the drawings.

FIG. 1 is a block diagram showing a main part of an information processing apparatus of a pipeline processing system according to an embodiment of the present invention.

In FIG. 1, 11 is a first instruction buffer, 12 is a second instruction buffer, 13 is a third instruction buffer, and each of the buffers 11, 12, and 13 is a flag indicating a used or released state. have.

14 is a selector, 15 is an instruction decoding circuit, 16 is a branch judgment circuit, 17 is an execution waiting instruction queue, 18 is an execution waiting instruction queue
Selector for selecting instruction information from 17; 19 for instruction address adder; 20 for instruction counter queue; 21 for selector for selecting instruction counter from instruction counter queue 20; 22 for instruction address adder 19 or selector 21 A selector for selecting an instruction counter, and 23 is an instruction counter register.

In this information processing device, instruction processing is processed by a pipeline processing method, and each instruction processing forms a stream of a series of instruction sequences, and in the stream, the instruction processing is performed by an instruction read stage, a decode stage, and an operand read. Each processing stage of the stage and the operation execution stage is sequentially advanced and executed.

The instruction sequence 1 is stored in each instruction buffer 11 to 13 for each stream of instruction processing.

The instruction read addresses corresponding to these instruction streams are stored in the instruction counter queue 20, respectively.

The instruction to be executed next is selected by the control signal from the branch determination circuit 16, for example, selected by the selector 14 from the first instruction buffer 11 and supplied to the instruction decoding circuit 15 to be decoded.

When the instruction decoding circuit 15 decodes the instruction, the instruction length 2
b, the subsequent branch destination flag 2b indicating whether the subsequent instruction is a branch destination instruction, and the setup information 2a necessary for executing the operation of the instruction are stored in the execution waiting instruction queue 17.

The subsequent branch destination flag 2d becomes logical "1" when the decoded instruction is a branch instruction and the branch destination stream is subsequently processed.

Further, when the branch instruction is decoded, the branch destination instruction address is stored in the instruction counter queue 20.

The instruction to be executed (instruction information) is selected from the execution-waiting instruction queue 17 by the selector 18, and when entering the operation execution stage, the instruction counter is output from the instruction counter register 23.

At this time, if the subsequent branch destination flag 2d is logical "0",
The instruction address adder 19 that adds the instruction length 2b to the instruction counter stored in the instruction counter register 23 by controlling the selector 22 with the subsequent branch destination flag 2d output from the execution-waiting instruction queue 17 through the selector 18 The instruction counter which is the output from is selected and set in the instruction counter register 23.

On the other hand, when the subsequent branch destination flag is logical “1”, the selector 22 is controlled so that the selector 21 moves from the instruction counter queue 20 to the selector 21.
The instruction counter output via is selected and set in the instruction counter register 23.

That is, when an instruction is cut out from the pending instruction queue 17 and set up, if the instruction is a different stream from the previously set up instruction, the instruction counter queue 20 corresponding to the stream is selected. 21 is controlled.

Next, the instruction processing operation in such an information processing apparatus will be concretely described by taking as an example the case where the processing of an instruction sequence including a branch instruction is executed, and a stream corresponding to the instruction processing is generated and the instruction processing is performed. Will be explained.

FIG. 2 is a diagram showing an example of an instruction stream for explaining the instruction processing operation of the information processing apparatus of FIG.

All the branch instructions in FIG. 2 are decoded by the decode circuit 15 before the operation of the instruction is executed in the operation execution stage of the pipeline processing, and the branch decision circuit 16
Is a branch instruction whose branch establishment is determined by.

When the information processing device executes instruction processing of an instruction sequence, it generates a stream of instruction processing and executes instruction processing by pipeline processing.

First, the stream of instructions to be executed is stored in the first instruction buffer 11, and the instruction counter is the instruction counter register.
Set to 23.

As a result, the first stream # 0 serving as the main stream is generated, and the instruction processing of the instruction string by the pipeline processing is executed.

When the instruction processing 24 of the stream # 0 proceeds and the branch instruction 25 appears, the branch instruction 25 generates the stream # 1 for the instruction processing 26 at the branch destination.

Therefore, the second instruction buffer 12 that stores the instruction of the branch destination instruction string is secured, and the branch destination instruction address is set in the instruction counter queue 20a.

When the branch instruction 25 is decoded by the decode circuit 15, the branch determination circuit 16 determines that the branch is taken.
The instruction processing of the preceding control performed in the pipeline processing moves to stream # 1, and here, the first instruction buffer 11 is released.

Since the instruction following the branch instruction 25 is the branch destination instruction,
When the instruction information from the instruction decoding circuit 15 is stored in the execution-waiting instruction queue 17, the subsequent branch-destination flag indicating that the subsequent instruction is a branch destination is stored in the execution-waiting instruction queue 17 as logical "1". .

As a result, the instruction processing moves to the stream # 1, the processing proceeds to the instruction processing 26, and when the instruction processing 26 further proceeds, the branch instruction 27
Appears.

Even in this case, similarly to the case of the branch instruction 25,
An instruction buffer is prepared.

As the prepared instruction buffer, for example, the third instruction buffer 13 is secured, and the branch instruction address is set in the instruction counter queue 20b.

The branch instruction 27 is determined by the branch determination circuit 16 when the branch instruction 27 is decoded by the decoding circuit 15,
The preceding control instruction processing performed in the pipeline processing moves to stream # 2, and the second instruction buffer 12 is released here.

Since the instruction following the branch instruction 27 is the branch destination instruction,
When the instruction information from the instruction decoding circuit 15 is stored in the execution-waiting instruction queue 17, the subsequent branch-destination flag indicating that the subsequent instruction is a branch destination is stored in the execution-waiting instruction queue 17 as logical "1". .

As a result, the branch destination stream # 2 is generated, and the instruction processing 28 is advanced.

When the branch instruction 29 appears again when the instruction processing 28 of the branch destination stream is advanced, a stream for instruction processing of the branch destination is newly generated in the same manner as described above.

At this time, since the first instruction buffer 11 has already been released, the decoding of the branch instruction 29 is not suppressed and the first instruction buffer 11 is not suppressed.
Secures the instruction buffer 11 and sets the branch instruction address in the instruction counter queue 20c.
At 0, the instruction processing 30 proceeds.

Further, when the branch instruction 25 enters the operation execution stage, the subsequent branch destination flag indicating that the instruction following the branch instruction 25 is the branch destination instruction is logical “1”.
, The output side of the selector 21 is selected.

As a result, the value of the instruction counter queue 20a is set in the instruction counter register 23, and the process proceeds as the instruction counter at that time and the instruction counter queue 20a
Is released.

In this way, the instruction counter queue 20 becomes an address buffer for storing the read address of the instruction stream.
By controlling the instruction counter queue 20 independently of each of the instruction buffers 11 to 13, if the branch determination is immediately made, the instruction buffer is released without waiting for the operation execution stage of the branch instruction. be able to.

Therefore, even when branch instructions appear consecutively, the processing speed can be increased without disturbing the flow of pipeline processing.

In FIG. 2, if the branch instruction 27 is, for example, a branch instruction whose branch is taken or not taken when the operation of the instruction is executed in the operation execution stage of pipeline processing, The third instruction buffer 13 for storing the instructions of the previous instruction sequence is secured.

In this case, the instruction processing of the advance control performed in the pipeline processing is a non-branch stream (stream # 1) from which the branch instruction 27 is read, as in the conventional information processing apparatus.

The main parts of the information processing apparatus according to the present embodiment are summarized as follows.

(1) A plurality of instruction buffers (11 to 13) store a series of instruction streams of an instruction sequence to be processed. The read address of each stream is the instruction buffer (11
To 13) are stored in an instruction counter queue (address buffer) 20 which is controlled independently.

(2) When an instruction other than a branch instruction is executed, the instruction address adder 19 adds the instruction counter and the instruction length, and the next instruction address following the instruction is obtained and output as the instruction counter.

At this time, the output of the instruction address adder 19 is selected by the selector 22 and stored in the instruction counter register 23 as a continuous next instruction address.

(3) When it is determined in the decode stage that the branch of the branch instruction is taken, the instruction processing of the preceding control performed in the pipeline processing moves to the branch destination stream, and the instruction buffer (11 to 13) from which the branch instruction is read out. ) Is released.

(4) When the branch instruction is executed, the address stored in the instruction counter register 23 is output, at the same time, the instruction address of the branch destination stream is selected by the selector 21, and the output of the selector 21 is output by the selector 22. Is selected and the branch destination instruction address is stored in the instruction counter register 23.

(5) As a result, the instruction buffers (11 to 13) can be released without waiting for the operation execution stage of the branch instructions, so that even if the branch instructions appear consecutively,
It is possible to speed up the processing without disturbing the flow of the pipeline processing.

(6) In addition, the instruction buffer (11 to 13) and the instruction counter queue 20 are independently controlled, and the instruction buffer (11
~ 13) and the release timing of the instruction counter queue 20 are different, and the read address of the released instruction buffer (11 to 13) is stored in the instruction counter queue 20 even after the instruction buffer (11 to 13) is released. Incidentally, since the instruction counter queue 20 is released when the branch instruction is actually executed and the stream moves to the branch destination, for example,
The instruction processed by the pipeline method is followed by the arithmetic instruction first, the branch instruction second, and the like. Before the first arithmetic processing is completed, it is determined that the branch of the second branch instruction is taken, and the instruction buffer (11 to 13) Even if the instruction counter queue is released
Since the read address is stored in 20, even if an interrupt occurs at the end of the first arithmetic process,
The read address in the instruction counter queue 20 can be used, and it is possible to respond promptly.

The present invention has been specifically described above based on the embodiments,
It is needless to say that the present invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention.

〔The invention's effect〕

As described above, according to the present invention, the instruction buffer in which each stream is stored and the address buffer in which the instruction read address of each stream is stored are independently controlled, and branching is established in the decode stage. In the case of a branch instruction to be judged, the instruction buffer storing the unnecessary stream is released without waiting for the execution of the branch instruction, so the branch destination stream of the subsequent branch instruction can be read. It is possible to speed up branch instruction processing.

Even if the instruction buffer and the address buffer are released at different timings, the instruction read address of the unnecessary stream is stored in the address buffer even after the instruction buffer that stores the unnecessary stream is released. , When a branch instruction is actually executed and the stream moves to the branch destination stream, the address buffer that stores the instruction read address of the stream that became unnecessary due to the branch judgment is released. Even if an interrupt or the like occurs, it is possible to promptly respond.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of an information processing apparatus of a pipeline processing system according to an embodiment of the present invention, and FIG. 2 is a diagram for explaining an instruction processing operation of the information processing apparatus of FIG. FIG. 3 shows an example of an instruction stream, FIG. 3 is a block diagram showing a main part of an example of an information processing apparatus of a conventional pipeline processing system, and FIG. 4 shows an instruction processing operation of the information processing apparatus of FIG. It is a figure which shows the example of the instruction stream for doing. In the figure, 11,31 ... first instruction buffer, 12,32 ... second instruction buffer, 13,33 ... third instruction buffer, 14,18,2
1,22,34,38,40,41,42,46 …… Selector, 15,35 …… Instruction decode circuit, 16,36 …… Branch decision circuit, 17,37 …… Execution waiting instruction queue, 19,39 ...... Instruction address adder, 20 ...
… Instruction counter queue, 23 …… Instruction counter register.

Claims (1)

[Claims] 1. An instruction sequence to be processed in an information processing apparatus of a pipeline processing system, in which processing stages of instruction reading, decoding, operand reading, and execution are sequentially performed, and processing for each instruction is overlapped. A plurality of instruction buffers that store a series of instructions as a stream, an address buffer that holds the instruction read address of each stream in correspondence with the stream, and that the instructions read from the stream are branch instructions. A means for judging, storing a new stream of a branch destination in the instruction buffer, and storing an instruction read address of the new stream in the address buffer, and an instruction for storing an instruction count value for managing execution of instruction processing Counter register and branch read from the stream When executing an instruction other than the instruction, a first means for adding the instruction length of the instruction and the contents of the instruction counter register and storing the result in the instruction counter register; and branching of a branch instruction read from the stream When the previous instruction is executed, the instruction read address of the branch destination stream is output from the address buffer, set in the instruction counter register, and the instruction read address of the stream from which the branch instruction is read is stored. Second to release the address buffer in the open
And the step of reading the branch instruction before executing the first means or the second means when the branch stage of the branch instruction read from the stream is determined in the decode stage. And a means for releasing the instruction buffer.