JPH03263224A - Data processor - Google Patents

Abstract

PURPOSE:To efficiently prefetch an instruction by forecasting success or failure of branch by a programmer and designating it with a branch instruction. CONSTITUTION:In the case of a branch instruction, the instruction code of the instruction read out to a program buffer 2 is sent to an instruction decoding circuit 14, and a signal line 17 is driven because of the branch instruction; and if a forecast bit 15 in the branch instruction is set, the output of an AND gate 18 goes to '1', and an address selecting circuit 13 selects a branch address instructed in the lower order of the branch instruction and sends it to a main storage device 1, thus prefetching the instruction in the branch destination. If the forecast bit 15 is not set, the output of the AND gate 18 is '0' and a normal instruction address selecting circuit 12 is selected to prefetch the normal sequence. Thus, success or failure of branch is forecasted by the program and is designated by the branch instruction to efficiently prefetch the instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device that prefetches instructions in main memory.

[Prior Art] Conventionally, in order to increase the instruction execution speed in a data processing device, instruction reading is prefetched, but when a branch instruction is issued, the instruction at the branch destination is prefetched and read, and when the branch condition is met, the instruction is prefetched. It was configured so that the instructions at the branch destination could be executed.

[Problems to be Solved by the Invention] The conventional data processing device described above operates most effectively when the branch condition in the branch instruction is met, but when the branch condition is not met, the data processing device operates again in the next instruction after the branch instruction. The disadvantage is that reading must begin. In other words, when a branch instruction is read, the instruction at the branch destination is always read, so it is effective if the probability of the branch condition being met is high, but it has the disadvantage of being inefficient if the probability of the branch condition being met is low. there were.

An object of the present invention is to provide a data processing device that can efficiently prefetch instructions.

[Means for Solving the Problems] A data processing device of the present invention includes a branch instruction including a branch condition prediction bit provided in an instruction code, a circuit for detecting the branch instruction, and a prefetch instruction reading system. In said branch instruction as the request address,
and a selection circuit that selects a branch destination address by the branch instruction when the prediction bit is set, and selects an address of an instruction sequence to which the branch is not to be branched when the prediction bit is not set.

[Operation] Instruction preemption can be performed efficiently by specifying whether a branch is established or not established in a program or a pre-branch instruction.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a data processing device according to an embodiment of the present invention, and FIG. 2 is a time chart showing the operation of this embodiment in comparison with a conventional one.

The block diagram stored in the main memory device 1 is read out to the program buffer 2, and usually program buffers 3 and 4 are read out to the program buffer 2.
The command is then stored in the instruction register 5. The contents of the instruction register 5 are sent to the data processing section 6, decoded and executed, and data processing is performed. Also, program buffer 2,
3.4 and instruction register 5, registers 7.8.9.10 for holding addresses exist on the main memory of the program and are used as addresses for prefetching instructions.

Now, in the case of a normal instruction that is not a branch instruction, it is read out to the instruction register 5 and processed by the data processing unit 6, but because the program is prefetched, several instructions are stored at the address of the current instruction (program buffers 2, 3, 4). The next address (changes depending on the situation) is added and sent to the main memory device 1 via the address selection circuit 12, 13, and a read request is made.

Next, in the case of a branch instruction, the instruction code of the instruction read into the program buffer 2 is sent to the instruction decoding circuit 14, and since it is a branch instruction, the signal line 17 is driven, and the prediction bit 15 in the branch instruction is set. If
The output of the AND gate 18 becomes "1", and the address selection circuit 13 does not normally select the output of the instruction address selection circuit 12, but selects the branch address 16 specified below the branch instruction and sends it to the main memory 1. , prefetch the instructions at the branch destination.

If the prediction bit 15 of this branch instruction is not set or if it is not a branch instruction, the output of the AND gate 18 is "0", and the normal instruction address selection circuit 1
2 is selected and the normal sequence is prefetched.

Next, the operation of this embodiment will be explained with reference to the timing chart of FIG.

In this figure, instructions A, A+1. A+2. -..., the instruction A+2 is a branch instruction, and it is assumed that the branch destination instruction is B. Figure vI2 (1) shows a case in which there is prefetching of instructions in the conventional method, but there is no prefetching of branch destinations.
12 is a timing chart in which a condition for branch instruction A+2 is satisfied. The memory request address, program buffers 2, 3.4, and instruction register 5 are set with the addresses and contents of the addresses as shown in the figure.

Also, A, A+1. B is an instruction that requires two stages, and A+2 is a branch instruction that completes in one stage.

The 0 point when A+2 is set in the instruction register 5 is already A+.
A read request of 5 has been issued, an instruction A+3 is set in program buffer 4, and an instruction A+3 is set in program buffer 4.
+4. A+5 is read out. However, when the branch instruction A+2 branches, it is necessary to read the instruction B, and A+3. A+4. Discard the A+5 command.

Processing must be interrupted until B is set in the instruction register 5. That is, in this time chart, it is necessary to wait four stages.

Next, the time chart of FIG. 2(2) shows a case where there is prefetching of the branch destination and the condition of branch instruction A+2 is satisfied. In this case, when A+2 is set in the program buffer 2, a read request for B is made, so one stage of wait is sufficient.

Next, the time chart in FIG. 2(3) shows a case where the branch destination is preempted, but the branch condition is not satisfied. When A+2 is set in the program buffer 2, a read request is made for B, and then B+1 is also requested, but the branch condition for A+2 in the instruction register 5 is not satisfied, so B.

It is necessary to discard B+1 and read from A+4 onward, requiring three stages of wait.

Table 1 summarizes the weight numbers shown in FIG. 2, and is a table comparing the conventional weight numbers and the weight numbers when using the expected bits of this embodiment.

(Left below) In this table, when the branch prediction bit is set, the number of waits for branch establishment/unestablishment is the same as before, 1 wait/3 waits, but when the branch prediction bit is not set, it is 4 waits and 10 waits. It's a weight.

That is, when a branch is taken, this embodiment is the same as or slower than the conventional method (when no branch prediction is made), but when the branch is not taken, this embodiment is the same or faster than the conventional method. Therefore, it is a comparison between branching when the programmer predicts that it will not branch and not branching, but in general, when programming, programmers can predict with a certain probability, so the probability of not branching is higher than when branching when they predict that it will not branch. It is thought that there is an overwhelmingly high probability that the branch will not occur. Therefore, when a branch is predicted to fail and the branch fails, three waits can be wasted compared to the conventional method.

FIG. 3 shows branch instructions B1, B2. B3. Table 2 is a flowchart of the program including B4, and Table 2 shows the table branch instructions B1. B2. B
3. Are the probabilities of branching/not branching for each of B4 and the average number of weights in this embodiment using the branch prediction bit and in the conventional case not using the branch prediction bit the same when the branch prediction bit is set? , the number of cases in which the branch prediction bit is not set is smaller in this embodiment.

The average number of weights passing through 81 to B4 is 7.2 in the conventional case, or 5.4 in the case of this embodiment, which clearly shows the effect.

[Effects of the Invention] As described above, the present invention has the advantage that instructions can be preempted efficiently by allowing the programmer to predict whether a branch will be taken or not and specifying it in a branch instruction.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the main parts of a data processing device according to an embodiment of the present invention, FIGS. 2 (1), (2), and (3) are timing charts showing operations of the conventional and this embodiment, The figure is a flowchart of a program including branch instructions 81 to B4. 1... Main memory device, 2, 3.4... Program buffer, 5... Instruction register, 6... Data processing section,
7.8.9.10...Instruction address register, 11.
. . . Instruction prefetch count, 12 . . . Normal instruction address selection circuit, 13 . . Address selection circuit, 14 . . Branch instruction decoding circuit, 18 . . . Ant gate.

Claims (1)

[Claims] 1. In a data processing device that prefetches instructions in main memory, a branch instruction including a prediction bit of whether a branch condition is met or not established provided in an instruction code, a circuit for detecting the branch instruction, and a prefetch instruction read request address a selection circuit that selects an address to be branched to by the branch instruction when the branch instruction is set and the expected bit is set, and selects an address of an instruction sequence that does not branch when the expected bit is not set; A data processing device comprising: