JPS5991552A - Instruction prefetch device having set associative type history table - Google Patents

Abstract

PURPOSE:To forecast an address to be branched with a comparatively high hit rate by using a set associative type history table to control preferch, in an information processing device. CONSTITUTION:A directory storage part 501 in a branch history table 410 stores a part of the instruction address of a branch instruction and V bits indicating whether the contents of the part are effective or not and a data storage part 502 stores the real address of an address to be branched. The contents of respective levels of the storage part 501 read out by regarding a part of a request address in an instruction address register 411 as a setting address are compared with a part of the contents of the register 411 and whether these contents coincide with each other or not is detected by test circuits 503-506 or the like. At the time of coincidence, a branch forecasting signal 106 with a corresponding level is generated, and if the coincidence of two or more parts is formed, a priority circuit 507 selects a signal with a lower level to read out the address to be branched stored in a storage part 502 through a selecting circuit 508.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a set for preempting the next instruction while predicting the judgment result prior to execution of a branch condition judgment step included in a step of an instruction sequence of a data processing system. The present invention relates to an instruction prefetching device having an associative branch history table.

BACKGROUND OF THE INVENTION In a data processing system in which a group of instructions including at least one branch instruction is stored in a storage device in the form of an instruction sequence, execution of such an instruction sequence is performed in the following manner.

First, a branch instruction is stored at a branch source address in the storage device. Next, the instruction to be executed following this branch instruction is prefetched. After this, a branch instruction is executed, and the result of this execution reveals the next instruction to be executed.

Such a system is proposed in US Pat. No. 4,2CQ927. However, in this system, if the branch instruction preemption control is stopped until the execution result is determined, speeding up of processing will be hindered.

In order to eliminate this drawback, a method has been proposed in which the execution result of a branch instruction is predicted in advance and instructions are preempted in accordance with this prediction. When this prediction is made correctly, the data processing system operates with little delay in processing time. For example, there are the following three methods as such conventional prediction methods. In the first prediction method, the branch destination direction of all branch instructions is predicted to be either the successful side or the unsuccessful side.

Another prediction method predicts the branch destination direction based on past facts. That is, by using the fact that the branch destination has already been revealed in the past execution results of the same branch instruction and making predictions based on these results, the prediction accuracy rate is increased. A typical example of such a prediction method is shown in Japanese Patent Laid-Open No. 57-76638.

In yet another prediction method, a large number of branch instruction flags are prepared to predict the direction of a branch in response to a branch instruction, and the branch destination is predicted by referring to these branch instruction flags in response to the occurrence of a branch instruction. There is. For details of this example, refer to Japanese Unexamined Patent Publication No. 53-74857. However, in any of the above three prediction methods, reading a branch instruction,
Deciphering is essential, and despite prediction, there is a drawback that processing is delayed by these reading and decoding operations.

A prediction method that eliminates this drawback is disclosed in Japanese Patent Application Laid-Open No. 57-59253.
It is shown in the publication No. In this method, the branch destination address of the branch instruction contained in the block of the instruction cache memory, which is a copy of the instruction part of the main memory, is stored as the address of the block to be fetched next after the block. Holds on to means. In the instruction prefetching operation, the storage means is accessed simultaneously with the access to the instruction cache memory to read the branch destination address, and the address of the instruction to be prefetched is determined based on the read branch destination address. This method is different from the above-mentioned three conventional prediction methods and is effective in speeding up processing. However, in this method, prediction is made in correspondence between the instruction cache and the memory block, so when a plurality of branch instructions exist in the block, prediction cannot be made corresponding to each branch instruction. As a result, there is a drawback that only a prediction hit rate with low accuracy can be obtained.

OBJECTS OF THE INVENTION It is an object of the present invention to provide an instruction preemption device having a set ancillary type branch history table which eliminates the above-mentioned drawbacks.

Structure of the Invention The instruction prefetching device having a set-unsociative type branch history table of the present invention includes a directory storage section that holds a part of the address of a branch instruction, and a directory storage section that holds a part of the address of a branch instruction, and a directory storage section that holds a part of the address of a branch instruction, and branch history table means constituted by a set associative type memory, including a data storage section configured to store branch information including information specifying a branch destination address of a branch instruction; In the instruction prefetching operation, checking means for checking whether information specifying the address of the branch instruction to be preempted has been registered in the branch history table means; When it is found that information specifying the address of the branch instruction to be preempted is registered in the table means,
The instruction prefetch control means reads branch information corresponding to the branch instruction to be preempted from the branch history table means and controls to start the next instruction prefetch operation according to the branch information.

Principle and operation of the invention The feature of the present invention is based on the fact that in addition to the branch direction in the execution of a branch instruction, the branch destination address can be predicted with a relatively high accuracy by understanding the past results of the same branch instruction. The purpose is for the device to operate according to the conditions.

Embodiment of the Invention Next, an embodiment of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, one embodiment of the present invention includes an instruction address generation circuit 401, an instruction address conversion circuit 402,
Instruction decoding circuit 4o3, operand address generation circuit 40
4 Operand address conversion circuit 405, operand reading circuit 4o6 having operand storage circuit, instruction execution circuit 407, instruction storage circuit 408, instruction buffer 409
, branch history table (BHT) 410. Instruction address register 411, instruction address addition circuit 412, branch information buffer 413, instruction alignment circuit 414, branch information switching circuit 415, branch information register 416°417.418
．． and 419, a prediction confirmation circuit 42o1, an address generation circuit 421, a selection circuit 422, a register 423, an instruction prefetch control circuit 424, and a flip 70 tube 425.

Instruction storage circuit 408 and operand read circuit 406
Both operand storage circuits in the main memory may be the main memory itself, and the instruction storage circuit 408 may be an instruction cache-memo 1 block which is a copy of a portion of the instruction portion of the main memory.
The operand storage circuit may be configured as an operand cache memory that is a copy of a portion of the operand portion of main memory.

The present invention does not necessarily need to have a device configuration corresponding to the above-mentioned instruction processing units; for example, an instruction address generation circuit 401, an operand address generation circuit 404, an instruction address conversion circuit 402, an operand address conversion circuit 405, and an instruction memory. The present invention can also be applied to a conbeater system in which the memory circuits in the circuit 408 and the Yooverand readout circuit 406 are shared. The branch history tree (BHT) 410 stores information specifying the address of a branch instruction, a branch no flag as a prediction of execution of the branch instruction, and a branch destination address in pairs as shown in FIG. The instruction address register (IAR) 411 for the instruction storage circuit 408 holds an instruction read request address and executes an instruction read operation. Furthermore, the instruction address register 411 (IAR) is connected to branch history tables 410 (B) (T) and an instruction address addition circuit 412 via a signal line 101. The contents of the register 411 are indexed into the branch history table 410 (BAT) and a signal is output to the signal line 106 indicating whether the address of the instruction to be read is registered therein. If registered, the corresponding branch destination address is read out onto the signal line 105. If it is not registered, the instruction address addition circuit 412 generates an address for the instruction preemption of the subsequent instruction word. The instruction address addition circuit 412 is a circuit that simply outputs "IAR+8" 107 when it is assumed that the instruction word read in one request is 8 bytes. The instruction buffer 409 stores a 3-byte preemption instruction word read from the instruction storage circuit 408, and forms a queue (QLlef) for supplying instructions to the instruction processing section. The instruction alignment circuit 414 includes an instruction buffer 4
When 09 is empty, the instruction storage circuit 4
When the instruction buffer 409 is not empty in response to the 8-byte instruction word read from the signal line 103, the instruction is extracted in response to the 8-byte instruction word stored in the instruction buffer via the signal line 103. This circuit supplies instructions to the instruction decoding circuit 403 via the instruction decoding circuit 403. The branch information buffer 413 is prepared corresponding to the instruction word stored in the instruction buffer 409, and if there is a branch instruction predicted to be a successful branch among the instruction words, the branch information buffer 413 is prepared in accordance with the instruction word stored in the instruction buffer 409. This is a circuit that stores branch information of a branch instruction, and the address of the branch instruction is sent via the signal line 101, and the branch destination address and V bit as branch information are sent via the signal line 105 from the branch history table 410 (BHT). Each is set via the The branch information switching circuit 415
outputs the branch information respectively. The registers 416, 417, and 418 correspond to each processing stage of instruction decoding, instruction address generation, and address translation of a branch instruction, and hold branch information thereof. The branch information register 419 is a register that replaces the branch destination address field with an actual branch destination address generated by executing the branch instruction. The prediction confirmation circuit 42
0 is a circuit that matches the actual branch instruction generation result generated by the execution of the branch instruction with the prediction information of the branch instruction held in the branch information register 418. The address generation circuit 421 is connected to the branch information register 41.
The address of the branch instruction held in 9 and the instruction word length of the branch instruction 1 are added to generate the instruction address of the instruction on the branch N0GO side. The selection circuit 422 responds to the state of the branch instruction success/failure signal line 111 to determine whether the state of the signal line is branch GO.
When the state of the line indicates branch N0GO, the output of the branch destination address field held in the branch information register 419 given via line 115 is selected, and when the state of the line indicates branch N0GO, line 116 is selected.
The output of the address generation circuit 421 given via the signal line 113 is selected, and the output of the selection circuit 422 is supplied to the register 423 via the signal line 113. The register 423 is used to update the branch history pull 410 (BHT) when prediction of a branch instruction fails, and is also used to update the branch history pull 410 (BHT) via the signal line 117 to the instruction address register 411.
(IAR) with a new address for instruction preemption. The instruction prefetch control circuit 424 controls the instruction address register 411 (IAR) based on the branch prediction signal provided from the branch history table 410 (BHT) via line 106 and the prediction success/failure signal provided from the prediction confirmation circuit via line 112. This is a circuit that controls the input of the

Next, the branch history table 410 (BUT), the prediction confirmation circuit 420 and the instruction prefetch control circuit 424
While referring to the detailed block diagram and time chart of
The operation of this embodiment will be explained in detail.

Referring to FIG. 2, the branch history table 410
(EiHT) includes a directory storage section 501, a data storage section 502, test circuits 503, 504, 505° and 506, a priority circuit 507, and a level selection circuit 5.
08 and an OR circuit 509. The storage units 501 and 502 are storage units with the number of sets m1 and the number of levels n, with the unit of the instruction word read from the instruction storage circuit 408 in response to one request being the unit of block.

Referring to FIG. 3, a part of the instruction address of a branch instruction and the V bit indicating whether or not the contents are valid are stored in the storage unit 501, and a real address of the branch destination address is stored in the storage unit 502. ing.

The V bit is stored in the corresponding branch history table (BHT
) 410 and has the function of a branch success/failure flag as a prediction of execution of the branch instruction.

Indexing into the branch history table (BHT) 410 is performed using the set associative method as described below.

The test circuits 503, 504505 shown in FIG.
, and 506 indicates whether the request address held in the instruction address register 411 (IAR) corresponding to each level of the table 410 is registered in the BHT AA4 of each level (t indicates a suffix corresponding to the level). The signal indicating
Output to 33.

Referring to FIG. 4, the test circuits 503 and 504
.

Each of 505 and 506 is a device composed of a match circuit 701 and a magnitude comparison circuit 702.
28) is read as the set address in the storage unit 501
The content of each level is compared with the content IAR (:4-17) of the register 411 to detect whether an address equal to 1 exists. The output of the matching circuit 701 is 8B of the instruction word to be read at the request address held in the instruction address register (IAR) 411.
In the yte block, the branch history table (B
It is determined whether there is a branch instruction registered in HT) 410. However, the above-mentioned coincidence detection alone is insufficient to establish a correspondence between the request address and the branch instruction from which it should be read.

Referring to Figure 5, 8 is read in one request.
2 Byte instruction BOO in a block of Byte instruction word
, A, BOl, and BO2 exist. Command B
C! 0. When both BOI and BO2 are branch instructions predicted to be successful, part of the address of each branch instruction is registered in the storage unit (BHT-AA) 501. At this time, when branching to instruction A from another branch instruction, the address <A> of instruction A is the instruction address register (
IAR) 411, the branch instruction information to be read from the branch history table (BHT) 410 must be the information of the branch instruction BC1 from the instruction execution path.

Therefore, the request address held in the register (IAR) 411 and the storage unit (BH'I"-AAi)
When the following relationship with the address of the branch instruction held in 501 holds together with the above matching condition, a BHT-HITi signal of a corresponding level is generated. This signal is applied to the third circuit 509 via lines 130-133, and the OR signal of the BHT-HITi signal is output via line 106 to become a branch prediction signal (BHT-HIT signal).

BHT-HIT i = (I plate (: 4-17) =
BHT-AAi (:4-17) ) Convex (1 gong (:2
9,30) Theft-benefit i (:29,30)) Convex BHT-
AAi (V) Referring again to FIG. 4, the magnitude comparison circuit is a circuit that realizes this condition. Furthermore, the signal BHT-H
When the condition of ITi is satisfied at two or more levels, the value of the address BHT-AAi (:29, 30) in the 8-byte block of the address of the branch instruction held in the corresponding level (BHT-AAi) of the storage unit 501 is The smallest level should be selected.

Referring again to FIG. 5, instructions BOI and BO2
The signal BHT-HIT i conditions are both satisfied at the level of the branch history table 410 in which branch instruction related information is stored. At this time, from the instruction execution path to the instruction BO
A level for I needs to be selected. The priority circuit 507 selects two of the signals BHT-HITi.
This output corresponds to the set address IAR(:18) of the storage unit BHT-DA502.
The branch destination address of the entry indicated by -28) is read out via the level selection circuit 508.

Referring to FIG. 6, the priority circuit 507 includes a group of AND circuits 601-604 and a group of OR circuits 605-
608. The AND circuit group 601-
n+1 pieces of 604 are arranged in parallel. The selection signals of the level selection circuit 508 in FIG. 2 are the signals ■o, ■1°V2. V3 is given as follows.

When VO VOLO+■0”1 + “”””
"" + voL,.

Vo/Vt Notoki VII'02VIL1+""...""
”+VIIaVo・V?v2 (7) Toki V2LO, V2
L1. −・−・・−・−−−・、V2I41VO°■
1・v2°Va notoki V3IJOIV3L1+ --+
VaLn As described above, the branch information read from the level selection circuit 508 in FIG. 2 can be associated with the instruction read from the instruction storage circuit 408 in FIG. 1.

FIG. 9 shows the above-mentioned correspondence between instructions in the instruction storage circuit 408 and branch information in the branch history table (BHT) 410. Instruction execution order is instruction Ao
Branch instructions BCo, B□, BCl, B2゜B3, BO2,
This is a case where B3, BO2, C11C2...... is predicted. In addition, <A> is the address of the human command,
BOj indicates a branch instruction.

Referring to FIG. 10, the instruction prefetching operation by the branch history table BHT 410 shown in FIG. 9 is performed as follows. An instruction word is read from the instruction storage circuit 408 in response to the request address being set in the instruction address register 411, and at the same time, the table BHT 410 is indexed.

When the BHT-1-IIT signal is output via the signal line 106, the branch destination address <B
1> is set in the address register 411, and the instruction is prefetched. BHT-HI via the signal line 106
When the T signal is not output, the current address is output, and the next instruction is preempted sequentially.

According to the above instruction prefetching scheme, the instruction words read from the instruction storage circuit 408 are read out sequentially according to the prediction based on the contents of the table BHT 410, and can be stored in the instruction buffer 409 in the predicted execution order of the instructions. It is.

At this time, even if the signal BHT-HIT is output,
The instruction prefetching operation in the branch prediction direction may be performed after partially performing the instruction prefetching operation on the side opposite to the branch prediction direction.

When the instruction preempted as described above is a branch instruction and is guided to the instruction decoding circuit 403 by the instruction alignment circuit 414 of FIG. 1, the branch information corresponding to the branch instruction is transferred to the first branch information register. It is set to 416 (QR・0).

Thereafter, as the branch instruction progresses, the branch information is stored in the second and third branch information registers 417 (QRl) and 418 (CaB6) corresponding to the instruction decoding and address conversion.
) will be forwarded to. Then, the prediction confirmation circuit 420 checks whether the actual branch instruction generation result generated by executing the branch instruction matches the prediction information of the branch instruction held in the branch information register 418 (QR2).

Referring to FIG. 8, the prediction confirmation circuit 12° is a comparison circuit 801, flip 70 knobs 802 and 803, AND circuits 804-806, and truth/false circuits 807 and 808.
, and an OR circuit 809. The comparison circuit 801 stores the real address of the branch destination address υ generated by the execution of the branch instruction in the instruction address conversion circuit 402.
is given via signal line 109, and the branch destination predicted from branch information register 418 (QR2) is given via line 108. The comparison circuit 801 determines whether the two match or do not match. The determination result and the V pit provided from the register 418 via the line 108 are provided to an AND circuit 806. Branch G depending on logical result
When an O is predicted, a signal indicating this fact is set in the flip-flop 802. This flip flop 80
If the output of 2 is "fl" and the result of executing the actual branch instruction is branch N0GO, a predicted GO failure signal 123 is generated from the AND circuit 805.The flip-flop 801
If the output of the branch instruction is "°1" and the execution result of the branch instruction is GO, a predicted N0GO failure signal 125 is generated from the AND circuit 808.Furthermore, the logical sum of the signal 124 and the predicted Go failure signal 123 is generated by an OR circuit. Prediction failure signal 1 from 809
12.

Referring to FIGS. 1 and 11, the branch destination address newly generated from the instruction address conversion circuit 402 is set in the branch destination address field of the branch information register 419 (QR3). In addition, the branch information register 41
The address generation circuit 421 adds the contents of the address field of the branch instruction BC1 of 9 (Qft3) and the contents of the instruction word length field of the branch instruction BC1 itself to generate the instruction address of the instruction of the branch NOGO9tl.

Then, when the branch instruction BC1 is actually executed, if the branch is GO, the output of the branch destination address field <D
If l> is a branch N0GO, the output <B2> of the address generation circuit 421 provided via the line 116 is selected by the selection circuit 422. The prediction failure signal 112 of the branch instruction BOI is sent from the prediction confirmation circuit 421 to the selection circuit 42.
The output <Dl> of 2 is sent to the register 423 (
WR).

On the other hand, the branch instruction address <BOI> of the branch information register 419 (QIR3) is set to the instruction address register 411 (IAR) via the signal line 114. This address is the branch history table 4 corresponding to the branch instruction.
10 (LIHT) can be supplied as a write address to the table 410 via line 101 for updating. The output of the prediction failure signal 112 is provided to a flip-flop 425, and this output is provided to the table 401 via line 119 as an instruction pulse. In response to this output, branch prediction information for the next instruction preemption of the branch instruction is updated. In this embodiment, when predicted N0GO fails, this update is performed with a new branch destination address held in the register 423 (WR), and when predicted Go fails, the v bit is reset. However, it is not possible to catch up by using other methods to update the branch prediction information. When a prediction fails, all operations of instructions following the prediction side are canceled, and the new request address held in the register 423 (WR) is updated to the instruction address register 411 (IAR) after updating the branch history table 410 (BHT). is supplied to the CPU, and command retrieval is started again.

Referring to the first υth instruction, the instruction prefetch control circuit 424
is a flip-flop 1201, a truth/false circuit 1202-12
04 and an AND circuit 1205. The flip-flop 1201 receives the prediction failure signal 112.
It is a 7 lip-flop that can hold 1 machine cycle. The output of this circuit 424 is the address register 411
This is the selection instruction signal for the selector in the previous stage. This selection instruction signal is the output of the instruction address addition circuit 412,
A signal is provided to instruct which one of the output of the register 423, the output of the table 410, and the output of the branch information register 419 is selected. Under the control of the instruction prefetch control circuit 424, when the branch prediction is successful, the instruction processing shown in FIG. 16, which will be described later, is performed, and when the branch prediction fails, the instruction processing shown in FIG. 17, which will be described later, is performed. The instruction address addition circuit 11 is connected to the line 10.
When the BHT-1-LIT signal is not output through 6, an address is generated to prefetch the instruction on the branch N0GO side. At this time, since the address is added as a real address, for example, in a computer system that performs paging, if the address addition exceeds a page boundary, it is necessary to perform address conversion again. For this purpose, a page boundary crossing detection circuit is provided in the instruction address addition circuit 11. When the page boundary crossing occurs due to the detection circuit, the instruction address generation circuit 1
The instruction address generation circuit (IA) 401 and the instruction address conversion circuit (IT) restart the instruction preemption operation.
Control may be performed starting from step 402.

The problem here is which part of the existing instruction address information should be removed when newly registering the instruction address information in the branch history table BH'f'' 410.

This method uses LRU (Least &c
only Used) The order in which the information was entered, i.e.
FIFO (F
irst In First Out), but either one may be used.

Effects of the Invention Next, the effects of the invention will be explained in detail with reference to FIGS. 13 to 17.

Referring to FIG. 13, instruction processing is generally divided into the following eight processing units.

(1) IA stage: Instruction address of the instruction to be executed (
logical address) is generated.

(2) IT stage: Address translation of the generated instruction address is performed.

(3) l(j stage: The instruction is read from the storage device at the address of the converted instruction.

(4) If) Stage: The read instruction is decoded.

(5) OA stage: The operand address (logical address) of the decoded instruction is generated.

(6) OT stage: Address translation of the generated operand address is performed.

(7) 00 stage: The operand is read from the storage device at the converted real address of the operand.

(8) EX stage: Life is executed.

In the address translation of the IT stage and the OT stage described above, if an address translation buffer is provided and a necessary translation table exists in the address translation buffer, the address translation process can be executed at high speed. In addition, in the above-mentioned IC stage and OC stage instruction and operand read operations, a cache memory that holds a copy of part of the data in the main memory is provided, unless the necessary instructions and operands are present in the cache memory. Processing of the IC stage and OC stage can be performed at high speed. The information processing system does not necessarily have to have a release corresponding to each of the above-mentioned processing units. However, for the sake of simplicity, each processing unit is assumed to have a circuit that performs its function.

The high-speed processing of the IT, OT, and 10.00 stages described above makes it possible to perform eight-stage pipeline control that efficiently executes the processing flow of multiple instructions.

The instruction processing flow n including the branch instruction at this time will be explained with reference to FIGS. 14 and 15.

FIG. 14 shows the flow of instruction processing when all the branches mentioned above are predicted to be 'oo' in instruction prefetching of a branch instruction (in step 8). In other words, instructions A-Q are This is an instruction that determines the condition, and the branch condition is determined when the instruction AQ is executed, that is, at time t7.When the branch instruction BO is decoded at time t4, it uses the instruction address generation circuit to generate the branch destination instruction B1. , and thereafter operates to prefetch the B1 instruction.

Time t2. t3. and after the branch N0GO side at t4.
-Continuation instruction AI, A2. Then, address generation for instruction preemption of A3 is started. At times t6 and t7, subsequent instructions B2 and B on the branch GO side as predicted operations are executed.
The instruction preemption operation of No. 3 is started. Based on the branch condition determination result at time t7, processing continues from time t8 onwards according to the correct instruction processing flow.

In this case, the pipeline loss cycles due to the appearance of a branch instruction are: 3 cycles when the prediction is correct (branch GO) and 3 cycles when the prediction is incorrect (branch GO).
When branching (NOGO), it takes 3 cycles.

Branch GO rate γ When predicted accuracy rate α, in this case γ=
With α, the prediction accuracy is 5 minutes and 5 minutes. Therefore r-α
=05, and the average loss cycle for one branch instruction is 3×γ+3×(1−γ)=3 cycles.

On the other hand, FIG. 15 shows the flow of instruction processing when prediction is performed based on the past results of the same branch instruction described above in instruction prefetching of a branch instruction.

That is, the branch instruction BC is decoded at time t4, and the address table of the branch instruction is searched to determine whether it exists or not, or whether the instruction B1 on the branch Go side is preempted based on the prediction of the branch instruction flag, or whether the branch instruction B1 on the branch Go side is preempted or the branch N0 GO is executed. It is determined whether to pre-fetch the side instruction A1. Same as last time, time t2. At t3 and t4, 1. A2. Then, generation of a preemptive address for instruction A3 is started. At times t6 and t7, generation of addresses for subsequent instructions B1 and B2 or A4 and A5 of instruction prefetching based on prediction is started. Based on the branch condition determination result at time t7, processing continues from time t8 onwards according to the correct instruction processing flow. In this case, when the pipeline loss cycle due to the appearance of a branch instruction is predicted to be a branch GO and fails, 3 cycles branch N
When the prediction is 0(K) and it fails, it is 6 cycles. Therefore, branch Go rate γ = 0.5 Prediction accuracy rate α = 0
8, the average loss cycle for one branch instruction is 3・γ・α10・(1−γ)・α+3γ(1−α)+6
We get (1-γ)(1-α)=21 cycles.

Therefore, this conventional invention uses the principle that when prediction is made based on past results of the same branch instruction, a high prediction accuracy rate is obtained, and the process shown in FIG. 14 that always predicts a branch GO is performed. Some improvement can be seen in comparison. However, even with this improved invention, 3 loss cycles are still required in the case of a predictive intermediate branch GO, and pl cannot be reduced any further.

Therefore, if a branch instruction occurs, a loss cycle will occur even if the prediction is correct.

16 and 17 show the flow of instruction processing according to the present invention.

In addition to the function of reading instructions from the storage device, the instruction processing unit IC stage of the present invention indexes a branch history table and detects whether the address of the instruction to be read is registered in the branch history table. , if registered, the corresponding branch information is read, and if not registered, it has a function of generating a preemptive address for the subsequent instruction.

Referring to FIGS. 16 and 17, the operation of branch instruction BO at time t1 is performed as follows. First, the branch history table is indexed at the same time as the branch instruction Be is read from the instruction cache memory. If the instruction address of the branch instruction BO is registered, the corresponding branch information is read. As a result of the analysis with this branch information, the instruction prefetch of the branch destination instruction B1 is started based on the branch destination address included in the branch information as a prediction on the branch GO side, or the branch N0() (branch as a prediction on the J side) N0
It is determined whether to generate an instruction address for the instruction A1 on the GO side and start prefetching the instruction A1. Thereafter, at time t5j, a subsequent instruction on the prediction side is preempted during the prediction period of the branch instruction BC, and the branch condition is determined at time t5. When the prediction is correct, the processing continues without any disturbance in the flow of the pipeline, as shown in FIG. When prediction fails, the branch history table is updated at time t6, as shown in FIG. 17, and then the instruction is taken out from the correct instruction flow. In this case, the pipeline loss cycles due to the appearance of a branch instruction are O cycles when the prediction is correct and 5 cycles when the prediction fails. In this case, since not only the branch direction but also the branch destination address is predicted, the prediction accuracy rate α is slightly lower than when predicting only the branch direction, but the ratio is insignificant. Therefore, assuming the prediction accuracy rate α=08, the average loss cycle per branch instruction is 0·α+5·(1−α)=1 cycle, which is a significant improvement over the prior art.

In this invention, a branch history table that stores the address of a branch instruction and branch information including the address of the branch instruction and the branch destination address of the branch instruction as a pair is indexed when an instruction is prefetched. By subsequently causing the next instruction to be prefetched at the branch destination address, the instruction word can be prefetched according to the description in the branch history table without decoding the instruction. As a result, only when the description in the branch history table is correct, a queue of instructions is formed in the instruction buffer according to the instruction execution path, and branch instructions are executed in pipeline control of the information processing system. This has the advantage that it can be performed without an IO cycle.

Furthermore, in the present invention, a branch history table that stores a plurality of pairs of branch information including the address of a branch instruction and information specifying the branch destination address of the branch instruction is configured with a set assomiasi type memory. This has the advantage that it is possible to realize a branch bistry table consisting of a memory with a large capacity.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the detailed structure of a branch history table, FIG. 3 is a diagram showing the storage format of the storage units 501 and 601 in FIG. 4 shows a detailed configuration of the test circuits 503-506 in FIG. 2, FIG. 5 shows a command word configuration, and FIG. 6 shows a detailed configuration of the priority circuit 507 in FIG. 2. , FIG. 7 is a diagram showing the storage format of the registers 417 to 419 in FIG. 1, FIG. 8 is a diagram showing the detailed configuration of the prediction confirmation circuit 420 in FIG. FIG. 10 is a diagram for explaining the correspondence between instructions in the circuit 408 and branch information in the branch history table 410. FIG. 10 is a diagram for explaining the instruction preemption operation by the table 410 in FIG. 9. FIG. 11 is a diagram for explaining the prediction. 12 is a diagram showing the detailed configuration of the instruction prefetch control circuit in FIG. 1. FIG. 13 is an overview of the instruction processing flow. Figures 14 and 1
FIG. 5 is a diagram showing the flow of instruction processing using the conventional prediction method, FIG. 16 is a diagram showing the flow of instruction processing when the prediction of a branch instruction is correct in the present invention, and FIG. FIG. 2 is a diagram showing the flow of instruction processing when prediction of a branch instruction fails in accordance with the second embodiment of the present invention. 1 to 17, 401...instruction address generation circuit, 402...instruction address conversion circuit, 40
3... Instruction decoding circuit, 404... Operand address generation circuit, 405... Operand address conversion circuit, 406... Operand reading circuit, 407... Instruction execution circuit, 408... Instruction storage circuit, 409...
Instruction buffer, 410...Branch history table' (
BHT), 411...Instruction address register (IAR
), 412... instruction address addition circuit, 413...
Branch information buffer, 414...Instruction alignment circuit, 415
... Branch information switching circuit, 416... Branch information register (Qao), 417... Branch information register (QRt
), 418...Branch information register (QR2), 419
...Branch information register (QR3), 420...Prediction confirmation circuit, 421...Address generation circuit, 422...
・Selection circuit, 423...Register (VvR), 424
...Instruction prefetch control circuit, 425...Flip-flop, 501.502...Storage unit, 503, 504,
505, 506... Test circuit, 507... Priority circuit, 508... Selection circuit, 509... OR circuit. Agent Patent Attorney Susumu Uchihara 41 402 Mouth 1f Figure 12 Figure 13 l2I) l fol it l l2I ta1tφ1mm1t1
Drink 71t-a + Fig. 14 1folix Otsu 21t31 t41 and 1h177It
a1to tt t2 /:, 3 t4ts
tbX″-＼ 8/ Af 1i21t311-411-51 Otsu'j7' L
8' ``[ Low S Figure 17

Claims (1)

[Scope of Claims] Branch history table means for storing a plurality of pairs of information specifying the address of a branch instruction and branch information including information specifying the branch destination address; Checking means for checking whether information specifying the address of a branch instruction to be preempted in the instruction prefetching multiple operation is registered in the branch history table means, and in response to the confirmation of the registration by the checking means. control means for reading out branch information corresponding to the branch instruction to be preempted from the branch history table means and controlling to start the next instruction prefetching operation according to the branch information; , a directory storage means that has a predetermined number of sets and a predetermined number of levels and holds a part of instruction addresses of branch instructions, and a data storage means that stores branch information corresponding to the storage contents of the directory storage means. An instruction prefetching device having a set associative branch history table.