JPS6324421A - Information processor - Google Patents

Abstract

PURPOSE:To reduce an idle time occurring in the respective parts in an information processing device and to improve the speed of executing an instruction at the time of executing a condition branch instruction by providing a condition branch forecasting part executing the forecasting of branch direction with the kind of the branch instruction and a branch distance as inputs. CONSTITUTION:During the execution of a program if the condition branch instruction is set in an instruction register 3, the condition of the branch and the value corresponding to the branch distance are respectively outputted from a condition branch recognition part 4 and from a branch distance recognition part 5 and inputted in a condition branch forecasting part 6. The condition branch forecasting part 6 executes the forecasting of the branch of condition branch instruction from given information and outputs the result to an instruction first fetch part 2. If the forecasting of branch direction is a branching direction, the instruction first fetch part 2 executes the fetch of a instruction code from a branching destination. If the forecasting of the branch direction isn't branching direction the instruction first fetch part 2 executes the fetch of the instruction code from the next instruction to the condition branch instruction. Therefore the condition branch instruction can be speedily executed with a few hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an information processing device that performs instruction prefetching, and in particular, to a branch direction prediction of a conditional branch instruction that is performed in order to effectively execute instruction prefetching. The present invention relates to an information processing device realized with less hardware.

(Prior Art) In general, an information processing device executes a program by performing the following operations for each instruction: fetching an instruction code (hereinafter referred to as instruction fetch), decoding the instruction code (hereinafter referred to as instruction decoding), and executing the instruction. ing. Some instructions also require operations such as accessing an operand from main memory (hereinafter referred to as operand read) or writing back the instruction execution result to main memory (hereinafter referred to as operand write).

In these information processing devices, a main memory control unit performs instruction fetch, operand read, and operand write, an instruction decode unit performs instruction decoding, and an instruction execution unit performs instruction execution. Since these operations are divided and processed by each part within the information processing device, it is possible to overlap and perform these operations in parallel for several consecutive instructions. Focusing on this point, in order to execute instructions at high speed, it is widely practiced to control the operations of several instructions to be processed in parallel. This is called pipeline control, and an information processing device that performs this kind of control is called a pipeline type information processing device.

In order to perform high-speed processing in a pipelined information processing device, each part within the device needs to operate in parallel. However, with conditional branch instructions, it cannot be determined whether the branch condition has been met and the branch has been executed until the previous instruction finishes executing and a valid value is set in the condition code.
The instruction following the conditional branch instruction cannot be fetched or coded. As a result, each unit within the information processing apparatus has idle time, which hinders improvement in instruction execution speed.

In order to solve this problem, we have proposed a method that predicts the branch direction from the branch direction of the conditional branch instruction and determines the preemption direction of the instruction, and a method that retains history information of branch instructions in the information processing device and uses this information as a base. A method for controlling the direction of command prefetching has been proposed.

(Problems to be Solved by the Invention) In order to improve the processing speed of a pipelined information processing device, Zhao Ma said that the prediction accuracy of the conditional branch instruction prediction method, which determines the instruction prefetch direction from the branch direction, is low. there were. Furthermore, the method based on branch instruction history information has the disadvantage of requiring a large amount of hardware to perform complex processing.

(Means for Solving the Problems) In order to solve the above-mentioned advantages, the information processing device according to the present invention includes a conditional branch prediction unit that predicts the branch direction using the type of branch instruction and branch distance as input. By doing so, it is possible to accurately predict the direction of a conditional branch with less hardware and determine the direction of instruction prefetching.

(Operation) The basic configuration of the present invention is shown in FIG. In FIG. 1, when a conditional branch instruction is set in the instruction register 3 during program execution, the conditional branch recognition unit 4 outputs the branch condition, and the branch distance recognition unit 5 outputs a value corresponding to the branch distance. , this is manually input to the conditional branch prediction unit 6. The conditional branch prediction section predicts a branch of a conditional branch instruction based on the given information, and sends this result to the instruction prefetch section 7. If this branch direction prediction is a branch direction, the instruction prefetch unit 7 fetches the instruction code from the branch destination. Further, if the branch direction prediction is in the direction of not branching, the instruction prefetch unit 7
Fetch the instruction code from the instruction following the conditional branch instruction.

By performing such control, it is possible to reduce the idle time that occurs in each part of the information processing device when executing a conditional branch instruction, thereby improving the instruction execution speed.

(Example) In this example, the inside of an information processing apparatus is divided as shown in FIG. 2 and explained. In the figure, the main memory control unit 12 is a part that accesses the main memory, and the instruction prefetch unit 2
has inside. Some information processing devices have a memory management mechanism or cache memory inside the main memory control unit 12. The instruction decoder 13 is a part that decodes instructions, and includes a conditional branch recognition section 4, a branch distance recognition section 5, and a conditional branch prediction section 6.
has inside. The instruction execution unit 14 is a part that executes instructions.

FIG. 3 is a diagram showing the configuration of the instruction decoder 13 in this embodiment. In the figure, a conditional branch instruction determination unit 20 located inside the conditional branch recognition unit 4 is a part that determines whether the instruction code stored in the instruction register 3 is a conditional branch instruction, and a gate 21 is a part that determines whether the instruction code stored in the instruction register 3 is a conditional branch instruction. This section outputs a branch condition to the conditional branch prediction section when the instruction code stored in the instruction register 3 is determined by the section 20 to be a conditional branch instruction. The negation unit 22 located inside the branch distance recognition unit 5 performs logical negation on each bit of the branch distance, the selector unit 23 outputs one of two inputs, and the FF1 unit 24 performs logical negation on each bit of the branch distance. This is the part that searches from the most significant bit of the first bit and outputs the position of the bit where 1 is found first in binary form. Conditional branch prediction f+! Branch prediction table 2 located inside part 1 6
Reference numeral 5 denotes a 1-bit memory that outputs branch prediction according to branch conditions and branch distances input as addresses.

FIG. 4 is a diagram showing the instruction format of a conditional branch instruction in the information processing apparatus described in this embodiment. In the figure, the instruction code 31 has 8 bits, of which the upper 4 bits are a value 32 indicating that it is a conditional branch instruction, and the lower 4 bits are a value 33 indicating the condition for branching. Further, the branch distance is expressed as a two's complement number, and the most significant bit is the sign bit 35.

First, a procedure for executing a normal command in the information processing apparatus in this embodiment will be described.

The instruction code stored in the main memory 11 is retrieved via the main memory access bus 15 by the main memory control unit 12 controlled by the instruction prefetch unit 2.
Instruction register 3 in instruction decoder 13 through bus 16
sent to. The instruction decoder 13 decodes the instruction code set in the instruction register 3, and sends the address of the operand handled by the next instruction to be executed and the distinction between read and write of the operand to the main memory control unit 12 via the address bus 17. At the same time, information regarding the operation performed by the instruction is sent to the instruction execution unit 14 via the instruction decode result bus 18.
send to The main memory control unit 12 accesses the operand address sent from the instruction decoder 13 through the main memory bus 15 for the operand to be read, and prepares the operands necessary for executing the next instruction. Instruction execution unit 1
4, the operand prepared by the main memory control unit 12 is retrieved through the data bus 19 and used to execute the operation j specified by the instruction through the instruction decode result bus 18. Main memory 11
When it is necessary to store the result in the main memory controller 12, the execution result is sent to the main memory controller 12 via the data bus 19. In the main memory control unit 12, when an operand that needs to be written is sent from the instruction execution unit 14, it is stored in the position specified by the operand address sent from the instruction decoder 13 in advance.
This operand is written through the main memory bus 15.

If the instruction to be executed is a branch instruction, the instruction decoder 13 sends the branch destination address to the main memory controller 12 via the address bus 17. The main memory control unit 12 performs a branch by fetching an instruction from a branch destination address.

Next, a procedure for predicting the branch direction of a conditional branch instruction using this information processing device will be described.

The upper 4 bits of the instruction register 3 are used by the conditional branch judgment unit 20.
When the conditional branch instruction 30 shown in FIG.
Since the output of the instruction register becomes valid, the lower four bits of the instruction register become the output of the conditional branch recognition section 4 through the gate 21.

When the output of the conditional branch instruction determination unit 20 is invalid, the output of the conditional branch recognition unit 4 is invalid.

A field representing the branch distance in the instruction register 3 is input to the branch distance recognition section 5. When the sign bit 35 of the branch distance is O, it represents a positive branch distance, and when the sign bit 35 is 1, it represents a negative branch distance. This sign bit 35 controls the selector section 23. That is, when the sign bit 35 is 0, the branch distance field is input to the FF1 section 24, and when the sign bit is 1, each bit of the field indicating the branch distance is inverted by the negator 22 and input to the FF1 section 24. The selector unit 23 switches to input the data. The FF1 unit 24 searches from the most significant bit and outputs the bit position where 1 is found first. By this operation, the effective bit length of the branch distance is output from the FF1 section 24, and is output from the branch processing recognition section 5 together with the sign bit 35.

In the branch prediction table 25 inside the conditional branch prediction unit 6, values indicating the effective bit length of the branch condition sent from the conditional branch recognition unit 4 and the branch distance sent from the branch distance recognition unit 5 are input as addresses. In this table, conditional branch prediction is set based on branch conditions and effective bit lengths of branch distances from previously investigated branch characteristics. A predicted result is defined to take effect when a branch is predicted to occur in a conditional branch instruction. When the value indicating the branch condition sent from the conditional branch recognition unit 4 is valid, the prediction result is output from the branch prediction table 25. When the input from the conditional branch recognition unit 4 is invalid, the output from the branch prediction table 25 is also invalid. The output from the branch prediction table 25 is sent to the instruction prefetch unit 2 as the output of the conditional branch prediction unit 6.

Therefore, whether the prediction result 7 sent to the instruction prefetch unit 2 is valid or invalid has the following meanings.

Prediction result 7 is valid: The instruction stored in the instruction register 3 is a conditional branch instruction, and a branch is expected to occur with this branch instruction.

Prediction result 7 is invalid: The instruction stored in the instruction register 3 is not a conditional branch instruction, or it is predicted that a branch instruction will not branch.

The instruction prefetch unit 2 controls the main memory control unit 12 to start fetching instructions from the branch destination address sent through the address bus 17 when the prediction result 7 output from the conditional branch prediction unit 6 is valid. Further, when the prediction result 7 output from the conditional branch prediction unit 6 is invalid, the main memory control unit 12 is controlled to fetch a subsequent instruction.

By performing such control, in a conditional branch instruction that is expected to take a branch, it is possible to fetch an instruction code before the branch is taken.

(Effects of the Invention) In the information processing device according to the present invention, it is possible to predict a conditional branch instruction using less hardware than a method of predicting a branch based on history information of branch instructions. Also,
This method allows for more accurate prediction than a method that performs branch prediction based on the branch direction. Therefore, it is possible to configure an information processing device that can execute conditional branch instructions at high speed with less hardware.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the components of the present invention, FIG. 2 is a diagram showing the configuration of an information processing apparatus in an embodiment of the present invention, and FIG. 3 is a diagram showing the configuration of an instruction decoder in an embodiment of the present invention. FIG. 4, a diagram showing the configuration, is a diagram showing an instruction format of a conditional branch instruction in an information processing apparatus according to an embodiment of the present invention. In the figure, 2... Instruction prefetch unit 3... Instruction register 4... Conditional branch recognition unit 5... Branch distance recognition unit 6... Conditional branch prediction unit 7... Prediction result 1
0... Processor 11... Main memory 12
...Main memory control unit 13...Instruction decoder 14...Instruction execution unit 15...Main memory access bus 16...Instruction code bus 17...
Address bus 18...Instruction decode result bus 19
...Data bus 20...Conditional branch judgment section
21...Gate 22,...Negation part 2
3...Selector section 24...FF1 section 25
...Branch prediction table 30, 2-condition branch instruction
31.・Instruction code 32...Value 33 indicating that it is a conditional branch...Value 34 indicating the condition for branching...Branch distance 35...Sign bit. -One. l'

Claims (1)

[Claims] In an information processing device that has an instruction prefetch unit that prefetches instructions and an instruction register for storing instructions, it receives the instruction stored in the instruction register as input, recognizes that this is a conditional branch instruction, and outputs the branch condition. A conditional branch recognition unit that inputs the instruction stored in the instruction register and outputs a value corresponding to the branch distance, a branch distance recognition unit that inputs the instruction stored in the instruction register, and determines the branch direction based on the output from the conditional branch recognition unit and branch distance recognition unit. Information characterized in that the instruction prefetching section controls the direction in which instructions are prefetched by having a conditional branch prediction section that predicts the conditional branch prediction section, and inputs the prediction result output from the conditional branch prediction section to the instruction prefetching section. Processing equipment.