JP2591325B2 - Branch control device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a branch processing device that executes a conditional branch instruction, a subroutine call instruction and a subroutine return instruction at high speed, and combines a parallel decoding of two instructions and a preceding branch control. Technology.

2. Description of the Related Art In order to speed up processing by parallel decoding, a conventional apparatus employs a method in which two instruction decoders are provided, two instructions are decoded in parallel, and two arithmetic units are operated simultaneously. For example, in Japanese Patent Application Laid-Open No. 63-49843, two instructions, an arithmetic operation and a logical operation, are decoded by independent first and second decoders, respectively. The operation speeds up the processing. The present invention relates to parallel decoding in a fixed word length instruction system having a fixed instruction code length.
JP-A-63-198226 and JP-A-1-28184 disclose a method of parallel decoding of two instructions in a variable word length instruction system in which the length of an instruction code changes depending on the type of operation and the addressing mode. . In Japanese Patent Application Laid-Open No. 63-198226, the possibility of parallel decoding is detected in advance, and if a conditional branch instruction does not branch, the instruction following the instruction is decoded in parallel. This speeds up the processing of the conditional branch instruction when the condition is not satisfied. Also, JP-A-1-28
In No. 184, the possibility of parallel decoding is also detected in advance, and a load instruction or a store instruction and a subsequent instruction are decoded in parallel. This speeds up processing of a load instruction or a store instruction.

Problems to be Solved by the Invention Parallel decoding in a fixed word length instruction system is easy because the starting position of the instruction following the instruction being decoded is fixed. Therefore, parallel decoding of two instructions is possible only by adding one second instruction decoder for decoding the subsequent instruction. However, in order to suppress an increase in the number of decryption hardware, it is necessary to determine in advance the sharing of instructions to be decrypted by the respective decryptors, so that the decryption hardware does not overlap in each decryptor. However, if the assignment of instructions to be decoded by the two decoders is determined, the amount of hardware of the decoder is reduced, but it becomes necessary to code schedule so that two types of instructions are supplied to the respective decoders. There is a problem that the load on the compiler increases.

In the variable word length instruction system, since the starting position of the instruction following the instruction being decoded is determined by the instruction currently being decoded, to decode two instructions in parallel, the instruction word following the instruction being decoded is used in parallel. A plurality of second decoders for decoding are provided, or a selector for selecting a command word to be input to the second decoder is provided, and the selector is controlled based on the decoding result of the first command decoder. To determine the input of the command decoder. Therefore, there has been a problem that the hardware of the decoder increases and the time required for decoding increases. In addition, by the method of detecting the possibility of parallel decoding in advance, even if the conditional branch instruction and the subsequent instruction in the case where the condition is not satisfied are decoded in parallel, the conditional branch instruction is not executed if the condition of the conditional branch instruction is satisfied. There was a problem that processing could not be performed at high speed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a branch control device that performs parallel decoding of two instructions in a variable word length instruction system without significantly increasing decoding hardware and speeds up processing when a condition of a conditional branch instruction is satisfied. That is. Still another object is to provide a branch control device in which processing of a subroutine call instruction and a subroutine return instruction is accelerated.

Means for Solving the Problems To achieve the above object, in the branch control device of the present invention, an instruction supply means for fetching an instruction prior to execution and supplying the instruction to a decoding unit, and a plurality of instructions supplied by the instruction supply means An instruction register that holds the instruction code of the instruction register, an instruction decoder that decodes the instruction code stored at the head of the instruction register, and a specific comparison instruction included in the instruction code following the instruction code stored at the head. Instruction detecting means for detecting the presence of a specific branch instruction, a branch destination address calculating means for calculating a branch destination address from an instruction code stored in the instruction register, and an instruction length of the instruction decoded by the decoder. And a detection result of the command detection means,
Precedent branch control means for storing and controlling the next instruction in the instruction register; return address storage means for storing the return address of the subroutine; adder for updating the stack pointer; and return destination output by the return address storage means A comparator for comparing the address with the return address read from the stack.

Operation The present invention speeds up the processing of a conditional branch instruction without significantly increasing the number of decoding hardware in the variable word length instruction system, and sets the execution clock to zero when the condition is satisfied. Also, the subroutine call instruction and the subroutine return instruction are each processed in one clock.

FIG. 1 is a block diagram showing a configuration of a decoding unit of a branch control device according to an embodiment of the present invention. In the figure, 100
Is an instruction supply means for supplying instructions prior to execution, and comprises an instruction cache 101 for performing high-speed instruction fetch and an instruction buffer 102 for temporarily storing instructions read from the instruction cache. An instruction register 103 stores an instruction sequence to be decoded, and stores an instruction word four times as long as a continuous basic word length among instruction words output by the instruction supply means. 104
Is an instruction decoder for decoding the instruction code stored at the head of the instruction register 103. 105 is the instruction register 103
Instruction detection means for detecting the presence of a specific comparison instruction and a specific branch instruction in the instruction code following the instruction code stored at the beginning of the instruction code. It consists of 107 and 108. Reference numeral 109 denotes a branch destination address calculating means for calculating a branch destination address 118 from the instruction code stored in the instruction register 103, and a program counter 129 for holding the start address of the instruction being decoded by the instruction decoder 104; Of the instruction code stored in the instruction register 103 and the lower bits of the instruction code stored in the instruction register 103.
0, 111, 112, 113, an adder 114 for adding 1 to the upper bit of the program counter 129, and a program counter 1
A subtractor 115 for subtracting 1 from the upper 29 bits, and a selector for selecting one of the addition results of the adders 110 and 113
116, the upper bits of the program counter and the adder 1
14 and a selector 117 for selecting one of the calculation results of the subtractor 115. A plurality of adders 110 and 113 further have 0 and 3 respectively according to the position of the instruction word to be added.
Add the offset value of 119 is a preceding branch control means, which is instruction length data 120 of the instruction decoded by the decoder 104.
And the detection results 121, 122 and 123 of the instruction detecting means 105, control the storage of the next instruction in the instruction register by the next instruction control signal 124, and
Thus, a correct branch destination address is selected from a plurality of branch destination address candidates. A selector 126 selects an instruction read address, and selects one from a prefetch counter 127, a branch destination address 118, and a return destination address 128 at the time of executing a subroutine return instruction.

FIG. 2 is a block diagram showing a configuration of an execution unit of the branch control device according to one embodiment of the present invention. In the figure, 200
Is a return address storage means, and the return address calculated by the ALU 201 when the subroutine call instruction is executed.
202 is stored in a first-in last-out buffer, and the last stored return address 203 is always output. Reference numeral 204 denotes a comparator, which compares the return address 203 output by the return address storage means 200 with the return address 205 read from the memory at the time of executing the subroutine return instruction, and determines whether or not both match. Is output to the return address match signal 206. An adder 207 adds the data stored in the general-purpose register (GR) 208 to an address deviation (disp) or a constant (const) of the instruction, and outputs an effective address 209. 210 is the program counter, 21
1 is a constant generator for generating a constant. 212, 213, and 214 are read pulses of the general-purpose register 208, respectively.
216 are write buses to the general-purpose register 208, respectively.
217 and 218 are selectors for selecting bus data. twenty one
Reference numeral 9 denotes a bus control unit which inputs and outputs data such as a return address between the external memory and the execution unit.

FIG. 3 is an instruction code configuration diagram of a variable word length instruction system handled by the branch control device of the present invention, and shows, as an example, a code of a conditional branch instruction. As shown in the figure, the instruction has a basic word length (16
), And in the case of a conditional branch instruction, there are instructions with a length of one to three words depending on the length of the deviation. The conditional branch instruction whose speed is increased by the embodiment of the present invention is a conditional branch instruction (Bcc: d8) having a basic word length of 8 bits.

FIG. 4 is a diagram showing the structure of an instruction code detected by the instruction detecting means in the embodiment of the present invention. 4 instructions to detect
There are several types: comparison instruction (CMP), conditional branch instruction (Bcc), subroutine call instruction (BSR), and subroutine return instruction (RTS), all of which are basic word length instructions. In the figure, OP is an operation code, R1 is a first operand of a comparison instruction, EA is an effective address specification, condition is a condition of a conditional branch, and disp8 is an 8-bit address deviation.

FIG. 5 is an instruction flow diagram that defines the sequence of instruction sequences to be executed, and is used in the description of the operation. In the figure, (a) shows an instruction flow of a conditional branch instruction, (b) shows an instruction flow of a subroutine call instruction, and (c) shows an instruction flow of a subroutine return instruction.

FIG. 6 is an explanatory diagram of the state of the instruction register when the condition is satisfied during execution of the conditional branch instruction.
The state at the time of decoding the instruction, the state at the time of decoding the CMP instruction, and the state at the time of decoding the B1 instruction are shown. In this embodiment, it is assumed that the A0 instruction, which is an instruction immediately before the CMP instruction, has a length of 1 to 2 times the basic word length. This is because the instruction register is limited to four words, and the method of the present invention is not limited.

FIG. 7 is an explanatory diagram of the state of the instruction register when a subroutine call instruction and a subroutine return instruction are executed.
(A) is a case of a subroutine call instruction, and shows a state at the time of decoding the A0 instruction, a state at the time of decoding the BSR instruction, and a state at the time of decoding the B1 instruction in order from the top. (B) shows the case of a subroutine return instruction, which shows, from the top, a state at the time of decoding the A0 instruction, a state at the time of decoding the RTS instruction, and a state at the time of decoding the B1 instruction. As in FIG. 6, this is the instruction immediately before each instruction.
The A0 instruction handles one to two times the basic word length.

FIG. 8 is a pipeline flow diagram in the case where the condition of the conditional branch instruction is satisfied and the branch is taken. In the figure, IF is an instruction fetch stage, D1 and D2 are instruction decoding stages, R is a register read stage, EX is an execution stage, and W is a register write stage. The number of stages and the configuration of the pipeline are those in one embodiment of the present invention, and the system of the branch control device of the present invention is not limited.

Hereinafter, the operation when a conditional branch instruction is executed in one embodiment of the present invention will be described mainly with reference to FIG.

<Timing 1> The A0 instruction is at the head of the instruction register 103 and the instruction decoder 1
04 decodes the A0 instruction. At this time, the state of the instruction register is as shown in "A0 instruction decoding" in FIG. 6, and the CMP instruction and the Bcc instruction subsequent to the A0 instruction are the instruction detection means 10 respectively.
Detected by 5. At the same time, branch destination address calculation means 1
In step 09, the candidate of the branch destination address of the conditional branch instruction is calculated from the lower 8 bits of each instruction word in the instruction register.

<Timing 2> Based on the instruction word length information 120 of the A0 instruction decoded at the timing 1 and the detection results 121, 122 and 123 of the instruction detecting means, the preceding branch control means 119 determines the head of the CMP instruction and determines the next instruction control signal. The instruction register 103 and the instruction buffer 102 are controlled by the instruction register 124, and the instruction register is brought into the state of "when the CMP instruction is decoded" in FIG. At the same time, a correct branch destination address is selected by the selector 126 from the branch destination address candidates calculated at the timing 1 by the branch destination address control signal 125 and input to the instruction supply means 100. At timing 1, since the instruction detecting means detects that the conditional branch instruction is stored in the instruction register, the instruction decoder 104 outputs, as a control signal, the result of decoding the comparison instruction and the conditional branch instruction in parallel. However, decoding of a conditional branch instruction merely outputs a condition code to a control signal to indicate that it is valid, and does not mean that an instruction decoder inputs and decodes the code of a conditional branch instruction. The instruction supply means 100 fetches the instructions B0 and B1 at the branch destination from the input branch destination address, and stores them in the instruction buffer 102. The instruction buffer saves instructions following the A1 instruction to an internal buffer in case the condition of the conditional branch is not satisfied. In this embodiment, the processing proceeds assuming that the conditional branch is a branch. If the execution does not result in a branch, the pipeline at that time is invalidated, and the pipeline processing is performed again from the decoding of the A1 instruction.

<Timing 3> The instruction register enters the state of “when the B1 instruction is decoded” in FIG. 6, and the instruction decoder decodes the B1 instruction. Instruction supply means
The instruction following the B2 instruction is fetched before the
It is omitted in the timing chart of FIG.

<Timing 4> The execution unit reads the operands required for the comparison instruction from the general-purpose register 208, and reads out the ALU 201 through the read buses 212 and 213.
To supply. At this time, the ALU is performing the operation of the A0 instruction.

<Timing 5> The read operands are compared, and it is determined whether or not the comparison result matches the condition of the conditional branch. This comparison is performed by dedicated hardware added to the ALU.
If the result of the determination is that the conditions match, the execution of the B1 instruction whose operand is being read at this time is calculated at the next timing. As a result of the determination, if the conditions do not match, as shown in FIG. 9, all the pipeline executions after the B1 instruction are canceled, and the decoding of the A1 instruction saved in the instruction buffer is started.

As described above, the branch control device of the present invention executes the conditional branch instruction at 0 clock when the following comparison instruction and the conditional branch instruction are present in the instruction register during the decoding of the A0 instruction and the conditions match. . If the conditions do not match, as shown in FIG. 9, the processing is executed with three clocks.
However, in the pipeline of this embodiment, since there are two decoding stages and a register reading stage is provided, it takes three clocks when the condition is not satisfied. However, when the number of pipeline stages is reduced, the condition is not satisfied. But one
It is possible to go down to the clock.

FIG. 10 and FIG. 11 are pipeline flow diagrams showing the operation when the condition is satisfied when the detection of the conditional branch instruction is delayed. The detection delay occurs when there is no instruction after the comparison instruction in the instruction register while decoding the A0 instruction. FIG.
FIG. 9 is a pipeline flow diagram when detection is delayed by one cycle, and is the same as the operation in FIG. 8 except that the calculation of the branch destination is delayed by one cycle. FIG. 11 is a pipeline flow diagram when the detection is delayed by two cycles. The comparison instruction and the conditional branch instruction cannot be detected during the decoding of the A0 instruction, and the conditional branch instruction cannot be detected during the decoding of the comparison instruction. Happens if not. In this case, the branch destination calculation is delayed by two cycles, and the branch determination is also delayed by one cycle. Therefore, the execution time when the condition is not satisfied is one cycle longer than that in FIG.

Next, the operation of the subroutine call instruction and the subroutine return instruction will be described. FIG. 12 is a pipeline flow diagram when a subroutine call instruction is executed, and WB indicates a writing stage to a memory.

<Timing 1> As in the case of the conditional branch instruction, the A0 instruction is at the head of the instruction register, and the instruction decoder 104 decodes the A0 instruction. At this time, the state of the instruction register is as shown in "A0 instruction decoding" in FIG. 7A, and the BSR instruction following the A0 instruction is detected by the instruction detecting means 105. At the same time, the branch destination address calculating means 108 calculates a candidate for a branch destination address of the subroutine call instruction from the lower 8 bits of each instruction word in the instruction register.

<Timing 2> Based on the instruction word length information 120 of the A0 instruction decoded at the timing 1 and the detection results 121, 122, 123 of the instruction detecting means, the preceding branch control means 119 determines the head of the BSR instruction and determines the next instruction control signal. The instruction register 103 and the instruction buffer 102 are controlled by 124, and the instruction register is set to "when the BSR instruction is decoded" in FIG. 7 (a).
State.

<Timing 3, Timing 4> Timing 3 and timing 4 are the same as in the case of the conditional branch instruction. However, at timing 4, the stack pointer and the program counter are read as the operation operands of the BSR instruction through the read buses 214 and 212, respectively.
Input to LU201.

<Timing 5> The adder 207 calculates the address of the stack that stores the return destination, and outputs the effective address 209. The ALU 201 calculates and outputs a return address 202 from the value of the program counter and information on the instruction length of the subroutine call instruction.

<Timing 6> The bus control unit 219 writes the return address to the effective address (the address indicated by the updated stack pointer). The return address storage means 200 stores the return address 202
Is stored in the internal buffer. The updated stack pointer value is written to the general-purpose register 208 via the write bus 215.

As described above, the subroutine call instruction is executed in one clock when the subsequent subroutine call instruction is present in the instruction register while the A0 instruction is being decoded. FIG. 13 is a pipeline flow chart when the detection of the subroutine call instruction is delayed by one cycle, and the branch destination address is calculated during the decoding of the subroutine call instruction.

FIG. 14 is a pipeline flow diagram when the return address of the return address storage means is correct when the subroutine return instruction is executed, and OF indicates a fetch stage of a memory operand. The operation will be described below at each timing.

<Timing 1> As in the case of the conditional branch instruction, the A0 instruction is at the head of the instruction register, and the instruction decoder 104 decodes the A0 instruction. At this time, the state of the instruction register is as shown in "A0 instruction decoding" in FIG. 7B, and the RTS instruction following the A0 instruction is detected by the instruction detecting means 105.

<Timing 2> The preceding branch control means 119 selects the last stored return address 203 output from the return destination storage means 200 by the selector 126 and inputs it to the instruction supply means 100. The instruction supply means 100 fetches a return instruction based on the address.

<Timing 3, Timing 4> Timing 3 and timing 4 are the same as in the case of the conditional branch instruction. However, at timing 4, the stack pointer is input to the adder 207 through the read bus 214 as the operation operand of the RTS instruction.

<Timing 5> The adder 207 updates the stack pointer
Performs an operation for the data length of the return address and performs write bus 21
Output to 5. At the same time, the selector 217 selects the data of the stack pointer read to the read bus 214 and outputs it to the address 209 as an effective address.

<Timing 6> The bus control unit 219 fetches the return address 205 from the effective address (the address indicated by the stack pointer before updating). The updated stack pointer value is
The data is written to the general-purpose register 208 through the write bus 215. The comparator 204 compares the return address 203 output by the return destination storage means 200 with the return address 205 fetched by the bus control means, and outputs a match determination result to 206. If both addresses match as a result of the comparison, the return instruction is executed immediately after the return subroutine instruction as shown in FIG. If they do not match, as shown in FIG. 15, all subsequent pipelines are canceled, and the pipeline is restarted from the instruction fetch by the return address fetched by the bus control means. In this case, the execution unit replaces the return address 203 output from the return address storage means with a correct return address fetched by the bus control means and inputs the correct return address to the instruction supply means.

As described above, when the subsequent subroutine return instruction is present in the instruction register while the A0 instruction is being decoded and the return destination of the return destination storage means is correct, the subroutine return instruction is executed in one clock.

Effect of the Invention As described above, according to the present invention, it is possible to provide an instruction detecting means, a preceding branch control means, and a branch destination address calculating means to calculate a candidate of a branch destination address while decoding an instruction immediately before a comparison instruction. Thereby, two instructions of the comparison instruction and the conditional branch instruction can be decoded in parallel, and the processing of the conditional branch instruction can be speeded up without using hardware such as a branch prediction mechanism.
Further, by providing the return address storage means and the comparison means, the processing of the subroutine call instruction and the subroutine return instruction can be speeded up.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a decoding unit of a branch control device according to an embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of an execution unit of the branch control device according to an embodiment of the present invention. FIG. 4 is a diagram showing an instruction code configuration of a variable word length instruction system handled by the branch control device of the present invention, FIG. 4 is a diagram showing an instruction code configuration detected by an instruction detecting means in the embodiment of the present invention, and FIG. FIG. 6 is an instruction flow diagram defining the sequence of instruction sequences to be executed, FIG. 6 is an explanatory diagram of an instruction register at the time of execution of a conditional branch instruction, and FIG. 8, FIG. 8 is a pipeline flow diagram when the condition of the conditional branch instruction is satisfied and the branch is taken, and FIG. 9 is a pipeline flow diagram when the condition of the conditional branch instruction is not satisfied and the branch is not taken. FIG. 0 is a pipeline flow diagram when the detection of a conditional branch instruction is delayed by one cycle, FIG. 11 is a pipeline flow diagram when detection of a conditional branch instruction is delayed by two cycles, and FIG. 12 executes a subroutine call instruction. FIG. 13 is a pipeline flow diagram when the detection of a subroutine call instruction is delayed by one cycle, and FIG. 14 is that the return address of the return address storage means is correct when the subroutine return instruction is executed. FIG. 15 is a pipeline flow chart in the case where the return address of the return address storage means is not correct when the subroutine return instruction is executed. 100: instruction supply means, 103: instruction register, 104: instruction decoder, 105: instruction detection means 108: branch destination address calculation means, 119: preceding branch control means, 200: return address storage Means, 204: comparator, 207: adder.

Claims (1)

(57) [Claims] 1. An instruction supply means for fetching an instruction prior to execution, an instruction register holding a plurality of instruction codes output by the instruction supply means, and an instruction for decoding an instruction code stored at the head of the instruction register. A decoder; an instruction detecting means for detecting the presence of a subroutine call instruction or a subroutine return instruction in the instruction code immediately following the instruction code stored at the head of the instruction register; and Precedent branch control means for inputting the instruction word length of the set instruction and the detection result of the instruction detection means, and controlling to store the subroutine call instruction or the subroutine return instruction in an instruction register; and a return address of at least one subroutine. Return address storage means independent of the stack area of the memory; An adder for updating a check pointer, a return address output from the return address storage means and a return address read from the stack area, and comparing the two addresses to determine whether they match. A subroutine call instruction or a subroutine return instruction is detected from a sequence of instructions following the instruction while the instruction is being decoded. If a subroutine call instruction is detected, the instruction is designated by the subroutine call instruction. The subroutine call instruction is executed using the call destination as an instruction fetch destination address, and if a subroutine return instruction is detected, the return destination is determined only when the output of the comparator indicates a match during the decoding of the subroutine call instruction. The instruction fetched based on the output of the address storage means is transferred to the subroutine Branch control unit and executes the next instruction.