JPS63195736A - Branch instruction processor for pipeline control - Google Patents

Abstract

PURPOSE:To shorten the program executing time by performing the branch instruction processing via an exclusive means and in parallel with other instructions. CONSTITUTION:An instruction segmentation shifter B3 extracts the next instruction to an instruction register B5 every time an instruction segmentation shifter A2 extracts an instruction to be processed next to an instruction register A4. If the instruction extracted to the register B5 is equal to a BC instruction, a BC instruction detecting circuit 9 detects the BC instruction to switch a selector 8 and supplies the two highest rank bits of the register B5 to a 3rd input of an adder 7. As a result, the instruction following the BC instruction is extracted to the register A4. The BC instruction detecting signal sent from the circuit 9 is also sent to an address calculator B14 and an instruction buffer memory 16 respectively as a BC instruction start command. Thus a branch destination instruction is read out to an instruction buffer 1.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an instruction processing device in a pipeline-controlled data processing device, and particularly to a mechanism for processing an instruction sequence including a branch instruction at high speed.

[Conventional technology]

Generally, pipeline-controlled data processing devices (e.g.
(Refer to Japanese Patent Publication No. 50-21821), the fourth
The processing of each instruction is as shown in the figure.

Various stages such as decoding (D), address calculation (A), operand reading (L), and operation execution (E) are progressed sequentially, and successive instructions are executed in parallel, with a delay of one stage at a time. It is processed.

Branch instructions also pass through the pipeline, so one stage's worth of time is spent for it, and then processing of the next instruction begins.For example, even if a branch condition is not met, the next Processing of the instruction (instruction 3) starts two stages after the start of processing of the instruction (instruction 1) preceding the one-branch instruction. This also applies to devices that prefetch one branch instruction (see, for example, Japanese Patent Laid-Open No. 50-39437). Although conventional branch instruction prefetch mechanisms speed up processing when a branch is executed by pre-reading the branch target instruction, processing of the branch instruction in the pipeline cannot be omitted, and thus It takes time for one stage.

[Problem that the invention seeks to solve]

Processing of a branch instruction includes special processing different from other instructions, such as determining a branch condition, reading a branch destination instruction, and controlling a program counter. Therefore.

Data processing devices that perform advanced pipeline control have dedicated logic that can operate independently and in parallel with logic for processing other instructions. Of course, data processing devices that prefetch branch instructions are also equipped with such dedicated logic! In such a data processing device, a logic section used for processing one normal instruction is vacant at each stage of the branch instruction pipeline processing process.

Focusing on this point, the present invention processes the instruction following a branch instruction in the branch instruction processing cycle of the conventional device, eliminates the processing time of the branch instruction in pipeline processing, and
This aims to improve the processing speed of instruction sequences including one-branch instructions.

[Means for solving problems]

In the present invention, in addition to a first instruction fetching means for a normal pipeline processing mechanism, a second instruction fetching means for prefetching an instruction from an instruction buffer is provided.

means for controlling the first instruction fetching means to immediately follow the instruction before the branch instruction and fetching the next instruction after the branch instruction when the instruction fetched by the second instruction fetching means is a branch instruction; Dedicated means is provided for executing at least part of the processing of the branch instruction fetched by the second instruction fetching means in parallel with pipeline processing of other instructions.

[Effect]

According to the above configuration, in pipeline processing of a sequence of instructions, a branch instruction is skipped, and an instruction following the branch instruction is processed instead. Branch instructions are processed in parallel with other instructions by dedicated means. Therefore, the pipeline processing time for a branch instruction is "0".

(Example) FIG. 1 shows an example of the present invention. The instructions read out sequentially from the instruction buffer storage device 16 are stored in the instruction buffer (IB
R) is temporarily held at 1. The instruction extraction shifter A2 is a shifter for taking out the next instruction to be processed from the instruction buffer 1, and the instruction extraction shifter B3 is a shifter for taking out the next instruction after the instruction taken out by the instruction extraction shifter A2. It is. The instruction taken out by the instruction extraction shifter A2 is set in the instruction register A (IRA) 4, and the instruction taken out by the instruction extraction shifter B3 is set in the instruction register A (IRA) 4.
Set in instruction register B (IRB)5. Therefore, instruction register A4 holds the next instruction to be processed, and instruction register B5 holds the instruction to be processed next to the instruction in instruction register A4. The two most significant bits of each instruction indicate the length of that instruction.

The instruction buffer pointer (IBOP) 6 always holds the head position in the instruction buffer 1 of the instruction to be fetched in the instruction register A4, and its contents are updated by a mechanism described later. The starting position of the instruction to be taken out by the instruction extraction shifter A2 is indicated by the instruction buffer pointer 6, and the starting position of the instruction to be taken out by the instruction extraction shifter B3 is determined by the most significant 2 bits Q1 of the instruction taken out by the instruction extraction shifter A2. , is indicated relative to the position pointed to by the instruction buffer pointer 6.

Adder 7 is a three-man power adder for updating the contents of instruction buffer pointer 6. Its first input is the current value of the instruction buffer pointer 6, its second input is the most significant two bits (instruction length) Ql of the instruction register A4, and its third input is the output of the selector 8. The selector 8 selects either “0” or the two most significant bits Q2 of the instruction register B5 as BC.
The selection is made according to the output of the instruction detection circuit 9. The output of adder 7 is returned to instruction buffer pointer 6.

The BC instruction detection circuit 9 detects that a BC (conditional branch) instruction has been taken out to the instruction register B5, instructs a dedicated logic unit (to be described later) to start processing the BC instruction, and also controls the selector 8. Then, the most significant two bits Q2 of the instruction register B5 are supplied to the third input of the adder 7. The selector 8 normally selects 0''.

FIG. 2 shows the format of the BC instruction.

OP is a field that commands an operation, and Ml is a mask field that determines branch conditions.

X2 and B2 indicate the numbers of general-purpose registers used to calculate the address of the branch destination instruction, and B2 indicates the displacement of the address. The branch destination address is given by the sum of the contents of each general-purpose register indicated by X2 and 82, and B2. M
l is compared with the condition code at the time of execution of the BC instruction, and if the two match, a branch is taken, but if they do not match, the next instruction after the BC instruction is executed.

Returning to FIG. 1, the instructions fetched into instruction register A4 are placed in instruction queue 10 to provide information necessary for execution of operations in each processing stage of the pipeline. Operand addresses are calculated by address calculator 11 and provided to operand buffer storage 12. The operation execution unit 13 performs a specified operation using a specified operand, and stores the result in the operand buffer storage device 12, a general-purpose register (not shown), or a main storage device. Such a pipeline processing mechanism itself is well known.

When the BC instruction detection circuit 9 detects a BC instruction in the instruction register B5 and generates a BC instruction start command, the address calculator B14 calculates a branch destination address, and the branch judgment circuit 1
5 compares Ml of the BC instruction with the condition code to determine whether the branch should be executed.

Instruction buffer storage 16 supplies new instructions to instruction buffer 1 as instruction fetch shifter A2 fetches instructions. The branch destination instruction is also transferred from the instruction buffer storage device 16 to the instruction buffer 1.

The operation is as follows. Every time the instruction extraction shifter A2 takes out the next instruction to start processing into the instruction register A4, the instruction extraction shifter B3 takes out the next instruction into the instruction register B5.The BC instruction detection circuit 9 does not detect a BC instruction. As far as selector 8 is (# Ojl adder 7
supplying the third manpower.

Therefore, the contents of instruction buffer pointer 6 are updated to the sum of its old value and the length of the instruction in instruction register A4. As a result, in the next cycle, instruction register A4
The instruction next to the instruction within is extracted by the instruction extraction shifter A2.

On the other hand, if the instruction fetched into the instruction register B5 is a BC instruction, the BC instruction detection circuit 9 detects this fact and
The selector 8 is switched and the most significant two bits Ω2 of the instruction register B5 (the length of the BC instruction in the instruction register B) are supplied to the third input of the adder 7. Therefore, the contents of the instruction buffer pointer 6 are updated to the sum of its old value, the length of the instruction in the instruction register A4, and the length of the BC instruction in the instruction register B5, and as a result, in the first cycle, The next instruction after this BC instruction is fetched into instruction register A4.

The BC command detection signal from the BC command detection circuit 9 is also
It is sent to the address calculator 14 and the instruction buffer storage device 16 as a BC instruction start command, and causes the instruction buffer 1 to read the branch destination instruction. The BC instruction start command is also sent to the branch judgment circuit 15, and upon receiving this command, the branch judgment circuit 15 enters a branch judgment waiting state, and as soon as the condition code is determined in the arithmetic execution unit 13, it immediately judges the success or failure of the branch condition. Do this.

FIG. 3 shows the above-mentioned operation as a time chart, in which branch instruction 2 is placed next to instruction 1.

Branch instruction 2 does not enter the pipeline and is processed in parallel with instruction 1 by a dedicated logic unit (address calculator B14 and others). PD is a branch instruction decoding stage, PA is a branch destination address calculation stage, and PL is a branch destination instruction reading stage. In the pipeline, instruction 2 is skipped and instruction 3 is processed following instruction 1. That is,
The pipeline processing time for branch instructions is lto'', especially.

If the branch is not executed, the execution time of the BC instruction appears to be higher ((0").

FIG. 5 shows an embodiment of the present invention applied to advance control that preempts a branch instruction even earlier.

The figure only shows the instruction fetching mechanism, and the remaining parts are the same as in FIG. Command extraction shifter B
3, instruction buffer pointer B (
IBOPB) 17 and adder B18 are added. Adder 818 adds the contents of instruction buffer pointer B17 and instruction length bit I12 in instruction register B5 and returns the result to instruction buffer pointer B17, thereby
Update the start position of the instruction to be prefetched. Such an instruction prefetch mechanism itself is well known. Flag register? The bit position 19 corresponds to each byte position of the instruction buffer 1. When the BC instruction detection circuit 9 detects a BC instruction,
It I II is set in the bit position of the flag register 19 corresponding to the position in the instruction buffer of this BC instruction (indicated by the contents of the instruction buffer pointer B).

The selector 8 supplying the third input of the adder A7 for the instruction register A4 sets the predetermined value it Qu as the length of the BC instruction instead of the instruction length bit Q2 from the instruction buffer B5 in FIG. receive. Every time the instruction extraction shifter A2 takes out one instruction, the bit of the flag register 19 corresponding to the position of the next instruction (indicated by the sum of the contents of the instruction buffer pointer A6 and the instruction length Q1) is read out. The signal is given to the selector 8 as its control signal. Selector 8 selects input "0" if this bit is #Ojl, and selects input "0" if this bit is tl 171.
Select n.g. Therefore, as in FIG. 1, the BC instruction is skipped and the next instruction is fetched into instruction register A4.

If all branch instructions are taken in advance at a sufficiently early timing, the fetching of one branch destination instruction can be completed at the same time as the decoding of the instruction before the branch instruction.

In that case, if the prediction of success/failure of one branch is correct or the judgment of the branch condition is completed early enough, the apparent execution time of the BC instruction will be '0' even if the branch is executed as well as if the branch is not executed. '', and as a result, the apparent execution time of all branch instructions becomes 0''. Furthermore, in a data processing device that performs such prefetching of branch instructions or advanced pipeline control, a special logic unit necessary for parallel processing of branch instructions is already provided. Only a small amount of additional hardware is required.

〔Effect of the invention〕

According to the results of actual measurements, in most programs, BC
The appearance frequency of instructions is 13 to 20%, and that of all branch instructions is 20 to 30%. Therefore, if branch decisions are successfully predicted for about half of the BC instructions, all instructions will be
When the present invention is applied to an ideal pipeline control data processing device that processes in cycles, the program execution time is reduced by about 10%. In particular, if ideal branch instruction prefetching is performed and all branch success/failure predictions are correct, the processing time for all branch instructions will be 10' according to the present invention.
'', and the program execution time is reduced by 20 to 30%.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing an example of the format of a BC command, FIG. 3 is a time chart of the operation of the device shown in FIG. 1, and FIG. 4 is a diagram of the conventional device. The time chart of operation, FIG. 5, is a block diagram of the main part of another embodiment of the present invention. 1... Instruction buffer, 2... Instruction extraction shifter A,
3...Instruction extraction shifter B, 4...Instruction register A
, 5... Instruction register B, 6... Instruction buffer pointer, 7... Adder, 8... Selector for skipping the BC instruction and calculating the position of the next instruction, 9...
BC instruction detection circuit, 10-13... pipeline processing unit □, 14-16... BC instruction processing unit.

Claims (1)

[Claims] 1. instruction buffer means for temporarily holding a sequence of instructions sequentially read from memory; first instruction fetch means for sequentially fetching instructions from said instruction buffer means to start pipeline processing; and said first instruction fetch means. second instruction fetching means for sequentially fetching instructions subsequent to the instruction fetched by the second instruction fetching means from the instruction buffer means; and means for detecting that the instruction fetched by the second instruction fetching means is a branch instruction. and means for executing at least a part of the processing of the branch instruction fetched by the second instruction fetching means in parallel with the pipeline processing of other instructions, in response to the detection of the branch instruction by the detection means. The first instruction immediately follows the instruction before the branch instruction and fetches the next instruction after this branch instruction.
A branch instruction processing device comprising means for controlling instruction fetching means.