JP3335735B2 - Arithmetic processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing unit for executing an instruction sequence including a dedicated instruction for converting subsequent instructions into nops (no operation) by a specified number of instructions.

[0002]

2. Description of the Related Art Generally, in order to enable conditional processing (conditional branch processing) to be executed by an arithmetic processing unit, it is general to label a branch destination instruction. An instruction sequence for such condition processing will be described with reference to FIG.

First, FIG. 8A shows an example of a source code for executing a different instruction process depending on the value of n. When n = 0, the instruction # 1 is executed, and when n = 1, the instruction # 1 is executed. The instruction # 2 is executed, and when n = 2, the instruction # 3 is executed to designate, for example, a condition process to proceed to a common instruction process. The condition processing here is, for example, an error factor n (0 to 0).
It is assumed that 2) branches to instructions # 1 to # 3 for generating a trap for each of the factors n (0 to 2).

[0004] In order to enable conditional processing specified by a source code as shown in FIG. 8A to be executed by an arithmetic processing unit, the source code is compiled to create an object code (load module). There is a need to. Conventionally, since conditional processing is realized by a combination of a conditional branch instruction and a branch destination instruction, the source code shown in FIG. 8A is generally compiled as shown in FIG. 8B. It is a target. SUB (n-0), SUB in the figure
(N-1) and SUB (n-2) are (n-
0), (n-1), and (n-2) subtraction instructions (SUB instructions), JNZ (L1), JNZ (L2),
JNZ (L3) is a conditional branch instruction that indicates that a jump to an instruction (branch destination instruction) with labels L1, L2, and L3 is to be performed when the operation result of the preceding instruction (SUB instruction) is not zero. L100) is a jump instruction that unconditionally jumps to the instruction of L100.

As described above, in order to realize conditional processing in a conventional arithmetic processing unit, it is necessary to label a branch destination instruction, and it is necessary to calculate a branch destination address using a register. In the case where there are a plurality of conditions (the value of n in the above example), the number of instructions increases because the condition determination is performed separately.

[0006] In error information analysis processing for automating error processing, there is a case where it is desired to know an execution instruction before a designated cycle. However, in a conventional arithmetic processing device, if a condition process exists in the middle, it is impossible to find a target instruction, and a person has to find the load module by following the load instruction.

In the past, immediate data (immediate operand data) and arguments had to be obtained by loading data from registers. Further, the return address has to be set in the link register.

[0008]

As described above, in the conventional arithmetic processing unit, in order to realize conditional processing, a label of a branch destination instruction must be attached, and a branch destination address using a register is used. In addition to the necessity of calculation, there is a problem that the number of instructions increases.

There is another problem that a person must follow a load module to find an execution instruction before a designated cycle. In addition, there is a problem that the overhead of the memory due to the data loading from the register and the increase in the cost due to the use of the register increase the number of the register.

The present invention has been made in view of the above circumstances, and an object thereof is to realize conditional processing without branching, thereby making it unnecessary to calculate a branch address using a register and reducing the number of instructions. An object of the present invention is to provide an arithmetic processing device.

Another object of the present invention is to provide an arithmetic processing unit capable of easily acquiring at least one of an instruction and an address before a designated cycle. It is still another object of the present invention to provide an arithmetic processing device in which immediate data can be fetched and arguments can be transferred easily without requiring loading from a register. Still another object of the present invention is to provide an arithmetic processing unit capable of acquiring a return address at the time of calling a procedure without requiring a setting operation to a link register.

[0012]

SUMMARY OF THE INVENTION The present invention provides
The instruction decoded by the instruction decoding means replaces the subsequent instruction by the specified number of operations with no operation (no
p) Number of designated instructions to be converted No operation conversion instructions (S
In the case of a KIP (N) instruction), a specific decode signal (first decode signal) is output from the instruction decode means, and a specific decode signal (first decode signal) is output from the instruction decode means. If output,
SK being decoded by the instruction decoding means
During a period of N cycles corresponding to the number N of instructions specified by the IP (N) instruction, a subsequent instruction decoded during the period is no.
An instruction nopling means (instruction no operation means) for outputting a nop control signal for handling as a p instruction to the instruction decoding means is provided.

In such a configuration, the combination of the instruction decoding means and the instruction nop means makes the SK
Since no more instructions are skipped by the number of instructions specified by the IP (N) instruction to be skipped, conditional processing can be realized without branching.

Further, the present invention provides a buffer means for sequentially storing an instruction decoded by the instruction decoding means and its address, and a write pointer means for sequentially switching and specifying the storage destination of the instruction and address in the buffer means. And the instruction decoded by the instruction decoding means is an instruction history fetch instruction (GETI
(I, r) instruction) or an address history fetch instruction (GETA (i, r,
r) instruction), the instruction decoding means
When the second decode signal is output, the cycle specified by the GETI (i, r) instruction or the GETA (i, r) instruction decoded by the instruction decode means is provided. On the basis of the number i and the position in the buffer means indicated by the write pointer means, an instruction or an address i cycles before is obtained from the buffer means.

In such a configuration, instructions decoded by the instruction decoding means and their addresses are sequentially stored in the buffer means. Then, the GETI (i, r) or GETA (i, r) is obtained by the instruction decoding means.
When the instruction is decoded, the information stored in the buffer means may be GETI (i, r) or GET.
The instruction before the cycle (i cycle) specified by the i field in the A (i, r) instruction or its address is, for example, the register specified by the r field in the GETI (i, r) or GETA (i, r) instruction. Fetched into register in file.

Therefore, the instruction for which the history is to be obtained is i
By preparing a GETI (i, r) instruction at a position to be executed after the cycle, if the instruction GETI (i, r) instruction is executed, i in the GETI (i, r) instruction is executed. It is possible to take out, as an instruction history, the instruction i cycles before specified by the value of the field, for example, to a register in the register file specified by the r field in the GETI (i, r) instruction.

Similarly, the SKIP (N) instruction causes nop
Immediate data (immediate operand data) or a fixed argument of a procedure call are set in the instruction part to be converted, and a GETI (i, r) instruction is prepared after that, and these instructions are executed to execute the buffer means. Among the information stored in the GETI (i, r) instruction, the immediate data or the fixed argument specified as the instruction i cycles before by the value of the i field in the GETI (i, r) instruction is, for example,
r) It is possible to take out to the register in the register file specified by the r field in the instruction.

Similarly, the number of cycles N + 1, ie, i = N + 1, is specified as a jump destination when an instruction (target instruction) in which an error trap is likely to occur after N cycles from the execution start cycle actually traps the error. GETA
By preparing the (i, r) instruction, when the target instruction is subjected to an error trap and the execution is shifted to the GETA (i, r) instruction, the information stored in the buffer means is replaced with the corresponding instruction. The address of the instruction N + 1 cycles before specified by the value of the i field in the GETA (i, r) instruction, that is, the address of the target instruction, is used as the address of the error-occurring instruction, for example, in the GETA (i, r) instruction. It becomes possible to take out to the register in the register file specified by the r field.

Similarly, by preparing a GETA (i, r) instruction designating a cycle number 1 at a jump destination of a procedure call instruction, a buffer is provided when the GETA (i, r) is called. Among the information stored in the means, the address of the instruction one cycle before specified by the value of the i field in the GETA (i, r) instruction, that is, the address of the procedure call instruction, is set as one of the return addresses. As the previous address, for example, it is possible to take out to the register in the register file specified by the r field in the GETA (i, r) instruction.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to an arithmetic processing unit of a pipeline control system will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of a main part of the arithmetic processing device according to the embodiment.

In FIG. 1, reference numeral 1 denotes a main memory 10 to be described later.
Is an instruction cache in which a copy of a part of the instruction group stored in the instruction cache is stored. At the time of a mishit when there is no instruction on the main memory 10 to be executed in the instruction cache 1, the instruction is read from the main memory 10 into the instruction cache 1 and used. The instruction cache 1 is provided for speeding up instruction fetch, and is not always necessary.

An instruction register 2 holds an instruction fetched (fetched) from the instruction cache 1.
Here, a new instruction applied in this embodiment is shown in FIG.
This will be described with reference to FIG.

The new instructions are of three types: a designated number of instructions nop instruction, an instruction history fetch instruction, and an address history fetch instruction. First, the designated instruction number nop instruction designates that the subsequent instruction is to be nop by the designated instruction number, and as shown in FIG. 2A, an OP code indicating that the instruction is the designated instruction number nop instruction A field (operation code field), and a field (N field) for specifying the number N of instructions to be converted into nops. SKIP or SK
Expressed as IP (N).

Next, the instruction history fetch instruction specifies that the instruction before the designated cycle is to be fetched from the circular buffer 41, which will be described later. As shown in FIG. 2B, the instruction history fetch instruction is an instruction history fetch instruction. It has an OP code field, a register (destination register) designating field (r field) for designating a storage destination register of a fetched instruction, and a designated cycle number field (i field) in which a designated cycle number i is set. This instruction history retrieval instruction is expressed as GETI or GETI (i, r). The position and the size of the i-field match those of the N-field of the designated instruction number nop instruction (SKIP (N) instruction).

Next, the address history fetch instruction specifies that the address before the designated cycle is fetched from the circular buffer 41, and has the same format as that of the instruction history fetch instruction. As shown in FIG. An OP code field indicating that the instruction is an address history fetch instruction, a register (destination register) designating field (r field) designating a storage destination register of the fetched address, and a designated cycle number in which a designated cycle number i is set Field (i-field). This address history fetch instruction is sent to GETA or GETA (i, r)
Express as:

GETI (i, r) instruction and GETA
For example, the least significant bit of the OP code field of the (i, r) instruction is positioned as an I / A bit. G
The difference between ETI (i, r) and GETA (i, r) is that the value of this I / A bit is different.
r) I / A bit is “1” and GETA (i, r) I / A bit
The / A bit is "0". Of course, the reverse is also acceptable.

Referring again to FIG. 1, reference numeral 3 denotes a program counter (PC) for specifying the address (on the main memory 10) of the instruction fetched into the instruction register 2 (from the instruction cache 1). The program counter 3 is incremented for each instruction fetch cycle. However, when a jump or the like occurs, the content of the program counter 3 is updated to the jump destination address.

Reference numeral 4 denotes an instruction register 2 from the instruction cache 1.
Is a buffer mechanism for sequentially holding a pair of the instruction fetched in the instruction counter and the value (address) of the program counter 3 at that time for each instruction fetch cycle.

The buffer mechanism 4 includes a buffer (circular buffer) 41 in which each entry is used cyclically, a write-destination pointer (WP) 42 pointing to a write-destination entry of an instruction / address in the circular buffer 41, and an adder. (ADD) 43. The adder 43 outputs the instruction decoded by the instruction decoder 8 described later to GET.
In the case of the I (i, r) instruction or the GETA (i, r) instruction, the number of cycles indicated by the i field in the instruction and the value indicated by the write destination pointer 42 are added, and the read target in the circular buffer 41 is added. It is used to generate entry information (read pointer information).

Reference numeral 5 denotes a circulating buffer 41 in the buffer mechanism 4.
Either of the instruction and the address read from the
Least significant bit in P code field (the same instruction is GE
A selector to be selected according to a TI (i, r) instruction or a GETA (i, r) instruction in the case of an I / A bit). The selector 7, which is selected in accordance with the selected control signal 82, is a register file including a register group. The register file 7 is used to hold output information of the selector 6.

8 is the O of the instruction held in the instruction register 2.
An instruction decoder that decodes a P-code field and outputs various decode signals (control signals) for controlling each unit. When the content of the OP code field indicates the SKIP (N) instruction, the instruction decoder 8 converts the value of the N field (the number of designated instructions) in the instruction into an instruction n described later.
The set signal 81 for setting in the op mechanism 9 is output, and the GETI (i, r) instruction or GETA (i, r)
In the case of an instruction, the selection control signal 82
Is configured to be output. Instruction decoder 8
Is a command nop control signal 91 from the command nop mechanism 9
During the period when is output, the instruction to be decoded is handled as a nop instruction regardless of the instruction type.

Reference numeral 9 denotes an instruction nop conversion mechanism. This instruction n
When the set signal 81 is output from the instruction decoder 8, the op-converting mechanism 9 internally sets the value N of the N field in the SKIP (N) instruction decoded by the instruction decoder 8, and The instruction nop conversion control signal 91 is output only during the period of the indicated cycle (the period of N cycles).
The instruction nop conversion mechanism 9 presets the value N of the N field in the SKIP (N) instruction to be decoded by the instruction decoder 8 according to the set signal 81, for example, until the value becomes “0”. It comprises a counter that counts down according to the clock CLK of the pipeline cycle, and a gate circuit (neither is shown) that outputs an active instruction nop control signal 91 while the value of the counter is not “0”. You.

Reference numeral 10 denotes a main memory for storing various programs, data, and the like consisting of an instruction sequence. Next, the basic operation of the configuration of FIG. 1 will be described with reference to the flowchart of FIG. 3 and the basic operation explanatory diagrams of FIGS.

First, it is assumed that the instruction at the address specified by the program counter 3 is fetched from the instruction cache 1 and read into the instruction register 2. At the same time, the write destination pointer 42 in the buffer mechanism 4
The pair of the instruction fetched from the instruction cache 1 and the address specified by the program counter 3 is written to the entry in the circular buffer 41 specified by the updated write-destination pointer 42 (to indicate the internal entry) ( (Recorded) (step S1). As a result, the write destination pointer 42 indicates the instruction fetched into the instruction register 2 and its address.

In this state, the instruction fetched from the instruction cache 1 to the instruction register 2 is an ADD (addition) instruction at the address “1000” on the main memory 10 (here, A
FIG. 4 shows an example of the case of (+ instruction specifying + B).

It is assumed that the write destination pointer 42 is updated (decremented) so that the address of the entry in the circular buffer 41 becomes smaller. When the value of the write destination pointer 42 is updated in a state of “0”, the updated value of the pointer 42 indicates the maximum value of the entry address.

The instruction fetched into the instruction register 2 is
It is led to the instruction decoder 8. Instruction decoder 8 decodes the contents of the OP code field of this instruction and outputs a corresponding decode signal.

Here, the instruction decoded by the instruction decoder 8 is a designated instruction number nop instruction, ie, SKIP
The case of the (N) instruction will be described. In this case, the set signal 81 is output from the instruction decoder 8. The set signal 81 is supplied to the instruction nop together with the value of the N field in SKIP (N) decoded by the instruction decoder 8.
To the conversion mechanism 9.

Then, the instruction nop conversion mechanism 9 internally sets the value “N” of the N field in the SKIP (N) decoded by the instruction decoder 8 in accordance with the set signal 81, and sets the value in the cycle indicated by the value. An active instruction nop control signal 91 is output only during the period (N cycle period).

The instruction nop control signal 91 from the instruction nop conversion mechanism 9 is guided to the instruction decoder 8. Then, while the instruction nop control signal 91 is active (the period of N cycles), the instruction decoder 8 converts the next N instructions guided through the instruction register 2 into a nop regardless of the instruction type.
Treat as an instruction.

As described above, in the arithmetic processing unit having the configuration of FIG. 1, the instruction decoded by the instruction decoder 8 is SK
If it is an IP (N) instruction (step S2), the subsequent N
The instruction is converted to nop (step S3).

Therefore, for example, a SKIP (N) instruction of N = 2, ie, SKIP
(2) If there is an instruction, as shown in FIG.
Two instructions following the KIP (2) instruction will be noped.

Next, the instruction decoded by the instruction decoder 8 is an instruction history fetch instruction, that is, GETI (i,
r) Instruction case will be described. In this case, the value “i” of the i field in the GETI (i, r) instruction decoded by the instruction decoder 8 and the value of the write destination pointer 42 at that time are added by the adder 43.
The instruction and address pair recorded in the entry in the circular buffer 41 specified by the addition result (the read pointer information which is the adder 43), that is, the instruction in the entry specified by the current write destination pointer 42 For i
The instruction and address pair before the cycle are stored in the same buffer 4
Read from 1.

The instruction and address read from the circular buffer 41 are guided to the selector 5. The selector 5 includes the GETI decoded by the instruction decoder 8.
The I / A bit in the OP code field of the (i, r) instruction is also derived (as a selection control signal). The value of this I / A bit is "1" in the GETI (i, r) instruction.

The selector 5 has I / A = 1 as in this example.
In the case of (1), the instruction read out of the instruction and the address read from the circular buffer 41 is selectively output to the selector 6. On the other hand, when the instruction to be decoded is a GETI (i, r) instruction as in this example, the instruction decoder 8 outputs a selection control signal 82 of logic “1”. This selection control signal 82 is guided to the selector 6.

When the selection control signal 82 is “1” as in this example, the selector 6 selects the selection output information (in this case, the instruction) of the selector 5. As described above, in the arithmetic processing device having the configuration shown in FIG. 1, when the instruction decoded by the instruction decoder 8 is a GETI (i, r) instruction (step S4), the instruction and its address pair i cycles before Is extracted from the circular buffer 41, and the instruction is extracted to the r register of the register file 7 via the selectors 5 and 6 (step S5).

This state is confirmed when the address of the GETI (i, r) instruction decoded by the instruction decoder 8 is “10”.
FIG. 6 shows an example in which the instruction before the i-th cycle is a SUB (subtraction) instruction (here, a SUB instruction designating CD).

Next, the instruction decoded by the instruction decoder 8 is an address history fetch instruction, that is, a GETA.
The case of the (i, r) instruction will be described. In this case, GETA (i,
r) The value “i” of the i field in the instruction and the value of the write destination pointer 42 at that time are added by the adder 43. The instruction and address pair recorded in the entry in the circular buffer 41 specified by the addition result of the adder 43 (the read pointer information) is the instruction in the entry currently specified by the write destination pointer 42. The instruction and its address pair i cycles before are
It is read from the buffer 41.

The instruction and address read from the circular buffer 41 are guided to the selector 5. The selector 5 includes the GETA decoded by the instruction decoder 8.
The I / A bit in the OP code field of the (i, r) instruction is also derived (as a selection control signal). The value of this I / A bit is "0" in the GETA (i, r) instruction.

The selector 5 has an I / A = 0 as in this example.
In the case of (1), the address read out of the instruction and the address read from the circular buffer 41 is selectively output to the selector 6.
On the other hand, when the instruction to be decoded is a GETA (i, r) instruction as in this example, the instruction decoder 8 selects the logic “1” in the same manner as the above-mentioned GETI (i, r) instruction. A control signal 82 is output.

When the selection control signal 82 is "1" as in this example, the selector 6 selects the selected output information (address here) of the selector 5. When the instruction decoder 8 decodes the GETA (i, r) instruction as in this example, the information (address) selected by the selector 6 is the contents of the r field content “r” in the instruction. It is stored in the register (r register) in the specified register file 7.

As described above, in the arithmetic processing unit having the configuration shown in FIG. 1, the instruction decoded by the instruction
If the instruction is a TA (i, r) instruction (step S6), a pair of an instruction i cycles before and its address is fetched from the circular buffer 41, and the address of which is
The data is extracted to the r-register of the register file 7 through the register 6 (step S7).

This situation is confirmed by the fact that the address of the GETA (i, r) instruction decoded by the instruction decoder 8 is “10”.
50 ", and the address of the instruction i cycles before is" 10 ".
FIG. 7 shows an example of the case of "00".

Next, in the arithmetic processing unit of FIG.
Using the IP instruction (specified instruction number nop instruction), FIG.
An example in which the condition processing designated by the source code as shown in FIG. 8A is realized without branching as shown in FIG. Note that the source code shown in FIG. 8A includes the instruction # 1 when n = 0, the instruction # 2 when n = 1, and n
When = 2, the instruction # 3 is executed, respectively, to designate, for example, a conditional branch process that proceeds to a common instruction process.

Now, in order to enable the conditional processing designated by the source code as shown in FIG. 8A to be executed by the arithmetic processing unit having the configuration shown in FIG. 1, the source code is compiled and the object code ( Load module). At this time, a SKIP instruction is inserted before the instruction to be executed when the condition is satisfied, and compilation is performed. In this embodiment, when the source code shown in FIG. 8A is compiled, as shown in FIG. 8C, SKIP (n *
2), instruction # 1, SKIP (3), instruction # 2, SKIP
An instruction sequence following (1) and instruction # 3 is created.

As described above, in the arithmetic processing unit having the configuration shown in FIG. 1, the subsequent N instructions are noped by the SKIP (N) instruction (steps S2 and S3 in FIG. 3). Accordingly, in the example of the instruction sequence shown in FIG. 8C, when n = 0, SKIP (n * 2), that is, SKIP (0), followed by instructions # 1 and SKIP (3). Executed, and the following three instructions (instruction # 2, SKIP (1), instruction #
After 3) is noped, the instruction following instruction # 3 is executed.

Similarly, when n = 1, SKIP (n
* 2), that is, after SKIP (2) is executed and the following two instructions (instruction # 1, SKIP (3)) are nopized,
The instructions # 2 and SKIP (1) are sequentially executed, and after the subsequent one instruction (instruction # 3) is noped, the instruction following the instruction # 3 is executed.

Similarly, when n = 2, SKIP (n
* 2), that is, SKIP (4) is executed, and the following four instructions (instruction # 1, SKIP (3), instruction # 2, SKIP
After the (1)) is converted to a nop, the instruction # 3 next to the SKIP (1) is executed, and the instruction next to the next instruction # 3 is executed.

As described above, in the arithmetic processing device having the configuration shown in FIG. 1, by using the SKIP instruction (instruction to change the number of designated instructions to nop), conditional processing can be realized without using branching. Therefore, as is clear from FIG. 8C, the number of instructions constituting the instruction sequence for the condition processing is
The number of instructions can be reduced as compared with the conventional instruction sequence shown in FIG. Further, since the number of instructions can be reduced, the processing can be speeded up. Further, since there is no problem of stopping the pipeline due to the occurrence of a branch, the speed can be further increased.

Next, in the arithmetic processing unit of FIG.
A case where an instruction before a specified cycle is acquired using a TI instruction (instruction history retrieval instruction) (instruction history retrieval) will be described with reference to FIG.

First, in order to make it possible to acquire an instruction before a designated cycle by using a GETI instruction, it is necessary to prevent a branch in the middle. Therefore, if conditional processing is required on the way, as described above, the conditional processing is compiled into a form using the SKIP instruction so that the conditional processing without branching can be realized.

FIG. 9 shows that the SKIP
(1) some one instruction, instruction # 1, some two instructions,
When the instruction sequence of GETI (3, r) is stored,
The instruction sequence is sequentially executed one instruction at a time, and the GETI (3,
This is for explaining the situation when r) is executed.

In the example of FIG. 9, SKIP (1), some one instruction, instruction # 1, some two instructions, GETI (3,
r) is fetched into the instruction register 2 one instruction at a time from SKIP (1), the write destination pointer 42 is decremented, and the pointer 4 after the decrement is decremented.
The fetched instruction and its address are recorded in the entry in the circular buffer 41 designated by the second instruction (step S1). The next instruction following SKIP (1) is
Nop is specified by specifying KIP (1) (step S
2, S3).

Now, GETI (3, r) is fetched into the instruction register 2 and the GETI (3, r) and its address are stored in the entry in the circular buffer 41 indicated by the write destination pointer 42 as shown in FIG. (Step S1), and the corresponding GETI (3, r) is stored in the instruction decoder 8
(Step S4).

In this case, as is apparent from the description with reference to FIG. 6, the value “3” (i = 3) of the i field of GETI (3, r) and the value of the write destination pointer 42 For the instruction and address pair read from the entry in the circular buffer 41 specified by the addition value (by the adder 43), that is, for the instruction GETI (3, r) in the entry pointed to by the current write destination pointer 42 Instruction of the instruction and address pair three cycles before (here, instruction #
9) is stored in the r register in the register file 7 specified by the r field of the GETI (3, r) as shown in FIG. 9 (step S5).

Here, since the conditional processing is realized without branching by using SKIP (1), even if there is a conditional processing in the middle, the execution of GETI (3, r) will cause the execution of the specified cycle (before the designated cycle). Here, the instruction (instruction # three cycles earlier)
1) can be correctly extracted to the designated register (r register) in the register file 7.

Next, in the arithmetic processing unit of FIG.
Immediate data is stored in the instruction portion (position) noped by the IP instruction (specified instruction number nop instruction), and the immediate data is stored in the register file 7 using the GETI instruction (instruction history fetch instruction). The case of extracting (immediate operand specification) will be described with reference to FIG.

First, in order to make it possible to extract immediate data using the GETI instruction, the SKI
It is necessary to store immediate data at an instruction position which is converted to a nop by the P instruction.

FIG. 10 shows that the SKIP
(2) When an instruction sequence of constant # 1, constant # 2, and GETI (2, r) is stored (constants # 1 and # 2 are also regarded as instructions), one instruction at a time from SKIP (2) This is for explaining a state when the program is executed and GETI (2, r) is executed. In the example of FIG.
Two immediate data of a constant # 1 and a constant # 2 are stored in advance in the two instruction portions which are converted to nop in (2).

In the example of FIG. 10, SKIP (2), constant #
Each time 1, the constant # 2, and the GETI (2, r) are fetched one by one from the SKIP (2) into the instruction register 2, the write destination pointer 42 is decremented, and the designation of the pointer 42 after the decrement The fetched instruction and its address are recorded in the entry in the circular buffer 41 (step S1). Also, SKI
The next two constants # 1 and # 2 of P (2) are the SKIP
Nop is specified by the designation of (2) (steps S2, S
3). Therefore, even if constants # 1 and # 2, which are immediate data, are stored (set) in the next two instruction portions of SKIP (2), there is no problem.

Now, GETI (2, r) is fetched into the instruction register 2 and the GETI (2, r) and its address are stored in the write destination pointer 42 as shown in FIG.
(Step S1), and the GETI (2, r) is decoded by the instruction decoder 8 (step S4).

In this case, as is clear from the description with reference to FIG. 6, the value "2" (i = 2) of the i field of GETI (2, r) and the value of the write destination pointer 42 For the instruction and address pair read from the entry in the circular buffer 41 specified by the added value (by the adder 43), that is, for the instruction GETI (2, r) in the entry pointed to by the current write destination pointer 42 As shown in FIG. 10, the instruction (in this case, the constant # 1 stored instead of the instruction) of the instruction and address pair two cycles before is specified by the r field of the GETI (2, r). Is stored in the r register in the register file 7 (step S5).

As described above, the SKIP (2) uses the nop
Constants # 1 and # 2, which are immediate data, in the two instruction parts to be converted
Is stored, the GETI at the position following the constant # 2 is stored.
By executing (2, r), constant # 1 (immediate data) can be obtained without performing a load instruction (designating data loading from a register). Note that GETI (2,
If GETI (1, r) is used instead of r), it is a matter of course that constant # 2 can be obtained.

Next, in the arithmetic processing unit of FIG.
Arguments are stored in the instruction portion (position) noped by the IP instruction (specified instruction number nop instruction), and the argument is stored in G
When fetching into the register file 7 using the ETI instruction (instruction history fetching instruction) (fixed argument passing),
This will be described with reference to FIG.

First, in order to be able to deliver an argument (fixed argument) by using the GETI instruction, the argument of the function (procedure call) is stored at the instruction position which is converted into a nop by the SKIP instruction at the time of compilation. GET to the destination
It is necessary to insert an I instruction.

FIG. 11 shows that the SKIP
(2), argument arg1, argument arg2, instruction sequence of CALL (FN1) which is a procedure call instruction (argument arg1,
arg2 is also regarded as an instruction) and CAL
When GETI (2, r) is stored in (the address corresponding to) the destination FN1 specified by L (FN1),
SKIP (2) is executed one instruction at a time in order, and CALL
After execution of (FN1), the target GETI (2,
This is for explaining the situation when r) is executed. In the example shown in FIG. 11, fixed arguments arg1 and arg2 are stored in advance in two instruction portions which are converted to nops by SKIP (2).

In the example of FIG. 11, SKIP (2), argument a
rg1, argument arg2, CALL (FN1), GETI
Every time (2, r) is fetched one instruction at a time from the SKIP (2) into the instruction register 2, the write destination pointer 42
Is decremented, and the fetched instruction and its address are recorded in the entry in the circular buffer 41 designated by the pointer 42 after the decrement (step S1). In addition, the next two arguments arg1 and arg2 of SKIP (2) are converted to nops by designating the SKIP (2) (steps S2 and S3). Therefore, in the next two instruction parts of SKIP (2), the argument arg
Even if 1 and arg2 are stored (set), there is no problem.

The GETI (2, r) is fetched into the instruction register 2 and the GETI (2, r) and its address are stored in the write destination pointer 42 as shown in FIG.
(Step S1), and the GETI (2, r) is decoded by the instruction decoder 8 (step S4).

In this case, as is clear from the description with reference to FIG. 6, the value "2" (i = 2) of the i field of GETI (2, r) and the value of the write destination pointer 42 For the instruction and address pair read from the entry in the circular buffer 41 specified by the added value (by the adder 43), that is, for the instruction GETI (2, r) in the entry pointed to by the current write destination pointer 42 As shown in FIG. 11, the instruction (in this case, the argument arg2 stored in place of the instruction) of the instruction and address pair two cycles earlier specifies the r field of the GETI (2, r). Is stored in the r register in the register file 7 (step S5).

As described above, nop is performed by SKIP (2).
Function (procedure call) argument ar
g1 and arg2 are stored, and GETI (2, r) is stored at the jump destination.
Is inserted, the argument arg2 can be obtained by executing GETI (2, r) without executing a load instruction (designating data loading from a register). If GETI (3, r) is used instead of GETI (2, r), it is needless to say that the argument arg1 can be obtained.

Incidentally, a supercomputer or the like often has a configuration in which the next instruction can be executed without waiting for the completion of the execution of one instruction. In such a case, even if an error trap occurs, it is difficult to obtain the address of the instruction in which the error occurs. Therefore,
In the arithmetic processing unit of FIG. 1, when an error trap occurs, a jump is made to a GETA instruction (address history extraction instruction), and the address of the error generation instruction is extracted into the register file 7 using the GETA instruction ( The address fetch of an error generating instruction will be described with reference to FIG.

First, in order to be able to take out the address of an error-occurring instruction using the GETA instruction, it is necessary to jump to the GETA instruction if an error trap occurs during compilation. When conditional processing is required, conditional processing can be performed without branching using the SKIP instruction.

FIG. 12 shows, on the main memory 10, a floating point addition instruction fadd which is a pipeline operation instruction for generating an execution result in three cycles, for example,
When GETA (3, r) is stored at the interrupt destination when the preceding instruction fadd traps an error during execution of the later instruction of the two instructions, the instruction fadd Instructions are sequentially started one instruction at a time, and as a result of the instruction fadd trapping an error, GETA (3,
This is for explaining the situation when r) is executed. It is assumed that the address of the instruction fadd is "1000".

In the example of FIG. 12, each time the instruction fadd and the following two instructions are sequentially fetched one by one into the instruction register 2, the write destination pointer 42 is decremented, and the pointer 42 after the decrement is designated. The fetched instruction and its address are recorded in the entry in the circular buffer 41 (step S1).

Here, it is assumed that the instruction fadd has error trapped two cycles after the execution start cycle. In this case, at the same time that the interrupt destination GETA (3, r) is fetched into the instruction register 2, the instruction fadd and its address are stored in the instruction fetched one cycle before the instruction fadd (the instruction succeeding the instruction fadd). The instruction is recorded in the entry in the circular buffer 41 located next to the instruction following the instruction (step S1). Then, it is assumed that GETA (3, r) fetched in the instruction register 2 is decoded by the instruction decoder 8 (step S6).

In this case, as is apparent from the description with reference to FIG. 7, the value "3" (i = 3) of the i field of GETA (3, r) and the value of the write destination pointer 42 For the instruction and address pair read from the entry in the circular buffer 41 specified by the addition value (by the adder 43), that is, the instruction GETA (3, r) in the entry pointed to by the current write destination pointer 42 As shown in FIG. 12, the address (here, "1000") of the pair of the error generating instruction fadd and the address three cycles before is stored in the register file 7 specified by the r field of the GETI (3, r). (Step S7).

Next, in the arithmetic processing unit of FIG.
A GETA instruction is inserted at the jump destination of the LL instruction (procedure call instruction), and a RET instruction (return instruction) is inserted at the end of the procedure.
The case where the address of the ALL instruction is fetched into the register file 7 (designation of the return address at the time of calling the procedure) will be described with reference to FIG.

FIG. 13 shows that CALL is stored in the main memory 10.
(FN1), an instruction sequence starting with instruction # 1 to be executed when returning from the procedure call by the CALL (FN1) is stored, and further, an address corresponding to a jump destination FN1 specified by the CALL (FN1). GE in the area starting with
An instruction sequence is stored in which TA (1, r) is the first instruction and RET (r + 1) for executing execution at an address (return address) obtained by adding 1 to the contents of the r register in the register file 7 as the last instruction. CALL (FN
Execution of instructions is started one by one in order from 1), and RET (r +
This is for explaining the situation when the execution returns to the return instruction # 1 by the execution of 1). In addition, CALL
(FN1), the address of the instruction # 1 is “100
0 "and" 1001 ".

In the example shown in FIG. 13, first, CALL (FN1)
Then, GETA (1, r) is fetched into the instruction register 2. Each time the instruction is fetched, the write destination pointer 42 is decremented, and the fetched instruction and its address are recorded in the entry in the circular buffer 41 designated by the decremented pointer 42 (step S1).

Here, when GETA (1, r) fetched into the instruction register 2 is decoded by the instruction decoder 8 (step S6), as apparent from the description with reference to FIG. An instruction read from an entry in the circular buffer 41 specified by an addition value (by the adder 43) of the value “1” (i = 1) of the i field of GETA (1, r) and the value of the write destination pointer 42 And an address pair, that is, an address (here, an instruction pair) of an instruction and address pair one cycle before the instruction GETA (1, r) in the entry pointed to by the write destination pointer 42
CALL (FN1) address "1000") is
As shown in FIG. 3, the data is stored in the r register in the register file 7 specified by the r field of the GETA (1, r) (step S7).

Now, it is assumed that the instruction sequence following GETA (1, r) is sequentially fetched into the instruction register 2 one instruction at a time, and RET (r + 1) is fetched into the instruction register 2 soon. Then, RET (r + 1) and its address are recorded in the entry in the circular buffer 41 specified by the write destination pointer.

Then, RET (r + 1) fetched into the instruction register 2 is decoded by the instruction decoder 8 and executed according to the decoding result (step S).
6, S8). This RET (r + 1) is a return instruction that shifts execution to an address obtained by adding 1 to the contents of the r register in the register file 7 as a return address. Here, CALL is stored in the r register in the register file 7 by executing the above-mentioned GETA (1, r).
The address “1000” of (FN1) is stored.

Therefore, by executing RET (r + 1), the instruction at address “1001”, that is, CALL (FN
Returning to the instruction # 1 at the address next to 1). Specifically, after the address “1001” is set in the program counter 3, the address “1001”
Instruction # 1 is fetched from the instruction cache 1 to the instruction register 2.

As described above, GE is set at the jump destination of the CALL instruction.
TA (1, r) is inserted, and the address of the CALL instruction is taken out to the designated register (r register) in the register file 7 by using the GETA (1, r) instruction. By inserting a RET instruction for returning to the address next to the address indicated by the register, the operation of setting the return address in the link register can be performed without returning to the CALL instruction when returning from the procedure call by the RET instruction. Execution can be moved to the address following the address (the return address of the procedure call).

In the above embodiment, the write destination pointer 42 has been described as being decremented, but may be incremented. However, in this case, a subtractor is provided instead of the adder 43, and the GETI
When the (i, r) or GETA (i, r) instruction is executed,
GET is performed from the value of the write destination pointer 42 by this subtractor.
It is necessary to obtain the entry address indicating the entry in the circular buffer 41 to be fetched by subtracting the value “i” of the i field in the I (i, r) or GETA (i, r) instruction.

In the above embodiment, the instruction cache 1
It has been described that the instruction fetched from the instruction register 2 into the instruction register 2 is decoded in the next cycle. However, in order to speed up the processing, an instruction buffer is provided in place of the instruction register 2 to transfer the instruction from the instruction cache 1 to the instruction buffer. Instruction prefetching may be performed. However, in this case,
There is a delay of several cycles until the instruction fetched from the instruction cache 1 to the instruction buffer is decoded. Therefore, in synchronization with this delay, the contents of the write destination pointer 42 are delayed and the corresponding instruction is decoded. A mechanism (for example, a group of pipeline registers) is required to hold the data. And GETI (i, r) or GETA
In the execution of the (i, r) instruction, not the value of the write destination pointer 42 but the value of the i field in the instruction is calculated.
An address indicating the entry in the circular buffer 41 where the currently decoded instruction stored in the mechanism is recorded.

In the above embodiment, the circular buffer 41
Has been described as storing an instruction and address pair. However, if an arithmetic processing unit does not use the GETA instruction, only the instruction is stored, and if the arithmetic processing unit does not use the GETI instruction, only the address is stored. It does not matter.

[0098]

As described in detail above, according to the present invention,
The following effects can be obtained. (1) Designated number of instructions nop instruction (SKIP (N) instruction)
Since the following instructions can be converted into nops as many as the number desired to be skipped, conditional processing can be realized without branching. (2) By preparing an instruction history fetch instruction (GETI (i, r) instruction) at a position to be executed i cycles after the instruction whose history is to be acquired, when the fetch instruction is executed, the fetch is performed. The instruction i cycles before the instruction specified by the instruction can be easily taken out from the buffer means as the instruction history. (3) Designated number of instructions nop instruction (SKIP (N) instruction)
The immediate data (immediate operand data) or the fixed argument of the procedure call is set in the instruction portion to be nop by the following, and further, the instruction history fetch instruction (GETI)
By preparing (i, r) instructions) and executing them, it is possible to easily obtain the immediate data or the fixed argument of the instruction portion i cycles before specified by the fetch instruction from the buffer means. Thus, since there is no need to load immediate data or arguments from registers,
It is possible to prevent the overhead of the memory due to the loading from the register and the increase in cost due to the use of the register. (4) The number of cycles N + 1 is set to a jump destination when an instruction (target instruction) in which an error trap is likely to occur after N cycles after the execution start cycle actually traps the error.
Is prepared, and if the target instruction is error-trapped and execution shifts to the fetch instruction, the instruction of the (N + 1) -th cycle preceding instruction specified by the fetch instruction is prepared. , Ie, the address of the target instruction, can be easily taken out from the buffer means as the address of the error generating instruction. (5) By preparing an address history fetch instruction (GETA (i, r) instruction) specifying a cycle number 1 at the jump destination of the procedure call instruction, when the fetch instruction is called, the fetch is performed. The address of the instruction one cycle before the instruction designated by the instruction, that is, the address of the procedure call instruction can be easily taken out from the buffer means as the address immediately before the return address. Therefore, it is not necessary to set the return address in the link register as in the related art.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a main part of an arithmetic processing device according to an embodiment of the present invention.

FIG. 2 is a format diagram of a new instruction applied in the embodiment.

FIG. 3 is a flowchart for explaining the flow of processing in the embodiment focusing on the processing when the instruction shown in FIG. 2 is fetched;

FIG. 4 is a view for explaining functions of a buffer mechanism 4 in the embodiment.

FIG. 5 is a diagram showing a nop instruction (S
FIG. 7 is a diagram for explaining a designated instruction number nop function realized by executing a KIP instruction).

FIG. 6 shows an instruction history fetch instruction (GET) in the embodiment.
FIG. 4 is a diagram for explaining an instruction fetching function before a designated cycle realized by executing an I instruction).

FIG. 7 shows an address history fetch instruction (G
FIG. 3 is a diagram for explaining an address fetching function of an instruction before a designated cycle realized by executing an ETA instruction).

FIG. 8 shows an instruction sequence (module) for realizing conditional processing without branching in the embodiment, a source code describing the conditional processing, and an instruction sequence (module) for conventional conditional processing with branching. 8A shows a source code, FIG. 8B shows a conventional instruction sequence as a result of compiling the source code, and FIG. 8C shows a result of compiling the source code. Instruction sequence in the example.

FIG. 9 is an exemplary view for explaining an instruction history fetching to obtain an instruction before a designated cycle by using a GETI instruction in the embodiment.

FIG. 10 is a diagram for describing immediate operand specification in which immediate data is stored in an instruction portion converted into a nop by an SKIP instruction and the immediate data is extracted to a register using a GETI instruction in the embodiment.

FIG. 11 is a diagram showing an example in which an argument is stored in an instruction part which has been converted into a nop by an SKIP instruction in the embodiment, and the argument is GET.
The figure for demonstrating the fixed argument delivery which takes out to a register using an I instruction.

FIG. 12 is a diagram for explaining address extraction of an error-occurring instruction in which an error trap is skipped to a GETA instruction and an address of the error-occurring instruction is extracted to a register using the GETA instruction in the embodiment; .

FIG. 13 shows that a GETA instruction is inserted at a jump destination of a CALL instruction (procedure call instruction) and a RET instruction (return instruction) is inserted at a procedure end position in the embodiment, and the CALL instruction is utilized using the GETA instruction. FIG. 9 is a diagram for explaining the return address specification at the time of calling the procedure, in which the address of (1) is fetched into a register and used for specifying the return address.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Instruction cache, 2 ... Instruction register, 3 ... Program counter (PC), 4 ... Buffer mechanism, 5, 6 ... Selector, 7 ... Register file, 8 ... Instruction decoder, 9 ...
Instruction nop conversion mechanism, 10: main memory, 41: circular buffer, 42: write destination pointer (WP), 43: adder (ADD), 81: set signal, 82: selection control signal,
91: Instruction nop control signal.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification code FI G06F 9/34 350 G06F 9/34 350A 390 390 9/40 310 9/40 310C 9/42 320 9/42 320 (72) Invention Yoshiya Mori 1 Toshiba-cho, Fuchu-shi, Tokyo, Japan Inside the Toshiba Fuchu factory (72) Inventor Kazuaki Takeuchi 1-Toshiba-cho, Fuchu-shi, Tokyo inside the Toshiba Fuchu factory, (56) References JP4 JP-A-369727 (JP, A) JP-A-62-66332 (JP, A) JP-A-62-262139 (JP, A) JP-A-2-137028 (JP, A) JP-A-61-221939 (JP, A) JP-A-63-66638 (JP, A) JP-A-62-262140 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 9/30-9/42

Claims (9)

(57) [Claims] 1. A storage means for storing an instruction group, and an instruction decoding means for decoding an instruction fetched from the storage means and outputting various decode signals necessary for executing the instruction. The specified number of instructions that make the subsequent instruction no-operation by the specified number of instructions
In the case of an operation instruction, an instruction decoding means for outputting a corresponding specific decode signal; and when the specific decode signal is output from the instruction decode means, the designated instruction number decoded by the instruction decode means. During a cycle corresponding to the number of instructions specified by the operation instruction, an instruction no-output for outputting to the instruction decoding means a no-operation control signal for treating a subsequent instruction decoded during the cycle as a no-operation instruction. Operating instruction means, wherein the instruction decoding means outputs the instruction to be decoded to a decoding instruction regardless of the instruction type while the instruction no-operating means outputs the no-operation control signal.・ It is characterized by being treated as an operation instruction Arithmetic processing unit. 2. The method according to claim 1, further comprising : inserting, in the storage means, the no-operation instruction of the designated number of instructions for causing the instruction group to be executed only when the condition is satisfied to be no operation, immediately before the instruction of the instruction group. If the no-operation instruction is executed, the
2. The arithmetic processing device according to claim 1, wherein the number of instructions specified by the operation instruction is changed to no operation. 3. A storage means for storing an instruction group, and an instruction decoding means for decoding an instruction fetched from the storage means and outputting various decode signals necessary for executing the instruction. The specified number of instructions that make the subsequent instruction no-operation by the specified number of instructions
An instruction decode that outputs a corresponding first decode signal in the case of an operation instruction, and outputs a corresponding second decode signal in the case of an instruction history fetch instruction that fetches an instruction before a designated cycle. Means; buffer means for sequentially storing instructions to be decoded by the decoding means; write pointer means for sequentially switching and specifying a storage location of the instructions in the buffer means; Is output during the cycle corresponding to the number of instructions designated by the no-operation instruction, the number of subsequent instructions decoded during the cycle is equal to the number of instructions designated by the instruction decoding means. A no-operation control signal for handling as an operation instruction Instruction no-operation means for outputting to the code means; and when the second decode signal is output from the instruction decode means, the number of cycles designated by the instruction history fetch instruction decoded by the instruction decode means. Means for acquiring an instruction before a designated cycle from the buffer means based on the position in the buffer means pointed to by the write pointer means, wherein the instruction decode means comprises: An arithmetic processing device characterized in that an instruction to be decoded is treated as a no-operation instruction regardless of the instruction type while the no-operation control signal is being output. 4. A storage means for storing an instruction group, and an instruction decoding means for decoding an instruction fetched from the storage means and outputting various decode signals necessary for executing the instruction. The specified number of instructions that make the subsequent instruction no-operation by the specified number of instructions
In the case of an operation instruction, a corresponding first decode signal is output, and in the case that the instruction is an address history fetch instruction for fetching the address of the instruction before the designated cycle,
Instruction decoding means for outputting a corresponding second decode signal; buffer means for sequentially storing an address of an instruction to be decoded by the decoding means; and designation of sequentially switching the storage destination of the address in the buffer means A write pointer means for performing the operation and, when the first decode signal is output from the instruction decode means, a cycle corresponding to the number of instructions specified by the specified instruction number no-operation instruction decoded by the instruction decode means During the period, the instruction no-operating means for outputting to the instruction decoding means a no-operation control signal for treating a subsequent instruction decoded during that time as a no-operation instruction; and 2 decoded signal is output Obtaining the address of the instruction before the designated cycle from the buffer means based on the number of cycles specified by the address history fetch instruction decoded by the instruction decoding means and the position in the buffer means indicated by the write pointer means. Means for decoding the instruction to be decoded during the period in which the instruction no operation control signal is output from the instruction no operation control means, irrespective of the instruction type. An arithmetic processing device characterized by being treated as an operation instruction. 5. A storage means for storing an instruction group, and an instruction decoding means for decoding an instruction fetched from the storage means and outputting various decode signals necessary for executing the instruction. The specified number of instructions that make the subsequent instruction no-operation by the specified number of instructions
In the case of an operation instruction, a corresponding first decode signal is output, and if the instruction is an instruction history fetch instruction for fetching an instruction before the specified cycle or an address history fetch instruction for fetching the address of the instruction before the specified cycle. Instruction decoding means for outputting a corresponding second decode signal; buffer means for sequentially storing an instruction to be decoded by the decoding means and its address; and storage of the instruction and address in the buffer means. Write pointer means for sequentially switching and specifying a destination; and when the first decoding signal is output from the instruction decoding means, an instruction specified by the specified instruction number no-operation instruction decoded by the instruction decoding means. Decode during and after a number of cycles An instruction no-operation conversion means for outputting a no-operation conversion control signal for treating a subsequent instruction to be processed as a no-operation instruction to the instruction decoding means; and the second decoding signal is output from the instruction decoding means. In the case where there is a specified cycle from the buffer means based on the number of cycles designated by the instruction history fetch instruction or the address history fetch instruction decoded by the instruction decoding means and the position in the buffer means indicated by the write pointer means, Means for obtaining a previous instruction or address, the instruction decoding means comprising:
An arithmetic processing device wherein an instruction to be decoded is treated as a no-operation instruction regardless of the instruction type while the instruction-no-operation control signal is being output from the instruction-no-operation control means. 6. The storage device according to claim 1, wherein the number of designated instructions is no
Bae configuration of the instruction, the designated number of instructions No Opereshi
The immediate history data set in the instruction part to be set to no operation by the unification instruction, and the instruction history fetch instruction for fetching from the buffer means by specifying the number of cycles by regarding the immediate data to be obtained as an instruction. 4. The storage device according to claim 3, wherein when the instruction history fetch instruction is executed, the immediate data before the cycle specified by the instruction history fetch instruction is acquired from the buffer means. The arithmetic processing device according to claim 5. 7. in the storage means, the designated number of instructions No o
Bae configuration of the instruction, the designated number of instructions No Opereshi
® emission reduction instruction by no operation of the the procedure call argument is set in the instruction portion the instruction history fetching instruction for retrieving from said buffer means, and to be acquired by specifying the number of cycles is regarded as instruction arguments And storing the argument before the cycle specified by the instruction history fetching instruction from the buffer means when the instruction history fetching instruction is executed. The arithmetic processing device according to claim 5. 8. in said storage means, to jump when after N cycles than the execution start cycle may occur an error trap instruction has actually error trap, the address history extraction to specify the number of cycles N + 1 An instruction is stored, and when the address history fetch instruction is executed, the address of the error trapped instruction before the cycle specified by the address history fetch instruction is acquired from the buffer means. The arithmetic processing device according to claim 4 or 5, wherein Of 9. in said storage means, to jump procedure call instruction, stores the address history extraction instruction that specifies a number of cycles, when the address history fetching instruction is executed, the address 6. The operation according to claim 4, wherein an address of the procedure call instruction before the cycle specified by the history fetch instruction is obtained from the buffer means, and an address next to the address is obtained as a return address. Processing equipment.