JP2534674B2 - Information processing device - Google Patents

Description

The present invention relates to an information processing apparatus for prefetching instructions, and more particularly to predicting a branch direction of a conditional branch instruction for effectively prefetching instructions. The present invention relates to an information processing device realized with a small amount of hardware.

(Prior Art) Generally, in an information processing apparatus, a program is executed by performing an operation of fetching an instruction code (hereinafter, instruction fetch), decoding an instruction code (hereinafter, instruction decode), and executing an instruction for each instruction. ing. In addition to this, some instructions require operations such as accessing an operand from the main memory (hereinafter, operand read) and writing back the instruction execution result to the main memory (hereinafter, operand write).

In these information processing apparatuses, the main memory control unit performs instruction fetch / operand read and operand write, the instruction decode unit performs instruction decode, and the instruction execution unit performs instruction execution. Since these operations are shared and processed by the respective parts in the information processing apparatus, it is possible to perform these operations in parallel by overlapping these operations for several consecutive instructions. Focusing on this point, in order to execute instructions at high speed, it is widely practiced to control operations of several instructions in parallel. This is called pipeline control, and an information processing apparatus that takes such control is called a pipeline type information processing apparatus.

In order to perform high-speed processing in the pipeline type information processing device, it is necessary that the respective parts in the device operate in parallel. However, with a conditional branch instruction, it is not possible to determine whether or not the branch condition was met and the branch was taken until the execution of the instruction immediately before that was completed and a valid value was set in the condition code.
The instruction following the conditional branch instruction cannot be fetched or decoded. Therefore, each unit in the information processing device has an idle time, which hinders the improvement of the instruction execution speed.

For a branch instruction, 1) a relative branch in which the branch distance set in the instruction code is added to the current program counter to obtain the branch destination address, and 2) the instruction code is specified regardless of the current program counter value. There are two types of absolute branching in which the branch destination address is obtained from the stored information and the value of the general-purpose register. In general, a conditional branch instruction often uses a relative branch. In this case, the instruction code (4th
The branch distance specified in the figure is determined when creating an executable machine language program. If the branch distance is negative, it means that the current program counter is subtracted, that is, the branch is backward in the program.
Conversely, if the branch distance is a positive value, the current program
It means to increment the counter, that is, to branch forward in the program.

In order to solve this problem, a method of determining a prefetch direction of an instruction by predicting whether to branch based on whether the branch distance specified by a conditional branch instruction is positive or negative, and history information of the branch instruction are used as an information processing device. A method of controlling the instruction prefetch direction based on this is proposed.

(Problems to be Solved by the Invention) A conditional branch instruction prediction for improving the processing speed of a pipeline type information processing apparatus is prefetched by predicting a branch from a positive or negative branch distance specified by a conditional branch instruction. The method of determining the direction has a problem that the prediction accuracy is low.
Also, in the method that is performed based on the history information of branch instructions,
There is a drawback that a large amount of hardware is required to perform complicated processing.

(Means for Solving Problems) In the information processing apparatus according to the present invention, in order to solve the above problems, by providing a conditional branch prediction unit that performs branch prediction with the type of the branch instruction and the branch distance as inputs. ,
Decide the instruction prefetch direction by performing accurate branch prediction with less hardware.

(Operation) The basic configuration of the present invention is shown in FIG. In FIG. 1, when a conditional branch instruction is set in the instruction register 3 during execution of the program, the conditional branch recognition unit 4 outputs a branch condition and the branch distance recognition unit 5 outputs a value corresponding to the branch distance. , And inputs this to the conditional branch prediction unit 6. The conditional branch prediction unit performs branch prediction of the conditional branch instruction from the given information, and sends the result to the instruction prefetching unit 7. When it is determined by the branch prediction that the branch is taken, the instruction prefetching unit 7 fetches the instruction code from the branch destination. If the branch prediction determines that the branch is not taken, the instruction prefetch unit 7 fetches the instruction code from the instruction next to the conditional branch instruction.

By performing such control, it is possible to reduce the idle time that occurs in each part in the information processing device when the conditional branch instruction is executed, and improve the instruction execution speed.

(Embodiment) In the present embodiment, the inside of the information processing apparatus will be divided as shown in FIG. In the figure, the main memory control unit 12
Is a part for accessing the main memory, and has the instruction prefetching part 2 inside. There is also an information processing device having a memory management mechanism and a cache memory inside the main memory control unit 12. The instruction decoder 13 is a portion that decodes instructions, and has a conditional branch recognition unit 4, a branch distance recognition unit 5, and a conditional branch prediction unit 6 inside. The instruction execution unit 14 is a portion that executes an instruction.

FIG. 3 is a diagram showing the configuration of the instruction decoder 13 in this embodiment. In the figure, the conditional branch instruction determination unit 20 provided inside the conditional branch recognition unit 4 is the instruction register 3
The gate 21 determines whether the instruction code stored in the instruction branch instruction is a conditional branch instruction. When the conditional branch determination unit 20 determines that the instruction code stored in the instruction register 3 is a conditional branch instruction, It is a part that outputs the condition of the branch to the conditional branch prediction unit. The NOT unit 22 inside the branch distance recognition unit 5 performs a logical NOT operation on each bit of the branch distance, the selector unit 23 outputs one of the two inputs, and the FF1 unit 24 inputs the input data. This is a part for performing a search from the most significant bit and outputting the position of the bit where the first 1 is found in a binary number. The branch prediction table 25 provided inside the conditional branch prediction unit 6 is a memory in which branch characteristics investigated in advance, such as a high possibility of branching if the branch distance is negative and short, are recorded. Yes, a 1-bit branch prediction result is output according to the branch condition and the branch distance input to this memory. The contents of this memory do not change during the execution of the program. This point is different from the history table for recording the history of branch instructions executed in the past.

FIG. 4 is a diagram showing an instruction format of a conditional branch instruction in the information processing apparatus described in this embodiment. In the figure,
The instruction code 31 is 8 bits, of which the upper 4 bits have a value 32 indicating a conditional branch instruction, and the lower 4 bits have a value 33 indicating a branching condition. The branch distance is 2
The most significant bit is the sign bit 35.

In the present invention, “branch distance” is used in the sense that it is added to the program counter in the case of a relative branch instruction, but such a concept is described in, for example, the literature (A CASE STUDY
OF VAX-11 INSTRUCTION SET USAGE FOR COMPILER EXE
CUTION, PP177−184, PROCEEDINGS OF SYMPOSIUM ON ARCH
ITECTUAL SUPPORT FOR PROGRAMMING LANGUAGES AND OPE
RATING SYSTEMS, MARCH 1-3-2,1982) in “BRANCH DIS
It is well known as being used as "PLACEMENT". Also, regarding "instruction format of conditional branch instruction", for example, Intel 8086 microprocessor (16-bit microprocessor, 1982 bit May issue, supplement, page 30) It is well known that a relative branch instruction is composed of a branch code and a branch distance, as described in 1.

First, a procedure for executing a normal instruction in the information processing apparatus according to this embodiment will be described.

The instruction code stored in the main memory 11 is fetched through the main memory access bus 15 by the main memory control unit 12 controlled by the instruction prefetching unit 2, and the instruction code bus
It is sent to the instruction register 3 in the instruction decoder 13 through 16. The instruction decoder 13 decodes the instruction code set in the instruction register 3 and sends the address of the operand handled by the instruction to be executed next and the distinction between read and write of the operand to the main memory control unit 12 through the address bus 17. At the same time, information regarding the operation performed by the instruction is sent to the instruction execution unit 14 through the instruction decoder result bus 18. In the main memory control unit 12, for the operand to be read, the operand address sent from the instruction decoder 13 is transferred to the main memory bus.
Access through 15 and prepare the operands required to execute the next instruction. The instruction execution unit 14 fetches the operands prepared by the main memory control unit 12 through the data bus 19 and executes the "operation performed by the instruction" designated through the instruction decode result bus 18 using this. Further, when it is necessary to store the execution result of the instruction in the main memory 11, the execution result is sent to the main memory control unit 12 through the data bus 19.
In the main memory control unit 12, when the operand that needs to be written is sent from the instruction execution unit 14, the operand is sent to the position specified by the operand address sent from the instruction decoder 13 in advance through the main memory bus 15. To write.

When the instruction to be executed is a branch instruction, the instruction decoder 13 sends the branch destination address to the main memory control unit 12 through the address bus 17. The main memory control unit 12 branches by fetching an instruction from the branch destination address.

Next, the procedure of branch prediction of a conditional branch instruction by this information processing apparatus will be shown.

The upper 4 bits of the instruction register 3 are the conditional branch determination unit 20.
When the conditional branch instruction 30 shown in FIG. 4 is judged by the instruction register 3, the output of the conditional branch instruction judgment unit 20 becomes valid, so that the lower 4 bits of the instruction register are processed through the gate 21. It is the output of the branch recognition unit 4. When the output of the conditional branch instruction determination unit 20 is invalid, the output of the conditional branch recognition unit 4 is invalid.

A field indicating the branch distance in the instruction register 3 is input to the branch distance recognition unit 5. When the sign bit 35 of the branch distance is 0, it represents a positive branch distance, and when the sign bit 35 is 1, it represents a negative branch distance. The sign unit 35 controls the selector unit 23. That is,
When the sign bit 35 is 0, the branch distance field is FF1.
When the sign bit is 1, the selector unit 23 switches so that each bit of the field indicating the branch distance is inverted by the negating unit 22 and is input to the FF1 unit 24. The FF1 unit 24 searches from the most significant bit, and outputs the bit position where 1 is first found. By this operation, the effective bit length of the branch distance is output from the FF1 unit 24 and is output together with the sign bit 35 to the branch processing recognition unit 5.

The effective bit length of the branch distance represents the magnitude of the absolute value of the branch distance as a power of 2. That is, when the effective bit length is n, the absolute value of the branch metric from 2 ^n-1, indicates that the range of 2 ⁿ -1.

In the branch prediction table 25 inside the conditional branch prediction unit 6, a value indicating an effective bit length of a branch condition sent from the conditional branch recognition unit 4 and a branch distance sent from the branch distance recognition unit 5 is input as an address. In this table, the conditional branch prediction is set based on the branch condition and the effective bit length of the branch distance from the branch characteristics investigated in advance. The prediction result is defined to be valid when it is expected to branch in the conditional branch instruction. When the value indicating the branch condition sent from the conditional branch recognition unit 4 is valid, the prediction result is output from the branch prediction table 25.
When the input from the conditional branch recognition unit 4 is invalid, the output from the branch prediction table 25 is also invalid. Branch prediction table
The output from 25 is sent to the instruction prefetching unit 2 as the output of the conditional branch prediction unit 6.

Therefore, the validity and invalidity of the prediction result 7 sent to the instruction prefetching unit 2 have the following meanings.

Prediction result 7 is valid: the instruction stored in instruction register 3 is a conditional branch instruction, and it is expected that a branch will occur at this branch instruction.

Prediction result 7 is invalid: It is expected that the instruction stored in the instruction register 3 is not a conditional branch instruction or does not branch with a branch instruction.

When the prediction result 7 output from the conditional branch prediction unit 6 is valid, the instruction prefetching unit 2 controls the main memory control unit 12 to start the instruction fetch from the branch destination address sent through the address bus 17. When the prediction result 7 output from the conditional branch prediction unit 6 is invalid, the main memory control unit 12 is controlled to fetch the subsequent instruction.

By performing such control, it becomes possible to fetch the instruction code before the branch is taken in the conditional branch instruction expected to branch.

(Effect of the Invention) In the information processing apparatus according to the present invention, it is possible to predict a conditional branch instruction with less hardware as compared with a method of performing branch prediction based on history information of branch instructions. Further, in the present invention, the branch prediction can be set according to the size of the branch distance, as compared with the method in which the branch prediction is performed only from the positive or negative of the branch distance. Therefore, it is possible to configure an information processing device capable of executing a conditional branch instruction at high speed with a small amount of hardware.

[Brief description of drawings]

FIG. 1 is a diagram showing components of the present invention, FIG. 2 is a diagram showing a configuration of an information processing device in one embodiment of the present invention, and FIG. 3 is a diagram of an instruction decoder in one embodiment of the present invention. FIG. 4 and FIG. 4 show the configuration of the instruction format of the conditional branch instruction, that is, the information included in the instruction code among the machine language instructions that can be executed by the information processing apparatus according to the embodiment of the present invention, and its designation. It is a figure which shows the method. In the figure, 2 ... Instruction prefetch unit, 3 ... Instruction register 4 ... Conditional branch recognition unit, 5 ... Branch distance recognition unit 6 ... Conditional branch prediction unit, 7 ... Prediction result 10 ... Processor, 11 ... … Main memory 12 …… Main memory control unit, 13 …… Instruction decoder 14 …… Instruction execution unit, 15 …… Main memory access bus 16 …… Instruction code bus, 17 …… Address bus 18 …… Instruction decode Result bus, 19 ... Data bus 20 ... Conditional branch judgment unit, 21 ... Gate 22 ... Negation unit, 23 ... Selector unit 24 ... FF1 unit, 25 ... Branch prediction table 30 ... Conditional branch instruction , 31 ...... Instruction code 32 ...... Value indicating conditional branch 33 ...... Value indicating branching condition 34 ...... Branch distance, 35 …… Sign bit.

Claims (1)

(57) [Claims] 1. An information processing device having an instruction prefetching unit for prefetching instructions and an instruction register for storing instructions, recognizing that the instruction stored in the instruction register is an input and is a conditional branch instruction. A conditional branch recognition unit that outputs a branch condition, a branch distance recognition unit that inputs an instruction stored in an instruction register and outputs a value corresponding to a branch distance,
A conditional branch prediction unit for predicting a branch direction based on outputs from the conditional branch recognition unit and the branch distance recognition unit is provided, and the prediction result output from the conditional branch prediction unit is input to the instruction prefetch unit. An information processing apparatus, wherein the instruction prefetching direction is controlled by the instruction prefetching unit.