JPH01239638A - Information processor performing branch prediction - Google Patents

Abstract

PURPOSE:To remarkably shorten the execution time of a branch instruction by providing an unconditional branch instruction recognition part and an unconditional branch effective table other than an instruction register, a pre-fetch address register, an instruction address table, and a branch destination address table. CONSTITUTION:The unconditional branch instruction recognition part 15 sets the contents of the instruction address table 13 and the branch destination address stable 14 when recognizing that an instruction held at the instruction register 12 is the branch instruction branched unconditionally and in which no branch destination changes dynamically, and also, writes an effective value on the unconditional branch effective table 16. Furthermore, when an address held at the pre-fetch address register 11 exists in the instruction address table 13 and also, a content held at a position in the unconditional branch effective table 16 corresponding to the position of the address in the instruction address table 13 is shown as valid, the instruction following the branch instruction is executed without waiting the determination of branch.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an information processing device that performs branch prediction, and in particular, in order to effectively prefetch instructions, a branch is executed unconditionally, and the branch destination is information that performs branch prediction that speeds up the processing of branch instructions by starting the execution of subsequent instructions before the execution of the branch instruction is completed. [Background Art Regarding Processing Devices] In general, information processing devices perform the following operations for each instruction: importing an instruction code (hereinafter referred to as instruction code), decoding the instruction code (hereinafter referred to as instruction decoding), and executing the instruction. is running the program. Depending on the instruction, operations such as calculating the operand address, accessing the operand from the main memory (hereinafter referred to as "operand read"), or writing back the execution results from the main memory I\ (hereinafter referred to as "operand write") are performed in this pond.・There are also things that require pi.

Generally, in an information processing device, it is necessary to perform instruction processing, instruction decoding, operand address calculation, operand read, operation execution, and operand write.These operations are performed within the information processing device. Since the processing is divided among each part, it is possible to overlap and perform these operations in parallel for several consecutive instructions. Focusing on this point, in order to execute instructions at high speed, it is widely practiced to control operations such that several instructions are processed in parallel. This is called pipeline control, and an information processing device that performs this kind of control is called a pipeline type information processing device.

In order to perform high-speed processing in a pipelined information processing device, each part within the device needs to operate in parallel. In the case of a branch instruction, the instruction cannot be executed until the calculation of the branch destination address is completed, so the pipeline does not work effectively and is an impediment to performance improvement. In order to solve this problem, for branch instructions executed in the past, pairs of the address where the branch instruction exists and the branch destination address are recorded in the instruction address table and the branch destination address table in the information system. , a method is used in which the execution of the instruction when the branch instruction is executed again is started before the calculation of the branch destination address is completed, that is, the branch prediction is performed.

When performing branch prediction, with conventional methods, the instruction following the branch instruction is not executed because the instruction may be prefetched from the wrong address for conditional branch instructions or branch instructions whose branch destination changes dynamically. is put on hold, and the following 128 instructions are resumed after the branch is finalized. In other words, if the branch prediction is correct, processing continues; if it is incorrect, the instruction that has been preempted and suspended is discarded, and execution starts from the result of the branch instruction or the instruction that should be executed. Ta.

[Problem to be solved by the invention]

In the conventional method of recording the address where the branch instruction exists and the branch destination address as a pair, the branch instruction that branches unconditionally and whose branch destination does not change dynamically,
Conditional branches and branch destinations dynamically change (because they were recorded in the instruction address table and branch destination address table without distinguishing between the instruction and the instruction to be hit), the branch was unconditionally branched and the branch destination did not change dynamically. Regarding branch instructions, it was necessary to suspend the processing of subsequent instructions until the execution of the branch instruction was completed and the branch was finalized, and it was also necessary to invest in hardware to cancel the preceding processing. Therefore, for branch instructions that branch unconditionally and the branch destination does not change dynamically, the effect of branch prediction cannot be fully demonstrated, which is a major hindrance to improving performance. [Means for Solving the Problems] In order to solve the above problems in the information processing device according to the present invention, an instruction to be executed branches unconditionally, and
It has an unconditional branch instruction recognition unit that recognizes a branch instruction whose branch destination dynamically changes and does not exist, and an unconditional branch valid table that corresponds to the instruction address table and the branch destination address table5. [Operation] In the information processing device of the present invention, when the executed branch instruction branches unconditionally and the branch destination does not change dynamically, the respective addresses are set in the instruction address table and the branch destination address table. At the same time, when the instruction address table contains the address of the 5-instruction FUE-SOCH which sets the contents of the unconditional branch valid table to be valid, the instruction FUE-ICH is executed from the address recorded in the corresponding branch destination address table. Branch prediction is performed by starting the branch instruction. At this time, if the contents of the unconditional branch valid table corresponding to the instruction address table are valid, instruction execution continues without suspending the processing of the instruction following the branch instruction. 7 [Embodiment] Next, an embodiment of the present invention will be explained in detail with reference to the drawings. Fig. 1 shows an embodiment of the present invention. In FIG. 1, one practical example of the present invention includes a prefetch readdress register 11 that holds the address of the instruction to be prefetched, an instruction register 12 that holds the instruction code, and an address related to the position where the branch instruction exists. It has an instruction address table 13 that holds the instruction address table 13 and a branch destination address table 14 that holds the branch destination address corresponding to the instruction address table 13, and the address held in the prefetch read address register 11 exists in the instruction address table 13. When the address is stored in the instruction register 12, the information processing device prefetches the instruction from the branch destination address held in the position in the branch destination address table 14 corresponding to the position where the address exists in the instruction address table. An unconditional branch instruction recognition unit 15 that recognizes that the instruction branches unconditionally and the branch destination does not change dynamically, and an unconditional branch instruction recognition unit 15 that recognizes that the instruction branches unconditionally and the branch destination does not change dynamically A conditional branch validity table 16 is provided.

When the unconditional branch instruction recognition unit 15 recognizes that the instruction held in the instruction register branches unconditionally and the branch destination does not change dynamically, the unconditional branch instruction recognition unit 15 reads the instruction address table 13 and the branch destination. In addition to setting the contents of the address table 14, a valid value is written to the unconditional branch valid table 16, and furthermore, if the address held in the prefetch read address register 11 exists in the instruction address table 13, and this address is When the content held in the position in the unconditional branch valid table 16 corresponding to the position in the address table 13 indicates that the branch is valid, the instruction following the branch instruction is executed without waiting for the confirmation of one branch. This is what I did.

FIG. 2 shows the inside of the information processing device in this embodiment.
In FIG. 2, a prefetch readdress register 11 is a register that indicates an address where an instruction code that is being prefetched exists. The main memory control unit 20 is a part that accesses the main memory 21. An information processing device having a memory management mechanism or a cache memory inside the main memory control unit 20 is also conceivable.

The instruction decoding section 22 is a section that decodes instructions and calculates addresses, and includes the instruction register 12 and the address calculation section 2.
3. The address calculation unit 23, which has an instruction address register 24, an unconditional branch instruction recognition unit 155, and a branch instruction confirmation recognition unit 25, is configured to recognize the instruction code stored in the instruction register 12 and the instruction code stored in the instruction address register 24. The instruction address table 13, which is the part that calculates the operand address using the registered address and registers in the information processing device, is composed of an associative memory, and all addresses stored therein and the prefetch readdress register 11 are stored in the instruction address table 13. Comparison with the contents is performed. As a result of this comparison, if there is a matching address, the branch destination address corresponding to this address is output from the branch destination address table 14 as a valid value. If there are no matching addresses, the output from this table is invalid. The branch destination address table 14 is composed of a normal memory. In addition,
26 is an address selection section, 27 is an address addition section, and 28 is an instruction execution section.

Next, a procedure for prefetching a command in the information processing apparatus in this embodiment will be described.

The instruction code on the main memory 21 whose location is specified by the address stored in the prefetch readdress register 11 is stored in the instruction register by the main memory control unit 20. When this operation is completed, the address adder 27 calculates the address of the subsequent instruction and inputs it to the address selector 26. The address selector 26 selects the output from the address adder 27 during execution of a normal instruction and sends it to the prefetch readdress register 11. Preemption readdress register 1
1 stores the address sent from the address selection unit 26. As a result, the address stored in the prefetch readdress register 11 indicates the address at which the instruction is being fetched.

At this time, since the output from the instruction address table 13 is invalid, the contents of the prediction flag are always set to invalid. The instruction decoding unit 22 decodes the instruction code stored in the instruction register 12.

When the prediction flag is invalid, the decoded result is sent to the instruction execution unit 28 without being suspended. Instruction execution unit 28
Then, the instruction is executed according to the decoding result in the instruction decoding section 22.

When the instruction to be executed is recognized by the instruction decoding unit 22 as a branch instruction, a branch destination address is calculated in the address calculation unit 23 according to the instruction code stored in the instruction register 12.3 This address is the instruction address. - Sent to register 24 and address selection section 26. In the address selection section 26, the address calculation section 23
Readdress register 11 that preempts the address sent from
Branching is performed by sending the Also, at this time, the value of the instruction address register is recorded in the instruction address table 13, the output of the address calculation unit 23 is recorded in the branch destination address table 14, and the output of the unconditional branch instruction recognition unit 15 is recorded in the unconditional branch valid table 16. Ru.

- Once executed, the instruction address table 13 is executed according to the procedure shown above.
The procedure for re-executing the instructions stored in the branch destination address table 14 is as follows.

Such a branch instruction is herein referred to as a re-execute unconditional branch instruction.The address stored in the prefetch readdress register 11 indicates the address from which the instruction is fetched, but this address is always the instruction address. It is compared with all the addresses recorded in Table 13. This is called a search operation, and if an address that matches the address stored in the prefetch readdress register 11 exists in the instruction address table 13, the search operation is considered to have been successful.A re-execution unconditional branch instruction is prefetched. Then, since the search operation using the address stored in the prefetch read address register 11 is successful, the branch destination address corresponding to the matching address is output as a valid value from the branch destination address table 14,
It is sent to the address selection section 26. The address selection unit 26 receives the branch destination address output as a valid value and sends it to the prefetch read address register 11. In the main memory control unit 20, the instruction is fetched from the address set in the pre-fetch rear address register 11, so the instruction fetch is performed from the branch destination, and from this point on, the instruction code is pre-fetched by the above-mentioned instruction pre-fetch procedure. will be held. Furthermore, if the search operation is successful, the values of the two prediction flags are set according to the values recorded in the unconditional branch validity table 16.

That is, when the values recorded in the unconditional branch validity table 16 are invalid, the values of the two prediction flags become values indicating that the branch is undetermined, and when the values recorded in the unconditional branch validity table 16 are valid, the values of the prediction flags are The two values are values that indicate branch determination. If one search operation is successful and the two prediction flags are set to branch undetermined, this indicates that branch prediction has been performed for a one-conditional branch instruction or a branch instruction whose branch destination dynamically changes. There is. In this case, the instruction decoding section suspends delivery of the instruction decoding result to the instruction execution section 28 until the branch instruction confirmation recognition section recognizes that the branch instruction has been finalized. In other words, execution of the instruction is suspended.

On the other hand, if the values of the two prediction flags for which the search operation was successful are set to branch confirmed, it means that branch prediction was performed for a branch instruction that branches unconditionally and whose branch destination does not change dynamically. It shows. In the instruction decoding section 22, when the value of the predicting flag 29 is a branch confirmed, the instruction decoding result is passed to the instruction execution section without being suspended, and the instruction following the branch instruction is executed.

〔Effect of the invention〕

As explained above, the present invention enables execution of instructions following the branch instruction without suspending processing when branch prediction is performed for a branch instruction that branches unconditionally and the branch destination does not change dynamically. , it becomes possible to configure an information processing device in which the execution time of such a branch instruction is significantly shortened.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the configuration requirements in an embodiment of the present invention. FIG. 2 is a program diagram showing one embodiment of the present invention. Destination address table, 15...Unconditional branch recognition unit, 16...
・Unconditional branch valid table, 20...main memory control unit, 21・
...Main memory, 22...Instruction decoding section, 28...Instruction execution section-

Claims (1)

[Claims] Pre-preempt read address which holds the address of the instruction to pre-fetch.
It has a register, an instruction register that holds the instruction code, an instruction address table that holds the address related to the location of the branch instruction, a branch destination address table that holds the branch destination address corresponding to the instruction address table, and a preemptive read address. - When the address held in the register exists in the instruction address table, the instruction is prefetched from the branch destination address held at the position in the branch destination address table corresponding to the position where the address exists in the instruction address table. In an information processing device, an unconditional branch instruction recognition unit that recognizes that an instruction held in an instruction register is a branch instruction that branches unconditionally and whose branch destination does not change dynamically, and an instruction address table and branch An unconditional branch valid table is provided corresponding to the destination address table, and the instruction held in the instruction register is branched unconditionally by the unconditional branch instruction recognition unit, and the branch destination does not change dynamically. When it is recognized that this is the case, the contents of the instruction address table and branch destination address table are set, a valid value is written to the unconditionally valid table, and the address held in the prefetch read address register is written to the instruction address table. If the address exists and the content held in the position in the unconditional branch valid table corresponding to the position in the instruction address table indicates that the address is valid, the branch instruction is executed without waiting for the branch to be confirmed. An information processing device that performs branch prediction characterized by executing subsequent instructions.