JP2944335B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a branch control system in a processor, and more particularly to an instruction buffer for storing a prefetch instruction, an instruction decode circuit, an instruction execution unit, a prefetch control circuit 4, a dynamic address conversion circuit, and the like. The present invention relates to an information processing apparatus having an instruction code memory, performing dynamic address translation (DAT), and performing prefetching of instructions.

[0002]

2. Description of the Related Art At present, the speed of branch instructions in processors is increasing, and in processors, advance control such as pipeline processing of instructions is becoming common. In such precedent control of instructions, when a continuous instruction sequence is executed, it operates very efficiently and at high speed, but when the sequence of instructions changes due to a branch instruction or the like, the instruction is executed in advance. Since instructions are wasted, if a large number of branch instructions are issued, the performance of the processor is reduced. Therefore, in order to suppress the performance degradation, prediction of the branch destination and instruction fetch for the branch address are performed. In such a processor that prefetches an instruction at a branch destination, address translation (DA) is performed on the instruction fetch at the branch destination.
T) exceptions (TLB fault page fault protection exception, etc.) may occur. It is necessary that such an exception to the instruction at the branch destination does not occur when the branch condition is not satisfied by the conditional branch instruction.

Therefore, in a conventional processor for fetching an instruction at a branch destination, the DAT exception processing for the instruction fetch at the branch destination is not performed until the condition determination is completed. Therefore, when an exception related to DAT occurs during the instruction fetch at the branch destination, the subsequent instruction fetch is suppressed, and the state at that time is retained so that the exception processing can be performed correctly when the branch condition is satisfied. It is necessary.

[0004]

Therefore, in a processor that fetches an instruction at a branch destination, high-speed DAT exception detection and instruction fetch control are required in order to suppress the instruction fetch immediately after the DAT-related exception occurs. Therefore, the amount of hardware increases and the machine cycle decreases.

Accordingly, the present invention provides a method for fetching an instruction even when an error relating to instruction conversion occurs in an instruction fetch at a branch destination.
It is an object of the present invention to provide an information processing apparatus which can eliminate the need to hold the state at that time, reduce the amount of hardware, and speed up the machine cycle.

[0006]

According to the present invention, there is provided an information processing apparatus for performing an advanced fetch of an instruction, the information processing apparatus being configured to store a branch destination address of a branch instruction obtained by the advanced fetch. A first holding unit for holding, and a first holding unit when the branch condition of the branch instruction is satisfied and when an exception accompanying the address translation process occurs while the branch condition is undetermined. And a prefetch control unit that prefetches instructions again from the branch destination address stored in the prefetch control unit.

In the present invention, there is provided a second holding unit for holding a preceding fetch address when the branch destination address is determined, wherein the prefetch control unit does not satisfy a branch condition of the branch instruction. In this case, the instruction is prefetched from the address held in the second holding unit.

Further, according to the present invention, when the branch condition of the branch instruction is satisfied and no exception occurs due to the address conversion processing, the branch destination address held in the first holding unit is read from the branch destination address. The prefetched instruction is executed by the instruction execution unit while the prefetched instruction is continued.

That is, as shown in FIG. 1, the present invention corresponds to an instruction buffer (1) for storing a prefetch instruction, an instruction decode circuit (2), an instruction execution unit (3), and the prefetch control unit. A prefetch control circuit (4);
Dynamic address translation circuit (5) and instruction code memory (6)
Performing dynamic address translation (DAT),
In a processor that prefetches an instruction, the instruction buffer 1 has branch destination instruction sequence holding means IB for holding a branch destination instruction sequence, and the instruction decode circuit 2 determines the branch address and evaluates the branch condition. The prefetch control circuit 3 has a branch destination register B corresponding to the first holding unit for holding the branch address and a continuous instruction sequence starting with the branch address. Holding register C to fetch during valid period
And a fetch address register E corresponding to the second holding unit for holding the preceding fetch address at the time when the branch destination address is determined. An exception detection flag D that holds that an exception accompanying the address translation circuit has occurred while indicating that the instruction is present. When the conditional branch instruction is executed, the holding register C restarts the fetch of the branch destination instruction, and the branch condition is satisfied. If the condition is not satisfied, the preceding fetch of the instruction is restarted from the address held in the fetch address register E, and if the branch condition is satisfied and the exception detected by the exception detection flag D does not involve the address conversion circuit 5 Sets the branch address indicated by the branch destination register B in the program counter, and stores the branch instruction sequence holding means I
A case where the instruction sequence of B is the data of the preceding fetch and the instruction sequence following the instruction fetched by the holding register C is prefetched, while the exception detection flag D indicates that the exception associated with the address conversion circuit 5 has occurred. Does not use the instruction sequence of the branch destination instruction sequence holding means IB,
Is to redo the preceding fetch of the instruction from the branch address indicated by.

[0010]

According to the present invention, when there is no branch instruction in the output of the instruction buffer 1 in the instruction decoding circuit 2, the prefetch control circuit 3 updates the address of the holding register C and outputs the output of the holding register C to the address conversion circuit 5
, And the memory 6 receives the corresponding physical address, and sets the instruction data in the instruction buffer 1. This is repeated to perform prefetch.

Here, when the address translation circuit 5 detects an exception accompanying the address translation, the address translation circuit 5 sends an exception detection signal from the exception detection flag D to the instruction execution unit 3, and the instruction execution unit 3 No. 3 interrupts execution of an instruction and performs interrupt processing for an exception. When the instruction decode circuit 2 detects a branch instruction at the output of the instruction buffer 1, the branch address is calculated, the branch destination address is set in the branch destination register B and the holding register C of the prefetch control circuit 4, and the branch reservation flag A is set. Turn ON. The prefetch control unit 4 sends an instruction address corresponding to a branch destination address to the address conversion circuit 5. The address conversion circuit 5 sends the corresponding physical address to the memory 6, and the corresponding instruction code is set in the instruction buffer 1.

The prefetch of the branch destination instruction is continuously performed while the instruction execution unit 3 determines the branch condition. If an exception is detected by the instruction execution unit 3 while the reservation flag A is ON, the exception detection flag D of the address conversion circuit 5 is set. The operation when the branch instruction is executed in the instruction execution unit 3 and the branch is determined is as follows.

I When no exception is generated (D = OFF) and the branch condition is not satisfied: The address held in the fetch address register E is set to C, the reservation flag A is reset, and the processing is continued. II When the branch condition is satisfied without occurrence of an exception (D = OFF) Prefetch is continuously performed, the reservation flag A is reset, and the instruction code corresponding to the address held in the branch destination register B is taken out from the instruction decode circuit 2, It is sent to the instruction execution unit 3.

III When an exception occurs (D = ON) and the branch condition is not satisfied The address held in the fetch address register E is set in the holding register C, the reservation flag A and the exception detection flag D are reset, and the processing is continued. IV When an exception occurs (D = ON) and the branch condition is satisfied The address held in the branch destination register B is held in the holding register C
To reset the reservation flag A and the exception detection D, take out the instruction code corresponding to the address held in the branch destination register B from the instruction decode circuit 2 and send it to the instruction execution unit 3. By re-executing the instruction fetch, an exception of the address translation is detected again, and an interrupt signal for exception processing is transmitted to the instruction execution circuit 3.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the information processing apparatus according to the present invention will be described below. 1 to 5 show an embodiment of an information processing apparatus according to the present invention. 1 and 2, 1 is 2
System buffers IBA11, IBB12, TFF (toggle flip-flop) 13, and multiplexer (MP
X) 14, an instruction buffer 2, a decoder 21, a JK flip-flop 22 that is a reservation flag A, and a branch (BR) non-branch (NBR) signal from the instruction execution unit 3, and a logic is applied to the K terminal of the flip-flop 22. An instruction decode circuit 3 comprising an AND gate 23 for outputting a sum, 3 denotes an instruction execution unit. Reference numeral 4 denotes a holding register C for holding and updating a prefetch address of an instruction, a register B for holding a branch destination address at the time of branching, a fetch address register E for holding a fetch address when the branch destination address is determined, and a multiplexer (MPX). ) 41 and a prefetch control circuit comprising an incrementer 42 for incrementing an address.
1. The decoder 52 comprises a JK flip-flop 53 which is an exception detection flag D, an AND gate 54, an inverter 55, and an AND gate 56 which generates an interrupt signal to the instruction execution unit 3, and converts a logical address into a physical address and a DAT. An address translation circuit 6 for detecting the occurrence of an exception in translation is a memory that stores an instruction code and transfers an instruction code corresponding to a physical address input from the address translation circuit to the instruction buffer 1. .

Next, the operation of the information processing apparatus according to this embodiment will be described. First, in the instruction buffer 1, the buffer I
The BA11 and the IBB12 are selected by the MPX14 by the TFF13 (toggle flip-flop). Each time a branch is taken, the value is inverted, the instruction buffer on the opposite side is selected and output to the instruction decode circuit 2.

The decoder 21 generates a branch destination address of a branch instruction from the input instruction code, detects a branch instruction, and generates a branch detection signal indicating that a valid branch destination address has been generated. Turns ON, the reservation flag A (JK flip-flop 22) is set. The reservation flag A is reset when the K input is turned on when the branch condition of the branch instruction is determined. Further, it extracts an instruction code from the output of the MPX 14 and transfers the instruction code to the instruction execution unit 3.

The instruction execution unit 3 outputs a signal BR when a branch condition is satisfied at a branch condition determination timing in a branch instruction, and outputs an NBR to the instruction decode circuit 2 when the branch condition is not satisfied. When the branch detection signal is turned on, the prefetch control circuit 4 sets the branch destination address in the branch destination register B, and at the same time, selects the branch destination address as the input of the holding register C by the MPX 41 and sets the branch destination address in the holding register C. You. In addition,
When it becomes N, the output of the holding register C is copied to the fetch address register E.

When the signal NBR is turned on, M
PX41 selects fetch address register E,
The value of the fetch address register E is set in the holding register C. When the signal is further turned on, the output of the branch destination register B is selected by the MPX 41, and the value of the branch destination register B is set in the holding register C. At other times, the signal that updates the holding register C is MPX
41, the value of the holding register C is updated every time the prefetch is performed.

In the address conversion circuit 5, the TLB 51 converts a logical address into a physical address, and at the same time, the decoder 6 detects a TLB fault for the address and outputs a TLBF signal. Reservation flag A is OFF
In the case of (1), the TLB fault signal TLBF becomes an interrupt signal to 3 as it is, but interrupts are suppressed while A = 1. When TLBF is turned on while A = 1, the exception detection flag D (JK flip-flop 53) is set, and a signal is output when the branch is taken.

These operations will be described based on actual examples. FIGS. 3 to 5 are timing charts showing the operation of the branch control method in the processor according to the embodiment.
First, in the case where no TLB fault (exception) occurs at the branch destination, and when branching normally, FIG.
As shown in (1), the reservation flag A is set to O by the branch detection signal from the decoder 21 during the execution of the IBA of the instruction buffer 1.
N, and the holding register C continuously performs prefetch. Then, the reservation flag A is reset by the BR signal from the instruction execution unit 3, and the instruction code IBB corresponding to the address held in the branch destination register B is decoded by the instruction decoding circuit 2.
The MPX 14 is switched by the TFF 13, and the switched instruction code IBB is transmitted from the instruction buffer 1 to the instruction execution unit 3 from the decoder 21. Thereby, the branch is performed normally.

If the branch is not taken, the reservation flag A is reset by the NBR signal as shown in FIG. 3 (2), the MPX1 is not switched, and the instruction code I is not changed.
BA is output to the instruction execution unit 3. TL at branch destination
If a B fault occurs, this embodiment operates as follows.

FIG. 4 shows a case where a TLB fault occurs at the branch destination and the branch is not taken. IBA of instruction buffer 1
Is executed, the reservation flag A is turned on by the branch detection signal from the decoder 21, and the prefetch is continuously performed using the address held in the holding register C. TLB on the way
When the fault signal is output from the decoder, the address held in the fetch address register E is stored in the holding register C.
Set to. However, the reservation flag A and the exception detection flag D are reset together with the output of the NBR signal, and the processing is continued.

Next, a TLB fault occurs at the branch destination,
FIG. 5 shows the case of branching. IBA of instruction buffer 1
Is executed, the reservation flag A is turned on by the branch detection signal from the decoder 21, and the prefetch is continuously performed using the address held in the holding register C. TLB on the way
When the fault signal is output from the decoder 52, the address held in the fetch address register E is set in the holding register C. Further, the address held in the branch destination register B is set in the holding register C, and the reservation flag A
And resets the exception detection D, retrieves the instruction code corresponding to the address held in the branch destination register B from the instruction decode circuit 2, and sends it to the instruction execution unit 3.

Then, the re-execution of the branch instruction causes the decoder 52 to detect the TLBF. At this time, since the reservation flag has been reset, the TLBF signal from the decoder 52 passes through the AND gate 56, is transmitted to the instruction execution circuit 3 as an interrupt signal INT for exception processing, and interrupt processing is performed.

[0026]

As described above, according to the present invention,
In the execution of the conditional branch instruction, the information processing apparatus restarts the fetch of the branch target instruction by the holding register C, and holds the information in the fetch address register E as the second holding unit when the branch condition is not satisfied. When the prefetch of the instruction is resumed from the address and the branch condition is satisfied, and the exception detection flag D does not include the exception associated with the address conversion circuit 5, the branch destination register B serving as the first holding unit is read. The branch address shown is set in the program counter, the instruction sequence of the branch destination instruction sequence holding means IB is used as prefetch data, and the instruction sequence following the instruction fetched by the holding register C is prefetched, while the exception detection flag D
Indicates that the exception associated with the address translation circuit 5 has occurred, the instruction fetch of the instruction is performed again from the branch address indicated by the branch destination register B without using the instruction sequence of the branch instruction storage unit IB. If an exception of address translation occurs in the prefetch of the branch destination instruction before the branch condition is determined, no special operation such as suppression of prefetch is required, and after the branch condition is determined. The re-execution has an effect that simplification and high-speed branch control and prefetch control can be realized.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a diagram showing an embodiment of an information processing apparatus according to the present invention.

FIG. 3 is a timing chart showing an operation of the information processing apparatus shown in FIG. 2;

FIG. 4 is a timing chart showing an operation of the information processing apparatus shown in FIG. 2;

FIG. 5 is a timing chart illustrating an operation of the information processing apparatus illustrated in FIG. 2;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Instruction buffer 2 Instruction decode circuit 3 Instruction execution part 4 Prefetch control circuit 5 Dynamic address conversion circuit 6 Memory

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toru Watanabe 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Takumi Maruyama 1015 Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited ( 72) Inventor Takumi Takeno 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Shinya Kato 1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Pornshaichswanna Paisan 1015 Ueodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Within Fujitsu Limited (56) References JP-A-63-12030 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 9 / 38

Claims (3)

(57) [Claims] (1)Information processing device for prefetching instructions
And Branch destination address of the branch instruction obtained by the preceding fetch
A first holding unit for holding the dress, When the branch condition of the branch instruction is satisfied, and
An exception occurred during the address translation process while the condition was undetermined.
The branch destination address held in the first holding unit.
Prefetch system that prefetches instructions again from the
Obe and An information processing apparatus comprising: 2. A destination when the branch destination address is determined.
A second holding unit for holding a row fetch address, The prefetch control unit determines that a branch condition of the branch instruction is
If not established, the address held in the second holding unit
Prefetching instructions from the address
The information processing device according to claim 1. 3. When the branch condition of the branch instruction is satisfied.
And no exception has occurred due to the address translation process
In the case, the branch destination address held in the first holding unit
When the instruction execution unit executes the instruction fetched earlier from
In both cases, the preceding fetch is continued.
3. The information processing apparatus according to 1 or 2.