JPH06295243A - Data processor - Google Patents

Abstract

PURPOSE:To avoid useless power consumption in other stage being in a stand-by state, in the case a comparatively long time is required for the processing in a certain stage, in the data processor for executing the pipeline processing. CONSTITUTION:The data processor is provided with clock supply selecting circuits 131-134 which can select whether supply of a clock to each pipeline processing stage 101-103, 106 and 107 is executed or stopped, or a power source supply selecting circuit which can select whether power feeding is executed or not, and constituted so that at the time of processing of a specific instruction which requires a compatively long time for the processing in an E stage 107 being a specific pipeline processing stage, supply of a clock or power feeding to each stage 101-103, and 106 of the pre-stages of its stage 107.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device,
In particular, the present invention relates to a low power consumption type data processing apparatus, and more specifically to a data processing apparatus capable of reducing the power consumption during the waiting time at each stage when performing pipeline processing.

[0002]

2. Description of the Related Art A block diagram of FIG. 13 shows an example of the configuration of a microprocessor of a conventional data processing apparatus having a plurality of stages for pipeline processing. FIG. 13 shows a basic pipeline processing mechanism of a 5-stage structure in the microprocessor 3.

That is, an instruction prefetch stage (IF stage) 101 for prefetching an instruction from an external memory (not shown), and a decode stage (D for decoding an instruction
Stage) 102, operand address calculation stage (A stage) 103 for performing operand address calculation, micro
The five stages are an operand prefetch stage (F stage) 106 for accessing the ROM 121 and operand prefetch, and an instruction execution stage (E stage) 107 for executing an instruction.

Reference numeral 1 denotes a clock supply wiring for supplying a clock to each stage, and 2 denotes a power supply wiring for supplying a power to each stage.
The E stage 107 is provided with a single-stage store buffer 120. Store buffer on this E stage 107
Since 120 is provided, the microprocessor 3 shown in FIG. 13 actually exhibits a pipeline processing effect of five or more stages.

Further, the F stage 106 includes a micro ROM 121.
It includes a micro ROM access stage (R stage) 104 for accessing the memory and an operand prefetch stage (OF stage) 105 for prefetching operands.
In the conventional data processing device having the microprocessor 3 as described above, the instruction to be processed is processed into a plurality of pipeline processing units (stage code) so that balanced pipeline processing can be performed in each stage in the instruction processing. Disassemble and process.

By the way, the IF stage 101 to the D stage
The information passed to 102 is the instruction code 108 itself.
The information passed from the D stage 102 to the A stage 103 is
There are two types, information about the operation specified by the instruction and information about the calculation of the operand address.
It is processed as a code 109 and a stage code called A code 110.

The information passed from the A stage 103 to the F stage 106 is of two types: information including the entry number of the microprogram routine, parameters to the microprogram, etc., and information including operand address and access method instruction information. Are processed as stage codes called R code 111 and F code 112, respectively. There are two types of information passed from the F stage 106 to the E stage 107: information including operation control information and literals, and information including operands, operand addresses, etc. These are called E code 113 and S code 114, respectively. Is processed as a stage code.

FIG. 14 is a schematic diagram showing an example of an instruction sequence to be processed by the data processing apparatus shown in FIG. 13 described above, and FIG. 15 is an instruction processed at each stage in each pipeline processing stage. It is a schematic diagram which shows the state of. The "smov.b" of the instruction 401 is a string transfer instruction with an indexing condition. Transfer is performed in string units, and the indexing condition is checked each time one transfer is completed.
If the indexing condition is met, the instruction ends without further processing.

The instruction sequence shown in FIG. 14 is illustrated below.
The operation of the data processing apparatus having the microprocessor 3 shown in 13 for processing will be described. First, the instruction 401 is fetched from the external memory (not shown) to the IF stage 101. The instruction 401 fetched by the IF stage 101 is the D stage 102 as the instruction code 108.
Transferred to. This state is shown in Fig. 15 (a).

The D stage 102 decodes the instruction 401, and the decoded result is the D code 109 and the A code 110.
Is transferred to the A stage 103 as. Also, the next instruction 40
2 is fetched from external memory to IF stage 101 and D
Transferred to stage 102. This state is shown in Fig. 15 (b).

At the A stage 103, when the processing of the instruction 401 is completed, the processing result is transferred to the F stage 106 as R code 111 and F code 112. Also, instruction 402 is D
Transferred from the stage 102 to the A stage 103. Order 40
3 is fetched from external memory to IF stage 101 and D
Transferred to stage 102. This state is shown in Fig. 15 (c).

When the processing of the instruction 401 is completed in the F stage 106, the processing result is transferred to the E stage 107 as the E code 113 and the S code 114. Also, instruction 402 is A
It is transferred from the stage 103 to the F stage 106. Order 40
3 is transferred from the D stage 102 to the A stage 103.
The next instruction 404 is fetched from the external memory to the IF stage 101 and transferred to the D stage 102. This state is a figure
It is shown in 15 (d).

At the E stage 107, when the processing of the instruction 401 is completed, if the instruction 401 involves memory writing, the write data is transferred to the store buffer 120.
Further, the instruction 402 is transferred from the F stage 106 to the E stage 107. Instruction 403 is A stage 103 to F stage 1
Transferred to 06. Instruction 404 is transferred from D stage 102 to A stage 103. The next instruction 405 is fetched from the external memory to the IF stage 101 and transferred to the D stage 102. This state is shown in Fig. 15 (e).

[0014]

By the way, the above-mentioned instruction
The processing in the E stage 107 of 401 may take a relatively long time. In such a case, the IF stage 101, the D stage 102, the A stage 103, and the F stage 10 in the preceding stage
6 is in a standby state until the processing in E stage 107 is completed. Power and clock are supplied to each stage in the standby state via the power supply wiring 2 and the clock supply wiring 1, and power is wasted.

The present invention has been made in view of the above circumstances, and in a data processing apparatus for performing pipeline processing, when a relatively long time is required for processing at a certain stage, another standby state is set. The purpose is to be able to avoid unnecessary power consumption in a certain stage.

[0016]

A data processing apparatus according to the present invention is basically a clock supply selecting means capable of selecting whether to supply or stop a clock to each pipeline processing stage, or Equipped with a power supply selection means that can select whether to perform power supply or stop,
When a specific instruction that requires a relatively long time for processing in a certain pipeline processing stage is processed, clock supply or power supply to each stage preceding the stage is stopped.

The first invention of the data processing apparatus of the present invention is as follows:
Specific instruction detecting means for storing an instruction code of a specific instruction in advance and detecting it when the instruction is decoded, next instruction address calculating means for calculating the address of the instruction next to the instruction being processed, and each pipeline It is provided with a clock supply selecting means for selecting whether to supply a clock to the processing stage or for stopping it, and an instruction fetch address storing means for storing an address of an instruction to be fetched next from the outside.

A second invention of the data processing apparatus of the present invention is as follows:
Specific instruction detecting means for storing an instruction code of a specific instruction in advance and detecting it when the instruction is decoded, next instruction address calculating means for calculating the address of the instruction next to the instruction being processed, and each pipeline It is provided with a clock supply selection means for selecting whether to supply power to the processing stage or to stop the power supply, and an instruction fetch address storage means for storing the address of an instruction to be fetched next from the outside.

A third invention of the data processing apparatus of the present invention is
Specific instruction detection means for storing the address of a specific instruction in advance and detecting it when the instruction is fetched, next instruction address calculation means for calculating the address of the instruction next to the instruction being processed, and each pipeline processing It is provided with a clock supply selection means for selecting whether to supply a clock to the stage or to stop it, and an instruction fetch address storage means for storing an address of an instruction to be fetched next from the outside.

A fourth invention of the data processing apparatus of the present invention is
Specific instruction detection means for storing the address of a specific instruction in advance and detecting it when the instruction is fetched, next instruction address calculation means for calculating the address of the instruction next to the instruction being processed, and each pipeline processing The stage is provided with a power supply selection means for selecting whether to supply power to the stage or to stop the power supply, and an instruction fetch address storage means for storing the address of an instruction to be fetched next from the outside.

A fifth aspect of the data processing apparatus of the present invention is
Specific instruction detecting means for storing an instruction code of a specific instruction in advance and detecting it when the instruction is decoded, next instruction address calculating means for calculating the address of the instruction next to the instruction being processed, and each pipeline Clock supply selecting means for selecting whether to supply or stop the clock to the processing stage; instruction fetch address storing means for storing the address of an instruction to be fetched next from the outside;
Each pipeline processing stage is provided with a static storage means for storing the processing result of each.

A sixth invention of the data processing apparatus of the present invention is
Specific instruction detection means for storing the address of a specific instruction in advance and detecting it when the instruction is fetched, next instruction address calculation means for calculating the address of the instruction next to the instruction being processed, and each pipeline processing Power supply selection means for selecting whether to supply power to the stage or stop, instruction fetch address storage means for storing the address of the next instruction to be fetched externally, and always separate from each pipeline processing stage It is provided with a static storage unit that is supplied with power and stores each processing result.

[0023]

According to the first aspect of the data processor of the present invention, each pipeline processing stage which is in a standby state when the specific instruction detecting means detects that a specific instruction is processed by its instruction code. The supply of the clock to the pipeline processing stage is stopped by the clock supply selecting means, and the supply of the clock to each pipeline processing stage is restarted by the clock supply selecting means when the processing in the specific pipeline processing stage is completed. The next instruction is fetched by calculating the address of the instruction by the next instruction address calculation means and supplying it to the instruction fetch address storage means.

In a second aspect of the data processing apparatus of the present invention, each pipeline processing stage which is in a standby state when the specific instruction detecting means detects that a specific instruction is processed by the instruction code thereof. The power supply to the pipeline processing stages is restarted by the power supply selecting means when the power supply to the pipeline processing stages is stopped by the power supply selecting means, and the processing in the specific pipeline processing stage is completed. The next instruction is fetched by being calculated by the next instruction address calculation means and given to the instruction fetch address storage means.

In the third aspect of the data processor of the present invention, each pipeline processing stage which is in a standby state when the specific instruction detecting means detects that a specific instruction is processed by its instruction address. The supply of the clock to the pipeline processing stage is stopped by the clock supply selecting means, and the supply of the clock to each pipeline processing stage is restarted by the clock supply selecting means when the processing in the specific pipeline processing stage is completed. The next instruction is fetched by calculating the address of the instruction by the next instruction address calculation means and supplying it to the instruction fetch address storage means.

According to a fourth aspect of the data processor of the present invention, each pipeline processing stage which is in a standby state when the specific instruction detecting means detects that a specific instruction is processed by its instruction address. The power supply to the pipeline processing stages is restarted by the power supply selecting means when the power supply to the pipeline processing stages is stopped by the power supply selecting means, and the processing in the specific pipeline processing stage is completed. The next instruction is fetched by being calculated by the next instruction address calculation means and given to the instruction fetch address storage means.

In a fifth aspect of the data processor of the present invention, each pipeline processing stage which is in a standby state when the specific instruction detecting means detects that a specific instruction is processed by the instruction address thereof. The supply of the clock to the pipeline processing stage is stopped by the clock supply selecting means, and the supply of the clock to each pipeline processing stage is restarted by the clock supply selecting means when the processing in the specific pipeline processing stage is completed. The next instruction is fetched by calculating the address of the instruction by the next instruction address calculation means and giving it to the instruction fetch address storage means, and the subsequent processing is started in each stage according to the contents stored in each static storage means. It

According to a sixth aspect of the data processor of the present invention, each pipeline processing stage which is in a standby state when the specific instruction detecting means detects that a specific instruction is processed by its instruction address. The power supply to the pipeline processing stages is restarted by the power supply selecting means when the power supply selecting means stops the power supply and the processing in the specific pipeline processing stage ends, and the address of the next instruction is The next instruction is fetched by being calculated by the next instruction address calculation means and given to the instruction fetch address storage means, and subsequent processing is started in each stage according to the contents stored in each static storage means.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments thereof. FIG. 1 is a block diagram showing the configuration of an embodiment of the first invention of the data processing apparatus according to the present invention. Note that in FIG. 1, the same reference numerals as those in FIG. 13 referred to in the description of the conventional example described above indicate the same or corresponding portions. FIG. 1 shows a basic pipeline processing mechanism having a five-stage structure in the microprocessor 3.

That is, an instruction prefetch stage (IF stage) 101 for prefetching an instruction from an external memory (not shown), and a decode stage (D for decoding an instruction
Stage) 102, operand address calculation stage (A stage) 103 for performing operand address calculation, micro
The five stages are an operand prefetch stage (F stage) 106 for accessing the ROM 121 and operand prefetch, and an instruction execution stage (E stage) 107 for executing an instruction.

Reference numeral 1 indicates each stage 101, 102, 103, 1
The clock supply wiring for supplying a clock to 06 is shown. The microprocessor 3 of the data processing device of the present invention is also provided with the power supply wiring 2 shown in the conventional example of FIG. 13 and the power supply wiring to each stage from the power supply wiring 2 to each stage 101. , 102, 103, 10
The power supply to 6 and 107 is always performed, but the power supply wiring 2 and the power supply lines to the respective stages are omitted.

The E stage 107 has a single-stage store buffer 120. Since the E stage 107 is provided with the store buffer 120, the microprocessor 3 shown in FIG. 13 actually exhibits a pipeline processing effect of five or more stages.

Further, the F stage 106 includes a micro ROM 121.
It includes a micro ROM access stage (R stage) 104 for accessing the memory and an operand prefetch stage (OF stage) 105 for prefetching operands.
In the conventional data processing device having the microprocessor 3 as described above, the instruction to be processed is processed into a plurality of pipeline processing units (stage code) so that balanced pipeline processing can be performed in each stage in the instruction processing. Disassemble and process.

By the way, the IF stage 101 to the D stage
The information passed to 102 is the instruction code 108 itself.
The information passed from the D stage 102 to the A stage 103 is
There are two types, information about the operation specified by the instruction and information about the calculation of the operand address.
It is processed as a code 109 and a stage code called A code 110.

There are two types of information passed from the A stage 103 to the F stage 106: information including entry numbers of microprogram routines, parameters to the microprogram, etc., and information including operand addresses and access method instruction information. Are processed as stage codes called R code 111 and F code 112, respectively. There are two types of information passed from the F stage 106 to the E stage 107: information including operation control information and literals, and information including operands, operand addresses, etc. These are called E code 113 and S code 114, respectively. Is processed as a stage code.

The above-mentioned configuration is similar to that of the conventional data processing apparatus whose configuration is shown in FIG. 13, but the data processing apparatus of the present invention includes the IF stages other than the E stage 107.
101, D stage 102, A stage 103 and F stage 106
Each of them is provided with a clock supply selection circuit 131, 132, 133, 134. These clock supply selection circuits 131, 1
32, 133, 134 supply the clock from the clock supply wiring 1 to the respective stages 101, 102, 103, 106,
Alternatively, it can be selectively stopped.

Specifically, each clock supply selection circuit 131,
When a detection signal 136 is given from an instruction decoding unit 135 described later, 132, 133, 134 stop the clock supply from the clock supply wiring 1 to the respective stages 101, 102, 103, 106, and vice versa. When the processing end signal 138 from the store buffer 120 is supplied, the clock supply wiring 1
From each stage 101, 102, 103, 106 to the clock.

Further, the IF stage 101 is provided with an instruction fetch address register 130 which indicates an address of an instruction to be fetched from an external memory (not shown).

The D stage 102 decodes the instruction code 108 fetched from the external memory by the IF stage 101, and a specific instruction (hereinafter referred to as a long-time processing instruction) which takes a long time to process at the stage or at the stage. An instruction decoding unit 135 for detecting whether or not there is is provided. The instruction decoding unit 135 checks whether or not the instruction code is an instruction code of some long-time processing instructions stored in advance when the instruction is decoded. If the instruction code is a long-time processing instruction,
The instruction decoding unit 135 includes an IF stage 101 and a D stage 10
Clock supply selection circuits 131 and 132 of 2 and A stage 103
The detection signal 136 is output to.

The E stage 107 is provided with a next instruction fetch address generator 137. The next-instruction-fetch-address generating unit 137 then outputs the IF
Generates the address of the instruction to be fetched into stage 101. The address of the instruction generated by the next instruction fetch address generation unit 137 is given to the instruction fetch address register 130 of the IF stage 101.

Further, when the processing of the long-time processing instruction in the store buffer 120 is completed as described above, a processing end signal 138 indicating that is output from the store buffer 120 to the next instruction fetch address generation unit 137 and each clock. Applied to supply selection circuits 131, 132, 133, 134. When this processing end signal 138 is given, each clock supply selection circuit
As described above, 131, 132, 133, and 134 supply clocks to the stages 101, 102, 103, and 106, respectively.

Next, regarding the operation of the first invention of the data processing apparatus of the present invention when executing the instruction sequence shown in FIG. 14 similar to the above-mentioned conventional example, each stage in each pipeline processing stage 2 showing the states of the instructions processed in
Will be described with reference to the schematic diagram of FIG.

First, the instruction 401 is fetched into the IF stage 101 from an external memory (not shown). IF stage
The instruction 401 fetched by 101 is transferred to the D stage 102 as an instruction code 108. This state is shown in Fig. 2 (a).

The D stage 102 decodes the instruction 401, and the decoded result is the D code 109 and the A code 110.
Is transferred to the A stage 103 as. Also, the next instruction 40
2 is fetched from external memory to IF stage 101 and D
Transferred to stage 102. This state is shown in Fig. 2 (b).

By the way, the instruction 401 is a long-time processing instruction (smo
vb), the instruction decoding unit 135 of the D stage 102
Outputs the detection signal 136 to the clock supply selection circuits 131 and 132 of the IF stage 101 and D stage 102 and the A stage 103. As a result, the supply of the clock from the clock supply wiring 1 to the IF stage 101 and the D stage 102 is stopped, and the operations of the IF stage 101 and the D stage 102 are stopped. Therefore, after this point, the IF stage 101
The instruction 402 following the 401 is never fetched from external memory.

At the A stage 103, when the processing of the instruction 401 is completed, the processing results are R code 111 and F code 11
2 is transferred to the F stage 106. This state is shown in FIG. 2 (c). Further, since the detection signal 136 from the instruction decoding unit 135 of the D stage 102 is also given to the A stage 103, the A stage 103 outputs the detection signal 136 to its own clock supply selection circuit 133 and after completion of the processing in the A stage 103. Output to F stage 106. This allows
The supply of the clock from the clock supply wiring 1 to the A stage 103 is stopped, and the A stage 103 also stops its operation.

In the F stage 106, when the processing of the instruction 401 is completed, the processing result is transferred to the E stage 107 as the E code 113 and the S code 114. This state is shown in Fig. 2 (d).
Is shown in. In addition, the detection signal 13 from the A stage 103
Since 6 is also given to the F stage 106, the F stage 106 outputs the detection signal 136 after the processing in the F stage 106 is completed.
Its own clock supply selection circuit 134 and E stage 107
Output to. As a result, the clock supply from the clock supply wiring 1 to the F stage 106 is stopped and the F stage 106 is stopped.
106 also stops its operation.

At the E stage 107, when the processing of the instruction 401 is completed, the instruction 401 transfers the write data to the store buffer 120 because the instruction 401 involves memory writing. This state is shown in FIG. 2 (e). Further, since the detection signal 136 from the F stage 106 is also given to the E stage 107, the next instruction fetch address generation unit 13 of the E stage 107
In the case of 7, the address (0
0000064H) is generated.

In the store buffer 120, when the processing of the instruction 401 is completed, a processing completion signal 138 is generated and given to the clock supply selection circuits 131, 132, 133, 134 and the next instruction fetch address generation unit 137. As a result, the supply of the clock from the clock supply wiring 1 to each of the stages 101, 102, 103, 106 is restarted, and the next instruction fetch address generation unit 137 causes the address of the instruction 402 generated earlier (00000064
H) is the IF stage 101 instruction fetch address register 1
Send to 30.

In the IF stage 101, the address (00000064H) of the next instruction 402 from the next instruction fetch address generator 137
Is given to the instruction fetch address register 130, the instruction 402 is fetched from the external memory and the instruction processing is continued.

As described above, in the first aspect of the data processor of the present invention, when the instruction decoding unit 135 of the D stage 102 decodes the instruction, it is detected that the instruction code is a long-time processing instruction code. If possible, the clock supply from the clock supply line 1 to each of the stages 101, 102, 103, 106 preceding the E stage 107 is stopped while the instruction is being processed by the E stage 107. Therefore, while the long-time processing instruction is being processed by the E stage 107, the stages 101, 102, 103, 106 which are conventionally in the standby state do not operate, and wasteful power consumption is avoided.

In the above embodiment, the instruction decoding unit 135 provided in the D stage 102 detects the instruction code of the long-time processing instruction, but the other stages 101, 1
Even if any one of 03, 106, and 107 detects a long-time processing instruction, substantially the same effect is obtained.

Next, the second invention of the data processing apparatus of the present invention will be explained. FIG. 3 is a block diagram showing the configuration of an embodiment of the second invention of the data processing apparatus according to the present invention. In addition, in FIG. 3, the above-mentioned conventional example and the first example
13 and FIG. 1 referred to in the description of the invention indicate the same or corresponding parts.

As shown in FIG. 3, in the second invention, the clock supply selection circuits 131, 132, 133, and 134 provided in the configuration of the first invention shown in FIG. 1 are used. Instead, power supply selection circuits 141, 142, 143, 144 are provided. Then, each power supply selection circuit 141, 142, 143, 144
Is similar to the clock supply selection circuit 131 of the first invention,
When the detection signal 136 is supplied, the power supply from the power supply wiring 2 to each stage 101, 102, 103, 106 is stopped, and when the processing end signal 138 is supplied, the power supply wiring 2 is connected to each stage 101, 102, 103, 106. Power is supplied to 102, 103, and 106.

The other structure is exactly the same as that of the first invention shown in FIG. Further, in FIG. 3, the clock is supplied from the clock supply wiring 1 to each of the stages 101, 102, 103, 106, 107 at all times, but the clock supply wiring 1 and the clock signal line from the clock supply wiring 1 to each stage are omitted. There is.

Specifically, in the second invention of the data processing apparatus of the present invention, the IF stage 10 other than the E stage 107 is provided.
Power supply selection circuits 141, 142, 143, and 144 are provided for the 1, D stage 102, A stage 103, and F stage 106, respectively. These power supply selection circuits 141, 142, 143, 1
As described above, the reference numeral 44 designates each stage 101, 102, 103, 1 from the power supply wiring 2 when the detection signal 136 is given.
When the power supply to 06 is stopped and the processing end signal 138 is given, each stage 101,
Supply power to 102, 103, 106.

Next, regarding the operation of the second invention of the data processing apparatus of the present invention when executing the instruction sequence shown in FIG. 14 similar to the above-mentioned first invention and the conventional example, each pipeline Description will be made with reference to the schematic diagram of FIG. 4 showing the states of instructions processed in each stage in the processing stage.

First, the instruction 401 is fetched from the external memory (not shown) to the IF stage 101. IF stage
The instruction 401 fetched by 101 is transferred to the D stage 102 as an instruction code 108. This state is shown in FIG. 4 (a).

The D stage 102 decodes the instruction 401, and the decoded result is the D code 109 and the A code 110.
Is transferred to the A stage 103 as. Also, the next instruction 40
2 is fetched from external memory to IF stage 101 and D
Transferred to stage 102. This state is shown in Fig. 4 (b).

By the way, the instruction 401 is a long-time processing instruction (smo
vb), the instruction decoding unit 135 of the D stage 102
Outputs the detection signal 136 to the power supply selection circuits 141 and 142 of the IF stage 101 and D stage 102 and the A stage 103. As a result, the power supply from the power supply wiring 2 to the IF stage 101 and the D stage 102 is stopped, and the IF stage 101
And the D stage 102 stops its operation. Therefore, from this point onward, the IF stage 101 outputs the instruction 402 next to the instruction 401.
Is not fetched from external memory.

At the A stage 103, when the processing of the instruction 401 is completed, the processing result is transferred to the F stage 106 as the R code 111 and the F code 112. This state is shown in Fig. 4 (c).
Is shown in. Further, since the detection signal 136 from the instruction decoding unit 135 of the D stage 102 is also given to the A stage 103, the A stage 103 outputs the detection signal 136 to its own power supply selection circuit 143 and after the processing in the A stage 103 is completed. Output to F stage 106. As a result, the power supply from the power supply wiring 2 to the A stage 103 is stopped, and the A stage 103 also stops its operation.

In the F stage 106, when the processing of the instruction 401 is completed, the processing result is transferred to the E stage 107 as the E code 113 and the S code 114. This state is shown in Fig. 4 (d).
Is shown in. In addition, the detection signal 13 from the A stage 103
Since 6 is also given to the F stage 106, the F stage 106 outputs the detection signal 136 after the processing in the F stage 106 is completed.
Is output to its own power supply selection circuit 144 and the E stage 107. As a result, the power supply wiring 2 to the F stage 10
The power supply to 6 is stopped and the F stage 106 also stops its operation.

At the E stage 107, when the processing of the instruction 401 is completed, the instruction 401 transfers the write data to the store buffer 120 because the instruction 401 involves memory writing. This state is shown in FIG. 4 (e). Further, since the detection signal 136 from the F stage 106 is also given to the E stage 107, the next instruction fetch address generation unit 13 of the E stage 107
In the case of 7, the address (0
0000064H) is generated.

In the store buffer 120, when the processing of the instruction 401 is completed, a processing completion signal 138 is generated and given to the respective power supply selection circuits 141, 142, 143, 144 and the next instruction fetch address generator 137. As a result, the power supply from the power supply wiring 2 to each stage 101, 102, 103, 106 is restarted, and the next instruction fetch address generation unit 137 sends the address (00000064H) of the instruction 402 generated earlier to the IF stage 101.
Sent to the instruction fetch address register 130 of

In the IF stage 101, the address (00000064H) of the next instruction 402 from the next instruction fetch address generator 137
Is given to the instruction fetch address register 130, the instruction 402 is fetched from the external memory and the instruction processing is continued.

As described above, according to the first aspect of the data processing device of the present invention, when the instruction decoding unit 135 of the D stage 102 decodes the instruction, it is detected that the instruction code is a long processing instruction code. If possible, the power supply wiring 2 to each of the stages 101, 102, 103 and 106 preceding the E stage 107 while the instruction is being processed.
The power supply from is stopped. Therefore, the long processing instruction is
While processing is performed in the stage 107, the stages 101, 102, 103, and 106, which are conventionally in a standby state, do not operate, so that useless power consumption is avoided.

Although the instruction decoding unit 135 provided in the D stage 102 detects the instruction code of the long-time processing instruction in the above embodiment, the other stages 101, 1
Even if any one of 03, 106, and 107 detects a long-time processing instruction, substantially the same effect is obtained.

Next, the third invention of the data processing apparatus of the present invention will be explained. FIG. 5 is a block diagram showing the configuration of an embodiment of the third invention of the data processing apparatus according to the present invention. In FIG. 5, the same reference numerals as those in FIG. 13 and FIGS. 1 and 3 referred to in the description of the conventional example and the first and second inventions described above indicate the same or corresponding portions.

As shown in FIG. 5, in the third invention, instead of the instruction decoding unit 135 being provided in the D stage 102 in the first invention shown in FIG. 1, a PC break pointer is used. 150, program counter (PC) 115
And an address comparator 151.

The A stage 103, F stage 106, E stage 107 and store buffer 120 are also provided with program counters 116, 117, 118 and 119, respectively.

In the following description, the D stage 102
The value of the program counter 115 of "DPC", A stage
The value of the program counter 116 of 103 is "APC", the value of the program counter 117 of F stage 106 is "FPC", E
The value of the program counter of the stage 107 is "CPC", and the value of the program counter 119 of the store buffer 120 is "SP".
C ”.

The other structure is exactly the same as that of the first invention shown in FIG. Further, in FIG. 5, the power is supplied from the power supply line 2 to each of the stages 101, 102, 103, 106, 107 at all times, but the power supply line 2 and the power supply line to each stage are omitted.

Next, a diagram similar to the above-mentioned conventional example and each invention.
Regarding the third operation of the data processing apparatus of the present invention when executing the instruction sequence shown in 14, refer to the schematic diagram of FIG. 6 showing the state of the instruction processed in each stage in each pipeline processing stage. And explain.

PC break pointer 150 of D stage 102
Is the address of a long-term processing instruction that is a specific instruction in the instruction sequence processed by this data processing device, that is, in the case of processing the instruction sequence shown in FIG. The address “00000062H” of the instruction 401 is stored in advance.

First, the instruction 401 is fetched from the external memory (not shown) to the IF stage 101. And IF
Instruction 401 fetched in stage 101 is instruction code 10
8 is transferred to the D stage 102. At this time, the address "00000062H" of the instruction 401 is set in the program counter 115 of the D stage 102 as "DPC". In this way, when the address of the new instruction is set in the program counter 115 as "DPC", the address comparator 15
1 compares "DPC" with the value stored in PC break pointer 150. This state is shown in FIG. 6 (a).

In the D stage 102, the instruction 401 is decoded, and the decoded result is the D code 109 and the A code 110.
Is transferred to the A stage 103 as. Also, the next instruction 40
2 is fetched from external memory to IF stage 101 and D
Transferred to stage 102. This state is shown in FIG. 6 (b).

At this time, the address "00000062H" of the instruction 401 is stored in the program counter 116 of the A stage 103 as "AP".
It is set as C ". Further, as described above, the address comparator 151 is connected to the program counter 115 of the D stage 102.
The "DPC" set in the register is compared with the value stored in the PC break pointer 150. In this case, since the comparison results match, the address comparator 151 outputs the detection signal 136 to the IF signal.
It outputs to the clock supply selection circuits 131 and 132 of the stage 101 and the D stage 102 and the A stage 103. As a result, the clock supply from the clock supply wiring 1 to the IF stage 101 and the D stage 102 is stopped, and the IF stage 10
1 and the operation of the D stage 102 stops. Therefore, the IF stage 101 does not fetch the next instruction 403 from the external memory.

At the A stage 103, when the processing of the instruction 401 is completed, the processing result is transferred to the F stage 106 as the R code 111 and the F code 112. At this time, F stage
The address "00000062H" of the instruction 401 is set in the program counter 117 of 106 as "FPC". Further, the detection signal 136 from the address comparator 151 is sent to the A stage.
Since it is also given to 103, the A stage 103 outputs the detection signal 136 to its own clock supply selection circuit 133 and the F stage 106 after the processing in the A stage 103 is completed. As a result, the supply of the clock from the clock supply wiring 1 to the A stage 103 is stopped and the operation of the A stage 103 is stopped. This state is shown in FIG. 6 (c).

At the F stage 106, when the processing of the instruction 401 is completed, the processing result is transferred to the E stage 107 as the E code 113 and the S code 114. At that time, E stage
The address "00000062H" of the instruction 401 is set in the program counter 118 of 107 as "CPC". Further, the detection signal 136 from the A stage 103 is sent to the F stage 106.
It is also given to the F stage 106
After the processing in 106 is completed, the detection signal 136 is output to the clock supply selection circuit 134 and the E stage 107 of its own. As a result, the supply of the clock from the clock supply wiring 1 to the F stage 106 is stopped, and the operation of the F stage 106 is stopped. This state is shown in FIG. 6 (d).

At the E stage 107, when the processing of the instruction 401 is completed, the instruction 401 involves memory writing, so the write data is transferred to the store buffer 120. that time,
Instructions are stored in the program counter 119 of the store buffer 120.
The address “00000062H” of 401 is set as “SPC”. Further, since the detection signal 136 is also given to the E stage 107 from the F stage 106, the next instruction fetch address generation unit 137 of the E stage 107 generates the address (00000064H) of the instruction 402 which is the next instruction of the instruction 401. To do. This state is shown in FIG. 6 (e).

In the store buffer 120, when the processing of the instruction 401 is completed, a processing completion signal 138 is generated and given to each clock supply selection circuit 131, 132, 133, 134 and the next instruction fetch address generation unit 137. As a result, the supply of the clock from the clock supply wiring 1 to each of the stages 101, 102, 103, and 106 is restarted, and the next instruction fetch address generation unit 137 causes the address of the instruction 402, which is the next instruction generated earlier ( (00000064H) to the instruction fetch address register 130
Send to.

In the IF stage 101, the address (00000064H) of the next instruction 402 from the next instruction fetch address generator 137
Is given to the instruction fetch address register 130, the instruction 402 is fetched from the external memory and the instruction processing is continued.

As described above, when it is known in advance which address of the instruction sequence to be processed is the long-time processing instruction, the address comparator 151 detects it, so that While the instruction is being processed by the E stage 107, each stage 101, 102, 103, 106 preceding it is processed.
By stopping the supply of the clock from the clock supply wiring 1 to the stages 101, 102, 103, 106, each stage 101, 102, 103, 106 does not operate, and unnecessary power consumption is avoided.

In the above embodiment, the address comparator 151 provided in the D stage 102 detects the address of the long-time processing instruction.
Almost the same effect can be obtained regardless of whether the address of a long-time processing instruction is detected by any of 3, 106, and 107.

Next explained is the fourth invention of the data processing apparatus of the invention. FIG. 7 is a block diagram showing the configuration of an embodiment of the fourth invention of the data processing apparatus according to the present invention. In addition, in FIG. 7, FIG. 13 and FIG. 1 referred to in the description of the above-mentioned conventional example and the first, second, and third inventions.
The same reference numerals as those in FIGS. 3 and 5 indicate the same or corresponding portions.

As shown in FIG. 7, in the fourth invention, the clock supply selection circuits 131, 132, 133, 134 provided in the configuration of the third invention shown in FIG. Instead, power supply selection circuits 141, 142, 143, 144 are provided. Then, each power supply selection circuit 141, 142, 143, 144
Is similar to the clock supply selection circuit 131 of the third invention,
When the detection signal 136 is supplied, the power supply from the power supply wiring 2 to each stage 101, 102, 103, 106 is stopped, and when the processing end signal 138 is supplied, the power supply wiring 2 is connected to each stage 101, 102, 103, 106. Power is supplied to 102, 103, and 106.

The other structure is exactly the same as that of the third invention shown in FIG. Further, in FIG. 7, the clock is supplied from the clock supply wiring 1 to each of the stages 101, 102, 103, 106, 107 at all times, but the clock supply wiring 1 and the clock signal line from each stage to the respective stages are omitted. There is.

Specifically, in the fourth invention of the data processing apparatus of the present invention, the IF stage 10 other than the E stage 107 is provided.
Power supply selection circuits 141, 142, 143, and 144 are provided for the 1, D stage 102, A stage 103, and F stage 106, respectively. These power supply selection circuits 141, 142, 143, 1
As described above, the reference numeral 44 designates each stage 101, 102, 103, 1 from the power supply wiring 2 when the detection signal 136 is given.
When the power supply to 06 is stopped and the processing end signal 138 is given, each stage 101,
Supply power to 102, 103, 106.

Next, the same drawing as the above-mentioned conventional example and each invention.
Regarding the fourth operation of the data processor of the present invention when executing the instruction sequence shown in FIG. 14, refer to the schematic diagram of FIG. 8 showing the states of the instructions processed in each stage in each pipeline processing stage. Explain.

PC break pointer 150 of D stage 102
Is the address of a long-term processing instruction that is a specific instruction in the instruction sequence processed by this data processing device, that is, in the case of processing the instruction sequence shown in FIG. The address “00000062H” of the instruction 401 is stored in advance.

First, the instruction 401 is fetched from the external memory (not shown) to the IF stage 101. And IF
Instruction 401 fetched in stage 101 is instruction code 10
8 is transferred to the D stage 102. At this time, the address "00000062H" of the instruction 401 is set in the program counter 115 of the D stage 102 as "DPC". In this way, when the address of the new instruction is set in the program counter 115 as "DPC", the address comparator 15
1 compares "DPC" with the value stored in PC break pointer 150. This state is shown in FIG. 8 (a).

In the D stage 102, the instruction 401 is decoded, and the decoded result is the D code 109 and the A code 110.
Is transferred to the A stage 103 as. Also, the next instruction 40
2 is fetched from external memory to IF stage 101 and D
Transferred to stage 102. This state is shown in FIG. 8 (b).

At this time, the address "00000062H" of the instruction 401 is stored in the program counter 116 of the A stage 103 as "AP".
It is set as C ". Further, as described above, the address comparator 151 is connected to the program counter 115 of the D stage 102.
The "DPC" set in the and the value stored in the PC break pointer 150 are compared. In this case, since the comparison results match, the address comparator 151 outputs the detection signal 136 to the IF stage.
Output to the power supply selection circuits 141 and 142 of the 101 and D stage 102 and the A stage 103. As a result, the power supply from the power supply wiring 2 to the IF stage 101 and the D stage 102 is stopped, and the operations of the IF stage 101 and the D stage 102 are stopped. Therefore, the IF stage 101 does not fetch the next instruction 403 from the external memory.

At the A stage 103, when the processing of the instruction 401 is completed, the processing result is transferred to the F stage 106 as the R code 111 and the F code 112. At this time, F stage
The address "00000062H" of the instruction 401 is set in the program counter 117 of 106 as "FPC". Further, the detection signal 136 from the address comparator 151 is sent to the A stage.
Since it is also given to 103, the A stage 103 outputs the detection signal 136 to its own power supply selection circuit 143 and the F stage 106 after the processing in the A stage 103 is completed. As a result, the power supply from the power supply wiring 2 to the A stage 103 is stopped and the operation of the A stage 103 is stopped. This state is shown in FIG. 8 (c).

At the F stage 106, when the processing of the instruction 401 is completed, the processing result is transferred to the E stage 107 as E code 113 and S code 114. At that time, E stage
The address "00000062H" of the instruction 401 is set in the program counter 118 of 107 as "CPC". Further, the detection signal 136 from the A stage 103 is sent to the F stage 106.
It is also given to the F stage 106
After the processing in 106 is completed, the detection signal 136 is output to the power supply selection circuit 144 of its own and the E stage 107. As a result, the power supply from the power supply wiring 2 to the F stage 106 is stopped and the operation of the F stage 106 is stopped. This state is shown in FIG. 8 (d).

At the E stage 107, when the processing of the instruction 401 is completed, since the instruction 401 involves memory writing, the write data is transferred to the store buffer 120. that time,
Instructions are stored in the program counter 119 of the store buffer 120.
The address “00000062H” of 401 is set as “SPC”. Further, since the detection signal 136 is also given to the E stage 107 from the F stage 106, the next instruction fetch address generation unit 137 of the E stage 107 generates the address (00000064H) of the instruction 402 which is the next instruction of the instruction 401. To do. This state is shown in FIG. 8 (e).

In the store buffer 120, when the processing of the instruction 401 is completed, a processing completion signal 138 is generated and given to the respective power supply selection circuits 141, 142, 143, 144 and the next instruction fetch address generator 137. As a result, the power supply from the power supply wiring 2 to each of the stages 101, 102, 103, 106 is restarted, and the next instruction fetch address generation unit 137 issues the instruction 402 address (00000064H) which is the previously generated next instruction. Send to fetch address register 130.

In the IF stage 101, the address (00000064H) of the next instruction 402 from the next instruction fetch address generator 137
Is given to the instruction fetch address register 130, the instruction 402 is fetched from the external memory and the instruction processing is continued.

As described above, when it is known in advance which address of the instruction sequence to be processed is the long-time processing instruction, the address comparator 151 detects it, so that While the instruction is being processed by the E stage 107, each stage 101, 102, 103, 106 preceding it is processed.
By stopping the power supply from the power supply wiring 2 to
Each stage 101, 102, 103, 106 does not work,
Useless power consumption is avoided.

In the above embodiment, the address comparator 151 provided in the D stage 102 detects the address of the long-time processing instruction. However, the other stages 101, 10
Almost the same effect can be obtained regardless of whether the address of a long-time processing instruction is detected by any of 3, 106, and 107.

Next, the fifth invention of the data processing apparatus of the present invention will be explained. FIG. 9 is a block diagram showing the configuration of the fifth embodiment of the data processing apparatus according to the present invention. In FIG. 9, the same reference numerals as those in FIG. 13 and FIG. 1, FIG. 3, FIG. 5, and FIG. 7 referred to in the above-mentioned conventional example and the description of the first, second, third, and fourth inventions. The same or corresponding parts are shown.

As shown in FIG. 9, in the fifth invention, in addition to the configuration of the first invention shown in FIG.
A buffer 160, 1 as a static storage means for statically storing data in order to transfer the data in each stage 101, 102, 103, 106 except the E stage 107.
It has 61, 162 and 163. Note that each of these buffers
Clock supply selection circuits 131, 1 for 160, 161, 162, 163
32, 133, 134 from each stage 101, 102, 103, 1
The clock supplied to 06 is supplied.

Further, in the first invention, the E stage 107
The next-instruction-fetch-address generating unit 137 provided in the above is not provided.

The other structure is exactly the same as that of the first invention shown in FIG. Further, in FIG. 9, the power is supplied from the power supply wiring 2 to each of the stages 101, 102, 103, 106 and 107 at all times, but the power supply wiring 2 and the power supply line to each stage are omitted.

The instruction fetch address register 130 of the IF stage 101 is connected to the buffer 160, and the instruction address held in the buffer 160 is input. Further, the detection signal 13 output when the long-time processing instruction is detected by the instruction decoding unit 135
6 is given only to the A stage 103, and then transmitted from the A stage 103 to the F stage 106, from the F stage 106 to the E stage 107, and further from the E stage 107 to each clock supply selection circuit 131, 132, 133, 134. . Further, the processing end signal 138 output from the store buffer 120 is the clock supply selection circuits 131, 132, 13
3 and 134, but not the instruction fetch address register 130.

Next, a diagram similar to the above-mentioned conventional example and each invention.
Regarding the operation of the fifth invention of the data processing device of the present invention when executing the instruction sequence shown in FIG. 14, a schematic diagram of FIG. 10 showing states of instructions processed in each stage in each pipeline processing stage. Will be described with reference to.

First, the instruction 401 is fetched into the IF stage 101 from an external memory (not shown). IF stage
The instruction 401 fetched by 101 is output as the instruction code 108 from the buffer 160 and transferred to the D stage 102. Then, the next instruction 402 is from the external memory to the IF stage.
The instruction code and the instruction address of the instruction 402 are temporarily stored in the buffer 160. This state is shown in Fig. 10 (a).

At the D stage 102, the instruction 401 is decoded, and the decoding result is obtained from the buffer 161 to the D code 109.
And is output as the A code 110 and transferred to the A stage 103. Also, the instruction decoding unit 135 of the D stage 102.
Since it is detected that it is a long-time processing instruction (smov.b), the instruction decoding unit 135 outputs the detection signal 136 to the A stage 10
Output to 3. Further, the instruction 403 is fetched from the external memory to the IF stage 101, and the instruction 403 is fetched into the buffer 160.
The instruction code and instruction address of are stored. This state is shown in Fig. 10 (b).

In the A stage 103, when the processing of the instruction 401 is completed, the processing result is output from the buffer 162 as the R code 111 and the F code 112 and transferred to the F stage 106. Further, the detection signal input from the D stage 102
136 is also output to the F stage 106.

Thereafter, the instruction 402 is transferred from the buffer 161 of the D stage 102 to the A stage 103. Also the instruction
403 is buffer 160 of IF stage 101 to D stage 10
Transferred to 2. Further, the instruction 404 is fetched from the external memory to the IF stage 101, and the instruction 40 is fetched into the buffer 160.
The instruction code and instruction address of 4 are stored. This state is shown in Fig. 10 (c).

In the F stage 106, when the processing of the instruction 401 is completed, the processing result is transferred from the buffer 163 to the E stage 107 as the E code 113 and the S code 114. The detection signal 136 input from the A stage 103 is also output to the E stage 107. After that, the instruction 402 is transferred from the buffer 162 of the A stage 103 to the F stage 106. Further, the instruction 403 is transferred from the buffer 161 of the D stage 102 to the A stage 103. Instruction 404 is the IF stage
It is transferred from the buffer 160 of 101 to the D stage 102.
Further, the instruction 405 is fetched from the external memory to the IF stage 101, and the instruction code and instruction address of the instruction 405 are stored in the buffer 160. This state is shown in Fig. 10 (d).

At the E stage 107, when the processing of the instruction 401 is completed, since the instruction 401 involves memory writing, the write data is transferred to the store buffer 120. afterwards,
The instruction 402 is transferred from the buffer 163 of the F stage 106 to the E stage 107. The instruction 402 is transferred from the buffer 162 of the A stage 103 to the F stage 106. Also the instruction
404 is buffer 161 of D stage 102 to A stage 10
Transferred to 3. Instruction 405 is the buffer of IF stage 101
Transfer from 160 to D stage 102. Further, the instruction 406 is fetched from the external memory to the IF stage 101, and the instruction code and instruction address of the instruction 406 are stored in the buffer 160. This state is shown in Fig. 10 (e).

Further, from the F stage 106 to the E stage 107
When the detection signal 136 is input to the E stage 107, the E stage 107 outputs the clock supply selection circuits 131, 101, 102, 103, 106 of each stage.
Outputs detection signal 136 to 132, 133, 134 and outputs each stage 10
Stop the clock supply from the clock supply wiring 1 to 1, 102, 103, 106. As a result, each stage 101,10
2, 103, 106 stop its operation, but buffer 160, 161, 162, 163 of each stage 101, 102, 103, 106
Does not lose the stored contents at that time, specifically, the processing results of the stages 101, 102, 103, 106 at that time, because the static storage is performed even if the clock is not supplied.

In the store buffer 120, when the processing of the instruction 401 is completed, a processing end signal 138 is generated and given to each clock supply selection circuit 131, 132, 133, 134. As a result, each stage 101, 102, 103, from the clock supply wiring 1
The clock supply to 106 is restarted. When the supply of this clock is restarted, each stage 101, 102, 103, 1
Buffers 160, 161, which store the data of the processing result of 06,
The contents of 162, 163 are the next stages 102, 103, 106, 107
Will be sent to each stage 102, 103, 106, 1
In 07, the subsequent processing is restarted according to those data.

In the IF stage 101, since the address next to the instruction address stored in the buffer 160, that is, the instruction address of the instruction 406 in the above example, is stored in the buffer 160, the instruction 407 next to the instruction 406 is stored. Address (00000
06EH) is given to the instruction fetch address register 130, the instruction 406 is fetched from the external memory and the instruction processing is continued.

As described above, when it is possible to detect that the instruction code of the instruction decoded by the instruction fetch address register 130 of the IF stage 101 is the code of the long-time processing instruction, the instruction is processed by the E stage 107. While processing, each stage 101, 102, 103, 106 of the previous stage outputs each processing result to each buffer 160, 161, 162,
The supply of the clock from the clock supply wiring 1 is stopped in the state of being stored in 163. Therefore, each stage 101, 102,
Since 103 and 106 do not operate, unnecessary power consumption is avoided, unnecessary instruction fetch from the external memory is not performed when processing is restarted, and each stage 101, 102, The result processed in 103, 106 can be reused as it is and the processing can be restarted quickly.

In the above embodiment, the instruction decoding unit 135 provided in the D stage 102 detects a long-time processing instruction, but the other stages 101, 103, 106, 107.
In any of the above cases, the same effect can be obtained regardless of whether the long-time processing instruction is detected. Further, in the above embodiment, the long-time processing instruction is detected by the instruction code obtained by decoding the instruction. However, if the address of the long-time processing instruction is known in advance, it is shown in FIGS. Has been third
As in the case of the fourth invention, the configuration may be such that address coincidence detection is performed.

Next, the sixth invention of the data processing apparatus of the present invention will be explained. FIG. 11 is a block diagram showing the configuration of a sixth embodiment of the data processing apparatus according to the present invention. In addition, in FIG. 11, the above-mentioned conventional example and the first example
To FIG. 13, FIG. 1, FIG. 3 referred to in the description of the fifth invention
The same reference numerals as those in FIGS. 5, 7, and 9 denote the same or corresponding portions.

As shown in FIG. 11, in the sixth invention, power supply selection circuits 141, 142, 143, 144 are provided, but clock supply selection circuits 131, 132, 133, 134 are not provided. Further, in FIG. 11, the clock is supplied from the clock supply wiring 1 to each of the stages 101, 102, 103, 106, 107 at all times, but the clock supply wiring 1 and the clock signal line from each stage to each stage are omitted. There is.

In addition, in the sixth invention, the buffer 160, which is provided in the configuration of the fifth invention shown in FIG. 9, is provided.
161, 162, 163 are all stages 101, 102, 103, 1
It is independent of 06, and the power supply from the power supply wiring 2 to each stage 101, 102, 103, 106 is the power supply selection circuit 14
Each buffer even when blocked by 1, 142, 143, 144
Power is supplied to 160, 161, 162, 163.

In the sixth invention, the program counters 115, 116, 117, 118 and 119 similar to those of the third and fourth inventions shown in FIGS.
Stage 102, A stage 103, F stage 106, E stage
107, provided in the store buffer 120.

Further, in the third and fourth inventions shown in FIGS. 5 and 7, the D stage 102 is provided with the PC break pointer 150 and the address comparator 151. However, in the sixth invention, Store them in the store buffer 120. The detection signal 136 output from the address comparator 151 provided in the store buffer 120 is given to each power supply selection circuit 141, 142, 143, 144.
Other configurations are similar to those of the fifth invention shown in FIG.

Next, a diagram similar to the above-mentioned conventional example and each invention.
The schematic diagram of FIG. 12 showing the state of the instruction processed in each stage in each pipeline processing stage in the operation of the sixth invention of the data processing device of the present invention when executing the instruction sequence shown in FIG. Will be described with reference to.

First, the instruction 401 is fetched from the external memory (not shown) to the IF stage 101. IF stage
The instruction 401 fetched by 101 is transferred to the D stage 102 as an instruction code 108 via the buffer 160.
At this time, the address "00000062H" of the instruction 401 is set in the program counter 115 of the D stage 102 as "DPC". Then the next instruction 402 from the external memory
The instruction is fetched into stage 101 and placed in buffer 160
The instruction code and instruction address of 402 are temporarily stored.
This state is shown in Figure 12 (a).

In the D stage 102, the instruction 401 is decoded, and the decoding result is transferred to the A stage 103 as the D code 109 and the A code 110 via the buffer 161. At that time, the program counter 11 of the A stage 103
The address “00000062H” of the instruction 401 is set to 6 as “APC”. The next instruction 402 is transferred from the IF stage 101 to the D stage 102 via the buffer 160, and D
The address "00000064H" of the instruction 402 is set in the program counter 115 of the stage 102 as "DPC". Further, the instruction 403 is fetched from the external memory to the IF stage 101, and the instruction code and instruction address of the instruction 403 are stored in the buffer 160. This state is shown in Figure 12 (b).
Is shown in.

At the A stage 103, when the processing of the instruction 401 is completed, the processing result is transferred to the F stage 106 as the R code 111 and the F code 112 via the buffer 162. At that time, the program counter of the F stage 106
In 117, the address “00000062H” of instruction 401 is “FPC”
Is set as. Also, the next instruction 402 is the A stage
The data is transferred from 103 to the A stage 103 via the buffer 161, and the address "00000064H" of the instruction 402 is set in the program counter 116 as "APC". Further, the instruction 403 is transferred from the IF stage 101 to the D stage 102 via the buffer 160, and the program counter 115 of the D stage 102 has the address “00000066” of the instruction 402.
H "is set as" DPC ". Further, the instruction 404 is fetched from the external memory to the IF stage 101, and the instruction code and instruction address of the instruction 404 are stored in the buffer 160. This state is shown in FIG. ).

In the F stage 106, when the processing of the instruction 401 is completed, the processing result is transferred to the E stage 107 as the E code 113 and the S code 114 via the buffer 163. At that time, the program counter of the E stage 107
In 118, the address “00000062H” of instruction 401 is “CPC”
Is set as. Also, the next instruction 402 is the A stage
The data is transferred from 103 to the F stage 106 via the buffer 162, and the address "00000064H" of the instruction 402 is set in the program counter 117 as "FPC". Further, the instruction 403 is transferred from the D stage 102 to the A stage 103 via the buffer 161, and the program counter 11
The address “00000066H” of the instruction 403 is set to 6 as “APC”. Further, the instruction 404 is transferred from the IF stage 101 to the D stage 102 via the buffer 160,
The instruction 404 is sent to the program counter 115 of the D stage 102.
The address "00000068H" is set as "DPC". Further, the instruction 405 is fetched from the external memory to the IF stage 101, and the instruction code and instruction address of the instruction 404 are stored in the buffer 160. This state is shown in Fig. 12 (d).
Is shown in.

At the E stage 107, when the processing of the instruction 401 is completed, since the instruction 401 involves memory writing, the write data is transferred to the store buffer 120. that time,
Instructions are stored in the program counter 119 of the store buffer 120.
The address “00000062H” of 401 is set as “SPC”. Further, the next instruction 402 is transferred from the F stage 106 to the E stage 107 via the buffer 163, and the address "00000064H" of the instruction 402 is set in the program counter 118 of the E stage 107 as "CPC". Further, the instruction 403 is transferred from the A stage 103 via the buffer 162 to the F stage 106, and the program counter 11
The address “00000066H” of the instruction 403 is set to 7 as “FPC”. Further, the instruction 404 is transferred from the D stage 102 to the A stage 103 via the buffer 161.
The address 0000 of instruction 404 is stored in the program counter 116.
0068H ”is set as“ APC ”.
5 is transferred from the IF stage 101 to the D stage 102 via the buffer 160, and the address “00000068A” of the instruction 405 is stored in the DP counter of the program counter 115 of the D stage 102.
Set as C ". In addition, the instruction 40
6 is fetched into the IF stage 101, and the instruction code and instruction address of the instruction 404 are stored in the buffer 160. This state is shown in Fig. 12 (e).

In the store buffer 120, the address of the long-time processing instruction previously stored in the PC break pointer 150 is compared with the value stored as "SPC" in the program counter 119. In this case, the detection signal is detected. 136
To the power supply selection circuits 141, 142, 143, 144 of the preceding stages 101, 102, 103, 106. As a result, the power supply from the power supply wiring 2 to each stage 101, 102, 103, 106 is stopped. As a result, each stage 101, 10
2, 103, 106 stop working, but buffers 160, 16
Since the power supply to 1, 162, 163 is not stopped, the stored contents at that time, specifically each stage 101, 102, 10 at that time
You won't lose the result of 3,106.

When the processing of the instruction 401 is completed, the store buffer 120 generates a processing completion signal 138 and supplies it to each power supply selection circuit 141, 142, 143, 144. As a result, the supply of power from the power supply wiring 2 to each stage 101, 102, 103, 106 is restarted. When the power supply is restarted, the contents of the buffers 160, 161, 162, 163 storing the processing result data of each stage 101, 102, 103, 106 are stored in the next stage 102, 103, 106, 107. Then, each stage 102, 103, 106, 107 restarts subsequent processing according to the data.

The IF stage 101 stores the address next to the instruction address stored in the buffer 160, that is, the address of the instruction 407 next to the instruction 406 since the instruction address of the instruction 406 is stored in the buffer 160 in the above example. (0000006E
H) is given to the instruction fetch address register 130, the instruction 406 is fetched from the external memory and the instruction processing is continued.

As described above, when it is possible to detect that the instruction decoded by the instruction fetch address register 130 of the IF stage 101 is a long-time processing instruction, the instruction is being processed by the E stage 107 while the instruction before it is being processed. Each stage 10
In 1, 102, 103, 106, the power supply from the power supply wiring 2 is stopped in a state in which the respective processing results are stored in the buffers 160, 161, 162, 163, respectively. Therefore, each stage 10
Since 1, 102, 103, 106 do not operate, unnecessary power consumption is avoided, unnecessary instruction fetch from external memory is not performed when processing is restarted, and each stage 101 , 102, 103, 106 can be reused as they are and the processing can be restarted.

In the above embodiment, the address comparator 151 provided in the E stage 107 detects the long-time processing instruction, but the other stages 101, 102, 103, 106.
In any of the above cases, the same effect can be obtained regardless of whether the long-time processing instruction is detected. Further, in the above embodiment, since the address of the long-time processing instruction is known in advance, the address of the long-time processing instruction is detected by the address comparator 151, but the long-time processing instruction is issued from the result of decoding the instruction. It may be configured.

[0134]

As described above in detail, according to the first aspect of the data processing apparatus of the present invention, each pipeline processing stage is placed in a standby state during processing at a specific pipeline processing stage. When the specific instruction is decoded, the supply of the clock to each pipeline processing stage preceding the specific pipeline processing stage is stopped. Therefore, while the specific instruction is being processed in the specific pipeline processing stage, each pipeline processing stage that is conventionally in the standby state does not operate, so that unnecessary power consumption is avoided.

Further, according to the second aspect of the data processing device of the present invention, a specific instruction that causes each of the other pipeline processing stages to be in a standby state is decoded during processing in the specific pipeline processing stage. At that point, power supply to each pipeline processing stage preceding the specific pipeline processing stage is stopped. Therefore, while the specific instruction is being processed in the specific pipeline processing stage, each pipeline processing stage that is conventionally in the standby state does not operate, so that unnecessary power consumption is avoided.

Further, according to the third aspect of the data processor of the present invention, the address of a specific instruction that causes each of the other pipeline processing stages to be in a standby state during processing in a specific pipeline processing stage is set. At the time of detection, supply of a clock to each pipeline processing stage preceding the specific pipeline processing stage is stopped. Therefore, while the specific instruction is being processed in the specific pipeline processing stage, each pipeline processing stage that is conventionally in the standby state does not operate, so that unnecessary power consumption is avoided.

According to the fourth aspect of the data processor of the present invention, the address of a specific instruction that causes each of the other pipeline processing stages to be in a standby state during processing in a specific pipeline processing stage is set. At the time of detection, power supply to each pipeline processing stage preceding the specific pipeline processing stage is stopped. Therefore, while the specific instruction is being processed in the specific pipeline processing stage, each pipeline processing stage that is conventionally in the standby state does not operate, so that unnecessary power consumption is avoided.

Further, according to the fifth aspect of the data processing device of the present invention, a specific instruction that causes each of the other pipeline processing stages to be in a standby state is decoded during processing in the specific pipeline processing stage. At that point, the supply of the clock to each pipeline processing stage and each static storage means is stopped while the processing result in each pipeline processing stage preceding the specific pipeline processing stage is held in the static storage means. To be done. Therefore, while processing a specific instruction in a specific pipeline processing stage, wasteful power consumption is avoided because each pipeline processing stage that is conventionally in the standby state does not operate, and each static processing is performed when processing is restarted. The pipeline processing is immediately restarted according to the contents held in the dynamic storage means.

According to the sixth aspect of the data processor of the present invention, the address of a specific instruction that causes each of the other pipeline processing stages to be in a standby state during processing in a specific pipeline processing stage is set. At the time of detection, power supply to each pipeline processing stage is stopped while the processing result in each pipeline processing stage preceding the specific pipeline processing stage is held in the static storage means. Therefore, while processing a specific instruction in a specific pipeline processing stage, wasteful power consumption is avoided because each pipeline processing stage that is conventionally in the standby state does not operate, and each static processing is performed when processing is restarted. The pipeline processing is immediately restarted according to the contents held in the dynamic storage means.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a first invention of a data processing device according to the present invention.

FIG. 2 is a schematic diagram showing a state of an instruction processed in each pipeline processing stage for explaining the operation of the first embodiment of the data processing apparatus according to the present invention.

FIG. 3 is a block diagram showing the configuration of an embodiment of a second invention of the data processing apparatus according to the present invention.

FIG. 4 is a schematic diagram showing a state of an instruction processed in each pipeline processing stage for explaining the operation of the second embodiment of the data processing apparatus according to the present invention.

FIG. 5 is a block diagram showing a configuration of an embodiment of a third invention of the data processing device according to the present invention.

FIG. 6 is a schematic diagram showing a state of an instruction processed in each stage in each pipeline processing stage for explaining the operation of the third embodiment of the data processor according to the present invention.

FIG. 7 is a block diagram showing the configuration of an embodiment of a fourth invention of the data processing device according to the present invention.

FIG. 8 is a schematic diagram showing a state of an instruction processed in each pipeline processing stage for explaining the operation of the fourth embodiment of the data processing apparatus according to the present invention.

FIG. 9 is a block diagram showing the configuration of an embodiment of a fifth invention of the data processing apparatus according to the present invention.

FIG. 10 is a schematic diagram showing a state of an instruction processed in each stage in each pipeline processing stage for explaining the operation of the fifth embodiment of the data processor according to the present invention.

FIG. 11 is a block diagram showing the configuration of an embodiment of a sixth invention of the data processing apparatus according to the present invention.

FIG. 12 is a schematic diagram showing a state of an instruction processed in each pipeline processing stage for explaining the operation of the sixth embodiment of the data processing apparatus according to the present invention.

FIG. 13 is a block diagram showing a configuration example of a conventional data processing device.

FIG. 14 is a schematic diagram showing an example of an instruction string pipelined by the data processing device of the present invention and the conventional data processing device.

FIG. 15 is a schematic diagram showing a state of an instruction processed in each stage in each pipeline processing stage for explaining the operation of the conventional data processing device.

[Explanation of symbols]

 1 Clock supply wiring 2 Power supply wiring 101 IF stage 102 D stage 103 A stage 106 F stage 107 E stage 115 Program counter 116 Program counter 117 Program counter 118 Program counter 119 Program counter 120 Store buffer 130 Instruction fetch address register 131 Clock supply selection Circuit 132 Clock supply selection circuit 133 Clock supply selection circuit 134 Clock supply selection circuit 135 Instruction decode unit 136 Next instruction fetch address generation unit 141 Power supply selection circuit 142 Power supply selection circuit 143 Power supply selection circuit 144 Power supply selection circuit 150 PC break Pointer 151 Address comparator 160 Buffer 161 Buffer 162 Buffer 163 Buffer

Claims (6)

[Claims] 1. A data processing device for pipeline processing an instruction fetched from the outside by a plurality of processing stages, each of which operates in synchronization with a clock supplied from a clock supply wiring, wherein: A specific instruction detecting means for detecting that a specific instruction in which another processing stage is in a standby state during processing in a specific processing stage is being processed, and a next instruction for calculating the address of the instruction next to the instruction being processed. Address calculation means, clock supply selection means for selecting whether to supply or stop a clock from the clock supply wiring to each processing stage, and an instruction for storing the address of an instruction to be fetched next from the outside. Fetching address storage means, the clock supply selecting means, When the processing is detected, the supply of the clock to the processing stage in the standby state is stopped, and when the processing in the specific processing stage is completed, the clock is supplied to each of the processing stages. The next-instruction-address calculating means is configured to give the address of the next instruction to the instruction-fetch-address storing means to fetch the next instruction when the processing in the specific processing stage is completed. And data processing device. 2. A data processing device for pipeline-processing an instruction fetched from the outside in a plurality of processing stages, each of which operates by being supplied with power from a power supply wiring, in a specific processing stage among the plurality of processing stages. A specific instruction detecting means for detecting that a specific instruction in which the other processing stage is in a waiting state during the processing of 1), and a next instruction address calculating means for calculating the address of the instruction next to the instruction being processed, Power supply selection means for selecting whether to supply power to the processing stages from the power supply wiring or to stop the processing stage, and instruction fetch address storage means for storing the address of an instruction to be fetched next from the outside The power supply selecting means is put in a standby state when the specific instruction detecting means detects that a specific instruction is processed. Stopping the power supply to the processing stage that is in progress, and when the processing in the specific processing stage is completed, power is supplied to each processing stage, the next instruction address calculation means, A data processing device, characterized in that, when the processing is completed, the address of the next instruction is given to the instruction fetch address storage means to fetch the next instruction. 3. A data processing device for pipeline-processing an instruction fetched from the outside by a plurality of processing stages each operating in synchronization with a clock supplied from a clock supply wiring, wherein: A specific instruction address storage means for storing in advance the address of a specific instruction in which another processing stage is in a standby state during processing in a specific processing stage; and an address of the instruction being processed and the specific instruction address storage means. Means for comparing the address of the next instruction of the instruction being processed, a next instruction address calculating means for calculating the address of the instruction next to the instruction being processed, and a clock is supplied from the clock supply wiring to each processing stage or stopped. A clock supply selection means for selecting whether to execute, and the address of the instruction to be fetched next from the outside are stored. An instruction fetch address storage means, wherein the clock supply selection means supplies a clock to a processing stage in a standby state when the specific instruction detection means detects that a specific instruction is processed. Stop, supplying a clock to each processing stage when the processing in the specific processing stage is completed, the next instruction address calculation means, when the processing in the specific processing stage is completed, A data processing device characterized in that the address of the next instruction is given to the instruction fetch address storage means to fetch the next instruction. 4. A data processing device for pipeline processing an instruction fetched from the outside by a plurality of processing stages each operating by being supplied with power from a power supply wiring, in a specific processing stage among the plurality of processing stages. In comparison with the address of the instruction being processed and the address stored in the specific instruction address storage means, the address of the specific instruction that stores in advance the address of the specific instruction in which the other processing stage is in the standby state in the processing Comparing means, a next instruction address calculating means for calculating the address of the instruction next to the instruction being processed, and a power supply for selecting whether to supply power to the processing stages from the power supply wiring or to stop the power supply. A selection means and an instruction fetch address storage means for storing the address of an instruction to be fetched next from the outside, The power supply selection means stops power supply to a processing stage in a standby state when the specific instruction detection means detects that a specific instruction is processed, and performs processing in the specific processing stage. Power is supplied to each processing stage when the processing is completed, and the next instruction address calculation means gives the address of the next instruction to the instruction fetch address storage means when processing at the specific processing stage is completed. The data processing device is characterized in that the next instruction is fetched. 5. A data processing device for pipeline processing an instruction fetched from the outside by a plurality of processing stages each operating in synchronization with a clock supplied from a clock supply wiring, wherein: A specific instruction detecting means for detecting that a specific instruction in which another processing stage is in a standby state during processing in a specific processing stage is being processed, and a next instruction for calculating the address of the instruction next to the instruction being processed. Address calculation means, clock supply selection means for selecting whether to supply or stop a clock from the clock supply wiring to each processing stage, and an instruction for storing the address of an instruction to be fetched next from the outside. Fetch address storage means and static storage provided in each processing stage for storing the processing result of each The clock supply selecting means stops the supply of the clock to the processing stage in the standby state when the specific instruction detecting means detects that the specific instruction is processed, and A clock is supplied to each of the processing stages when the processing in the specific processing stage is completed, and the next instruction address calculation means is configured to address the next instruction when the processing in the specific processing stage is completed. Is provided to the instruction fetch address storage means to fetch the next instruction. 6. A data processing device for pipeline-processing an instruction fetched from the outside in a plurality of processing stages each of which operates by being supplied with power from a power supply wiring, in a specific processing stage among the plurality of processing stages. A specific instruction detecting means for detecting that a specific instruction in which the other processing stage is in a waiting state during the processing of 1), and a next instruction address calculating means for calculating the address of the instruction next to the instruction being processed, A power supply selection means for selecting whether to supply power to the processing stages from the power supply wiring or stop the power supply; and an instruction fetch address storage means for storing an address of an instruction to be fetched next from the outside, Power is supplied separately from each processing stage at all times, and static storage means for storing each processing result is provided. When the specific instruction detecting unit detects that a specific instruction is processed, the stage stops supplying power to the processing stage in the standby state, and when the processing in the specific processing stage is completed. To each of the processing stages, the next instruction address calculation means, when the processing in the specific processing stage is completed, supplies the address of the next instruction to the instruction fetch address storage means to output the next instruction. A data processing device characterized by being made to fetch.