JPH01258031A - Data processor - Google Patents

Abstract

PURPOSE:To improve the reliability of branch instruction predicting by connecting a comparator for outputting an operation control signal to a branch instruction predicting part so that the branch instruction predicting part is not driven in an optional address space. CONSTITUTION:An instruction decoding part 2 sends an instruction address signal S2 to be decoded next to current decoding to the branch instruction predicting part 4 and a mask register 7. The register 7 masks the sent signal S2 and sends the masked instruction address to a comparator 9 and an optional address stored in an address register 8 is also sent to the comparator 9. The comparator 9 compares the value sent from the register 7 with the value sent from the register 8 and sends a control signal S4 to the predicting part 4 in accordance with the compared result so as not to drive the predicting part 4.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data processing device, and more specifically,
The present invention relates to an improvement of a data processing device having an instruction pipeline processing function and a branch prediction function for conditional branch instructions.

[Conventional technology]

The general configuration of a conventional data processing device equipped with this kind of instruction pipeline processing function is shown in the block diagram of FIG. 2, and the prediction table used in the branch prediction section of the data processing device is shown in FIG. It is shown in the explanatory diagram.

1. In the configuration of the conventional device shown in FIG. 2, the reference numeral 1 indicates an instruction prefetch queue that creates a queue by prefetching (prefetching control) instructions via the data bus 6, and 2 indicates this instruction prefetch queue. an instruction decode unit that fetches and decodes instructions from the instruction brief fetch queue l; 3;
is an instruction execution unit that actually executes the result decoded by the instruction decoding unit 2; 4 is a branch instruction p1jl11 unit that predicts a branch instruction according to a branch prediction table that will be detailed later; and 5 is the This is a branch destination address generation circuit that generates a branch destination address based on the decoding result of the instruction decoding unit 2. Furthermore, Sl is a branch prediction signal, Sl is an address signal of the next instruction to be decoded, and S3 is currently being executed. This is the instruction address signal.

However, in the case of the device configuration according to this conventional example, while the instruction execution unit 3 is executing the instruction, the instruction decoding unit 2 is decoding the next instruction to be executed, and the previous instruction is being executed. Part 3 execution is over! Immediately, the next instruction that has already been decoded by the instruction decoding section 2 is executed.

Also, in this case, the instruction prefetch queue! Now, using the time when the main memory (not shown) is not being accessed,
By fetching an instruction in advance, the instruction decoding unit 2 fetches (captures) the data of the next instruction to be decoded from this instruction brief fetch queue l.
In this way, the time required for so-called instruction fetching can be reduced.

In other words, in a data processing device equipped with a pipeline processing function, the effective processing speed is increased by operating each of the sections 1 to 3 in parallel.

However, on the other hand, when the flow of instructions is disrupted during the above processing, the decoding result of the instruction decoding unit 2 and the instruction data fetched into the instruction briefetch queue l are canceled, and the instruction briefetch queue l is From the branch destination address specified by the branch instruction,
New queuing will be performed. In other words,
The first instruction to be executed after a branch is executed by a branch instruction is
It must be fetched directly from main memory, and before the instruction is fetched and decoded.

The execution of instructions in the instruction execution unit 3 must be temporarily interrupted.

Therefore, in the configuration of the conventional device described above, in order to improve this point, the branch instruction prediction unit 4 that predicts branch instructions
The branch instruction prediction unit 4 uses the branch instruction address shown in FIG. Each branch prediction bit that predicts whether or not a branch will be taken is stored in pairs, and the stored branch prediction table is used to perform the branch or measurement. It has been found that depending on the method used to create the prediction table, it is possible to predict the flow of a program with a fairly high probability.

Next, the operation of this conventional device will be described in more detail.

The branch instruction detection section 4 sends a branch prediction signal 51 to the instruction decoding section 2 based on the address signal S2 of the next instruction to be decoded by the instruction decoding section 2. In this case, the branch prediction signal Sl is the value of the branch prediction bit shown in FIG. This is a prediction of whether or not it will happen.

On the other hand, when instruction data is taken into the instruction decoding section 2 from the instruction brief fetch queue (2), instruction decoding is started in the instruction decoding section 2, and as a result of this instruction decoding, the decoded instruction is A branch instruction and a branch prediction signal S from the branch prediction unit 4
When l predicts the occurrence of a branch, the instruction data fetched into the instruction briefetch queue 1 is cleared, and based on the decoding result in the instruction decoding unit 2,
In the branch destination address generation circuit 5, a branch destination address is generated, and this branch destination address is passed to the instruction prefetch queue l, and the instruction prefetch queue l also processes instructions according to the branch destination address. Queuing is performed and the fetched instruction data is passed to the instruction decoding section 2.

When the branch prediction is correct, the next instruction to be executed is fetched from the main memory in the instruction execution unit 3 earlier, thereby shortening the waiting time until the ninth instruction is executed. In addition, when the branch prediction is incorrect, the address SJ of the branch prediction bit in the branch prediction 1jjll table shown in FIG. It performs the following operations: (when a branch is taken even though it was not predicted), and erasure (when the branch is taken and the branch is not taken even though it was predicted). branch instruction preliminaries 1111
By adding part 1 and 4, it is possible to suppress random execution of vibe line processing due to branching after execution of a branch instruction, thereby improving the effective calculation processing speed during data processing.

[Problem to be solved by the invention]

In the case of a conventional data processing device equipped with an instruction vibe line processing function, the branch instruction prediction unit 4 is added to predict the occurrence of a branch in a conditional branch instruction, as described above. However, in the case of such a device configuration, on the other hand, in an operating system (hereinafter referred to as O5) that performs multi-task processing, multiple When a user program is running, each time this user program is switched, the branch-r measurement table in the branch instruction prediction unit used in the user program changes to the conditional branch instruction in the OS area. This branch prediction table is rewritten, and as a result,
There is a problem that a conditional branch instruction in the O3 area may disturb the branch prediction 1i111 of the user program and complete the program.

This invention was made to solve these conventional problems, and its purpose is to provide a mask register and an address register, and to properly control each of these registers: It is an object of the present invention to provide a data processing device of this type in which, by setting the branch instruction prediction unit, no operation is performed for an arbitrary address space.

[Means to solve the problem]

In order to achieve the above object, the data processing device according to the present invention masks the address from the instruction decoding section when operating the branch instruction prediction section in a configuration including an instruction pipeline processing function. value and address
The register values are compared, and when these explants match, a control signal is output that does not operate the branch prediction unit.

That is, the present invention provides an instruction pipeline processing function,
and a data processing device having a branch prediction function for conditional branch instructions, comprising an instruction decoding unit that decodes an instruction to be executed next, an instruction execution unit that executes a result decoded by the instruction decoding unit, and the instruction A branch instruction prediction section that supplies a branch prediction signal of a branch instruction decoded by the decoding section to this instruction decoding section, a mask register that masks the instruction address from the instruction decoding section, and an arbitrary address can be set. a comparator that compares the address register, the address from the instruction decoding section masked by the mask register, and the value of the address register, and outputs an operation control signal to the branch instruction prediction section; This is a data processing device characterized by comprising:

[For production]

Therefore, in the case of the present invention, the judgment made by the branch instruction prediction unit based on an arbitrary address can be prevented from occurring depending on the conditional branch instruction in the O8 area, and the reliability of branch instruction prediction can be further improved. .

〔Example〕

Hereinafter, one embodiment of a data processing apparatus according to the present invention will be described in detail with reference to FIG.

FIG. 1 is a block diagram showing a general configuration of a data processing device equipped with an instruction pipeline processing function and a conditional branch instruction branch prediction 11!1 function according to this embodiment. 2, the same reference numerals as those in the conventional structure shown in FIG. 2 represent the same or corresponding parts.

In other words, in the configuration of the embodiment shown in FIG. 1 as well, reference numeral 1 denotes an instruction prefetch queue for prefetching instructions via the data bus 6 to create a queue, and reference numeral 2 denotes an instruction decoding unit for fetching and decoding instructions from the instruction prefetch queue l. , 3 is an instruction execution unit that actually executes the result decoded by the instruction decoding unit 2, and 4 is a branch instruction prediction unit that predicts a branch instruction according to a branch prediction table that sets branch instruction addresses and branch prediction bits. , 5 is a branch destination address generation circuit that generates a branch destination address based on the decoding result of the instruction decoding unit 2, St is a branch prediction signal, S2 is an address signal of the next instruction to be decoded, and S3 is an instruction currently being executed. It is an address signal.

Further, 7 is a mask register for masking the address signal S2 of the instruction from the instruction decoding section 2, 8 is an address register in which a certain arbitrary address is stored, and 9 is the value of the mask register 7. This is a comparator that compares the value of the address register 8 with the value of the address register 8, and S4 is circle A 3 for the branch prediction unit 4.

Therefore, in the configuration of the embodiment, if the decoded instruction is a branch instruction as a result of instruction decoding, and branch prediction No. 13 Sl from the branch prediction unit 4 predicts the occurrence of a branch, The instruction data fetched in the instruction prefetch queue 2 is cleared, and the branch destination address output from the branch destination address generation circuit 5 is received in the instruction prefetch queue l based on the decoding result in the instruction decoding section 2. The instruction prefetch queue 1 queues the instructions according to this branch destination address, and passes the fetched instruction data to the instruction decoding section 2.

In this case, when the branch prediction in the 1-branch instruction prediction unit 4 is correct, the instruction execution unit 3 executes the next instruction in order to fetch the next instruction to be executed from the main memory earlier. The waiting time until execution can be effectively shortened.

Also, when a conditional branch instruction is executed by the instruction execution unit 3, for example, when the instruction is executed for the first time, it may not be registered (stored) in the branch instruction prediction unit 4, or the branch instruction prediction unit 4 is incorrect, the currently executed instruction address signal S3 is sent from the instruction execution unit 3 to the branch instruction prediction unit 4, and the branch instruction address in the branch prediction table shown in FIG. , set or reset branch prediction bits.

In other words, in the instruction decoding unit 2, the current

The address signal S2 of the instruction being decoded is sent to the branch instruction i
The mask register 7 masks the address signal S2 of the received instruction, sends the masked instruction address to the comparator 9, and sends the address signal S2 to the comparator 9. - Any addresses that remain in register 8 are also sent to comparator 9, which compares these values sent from mask register 7 with the values sent from address register 8. Based on the comparison result, a control signal S4 is sent to the branch instruction prediction unit 4 to prevent it from operating.

In this case, the O5 area and the user program area in memory are distinguished from each other by the most significant bit of their address, and this most significant bit is "1".
” area indicates the O3@ area, and the “0” area indicates the user
Shows the program area.

Therefore, in order to prevent branch prediction from being performed when a conditional branch instruction in the Moeki OS area is executed, masking and
All but the most significant bit of the address is masked in register 7, and the most significant bit in address register 8 is set to "1" and all other bits are set to "0".

Therefore, in this case, the instruction in the O8 area is sent to the instruction decode unit 2.
and the resulting value whose address is masked by mask register 7 and address register 8.
In this case, comparator 9 outputs:
A control signal S4 that stops the operation of the branch instruction prediction unit 4 is output, and the branch prediction signal Sl from the branch instruction prediction unit 4 always predicts "no branch", and
Even when a branch occurs in the instruction execution unit 3, the branch prediction table is
There is no pull retelling.

That is, in this way, with the device configuration according to this embodiment, it is possible to prevent branch prediction from being performed for instructions in a certain area.

In the above embodiment, the branch instruction prediction unit is not operated for instructions in the O8 area, but by appropriately setting the values of the mask register and address register, instructions in any area can be executed. Of course, it is possible to similarly disable the branch instruction prediction unit.

〔Effect of the invention〕

As described in detail above, according to the device of the present invention, in a data processing device having an instruction vibe line processing function and a conditional branch instruction branch prediction function, a mask masking function is used to mask an instruction address from an instruction decoding section. In addition to providing a register and an address register that can set an arbitrary address, the value of the address masked by the mask register from the instruction decoding unit is compared with the value of the address register, and the address register is set to the branch instruction prediction unit. A comparator that outputs an operation control signal is provided, and the operation of the branch instruction prediction unit is configured to be negligible for instructions in a certain area of memory. Even when a user program is running, the fear that the conditional branch or prediction of the user program will be incorrect due to the influence of the conditional branch instruction in the O5 area is eliminated, and the reliability of branch instruction prediction is reduced due to the fear. can be further improved.

[Brief explanation of the drawing]

FIG. 1 shows a command vibe line processing function according to the present invention.
FIG. 2 is a block diagram showing a general configuration of an embodiment of a data processing device equipped with a branch prediction function for conditional branch instructions; FIG. FIG. 3 is an explanatory diagram showing a prediction table used in the branch prediction unit same as above. l...Instruction briefetch queue, 2...Instruction decoding unit, 3...Instruction execution unit, 4...Branch instruction prediction unit, 5...Branch destination address generation circuit, 6 ...
・Data bus, 7...Mask register, 8...
・Address register, 9... Comparator. Sl: Branch prediction signal, Sl: Address signal of the next instruction to be decoded, S3: Address signal of the instruction currently being executed, S4: Control signal. Agent Masuo Oiwa Diagram 3 procedural amendment (voluntary) 1.1G display Patent application No. 1986-86111 j3
．． Person making the amendment 1 (Relationship to the matter Patent applicant address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki 1゜Agent address: Chiyoda, Tokyo Mitsubishi Electric Corporation, 2-2-3 Marunouchi, Ward Name (7375) Patent Attorney Masuo Oiwa (Contact information 03 (213) 3421 Patent Department) -6 Contents of amendment (1) Specification page 5, line 3 - "Will it branch?" in lines 4 and 19 will be corrected to "will it branch?" (2) "Tsum 9" in line 7, page 13 of the same book, will be corrected to "further." (3) Page 13 of the same book, line 7. Correct "this case" in the row to "case of this embodiment." (4) Correct the drawings in FIGS. 1 to 3 as shown in the attached sheet.

Claims (1)

[Claims] A data processing device that has an instruction pipeline processing function and a branch prediction function for conditional branch instructions, and includes an instruction decoding unit that decodes the next instruction to be executed and a result decoded by this instruction decoding unit. an instruction execution section; a branch instruction prediction section that supplies a branch prediction signal of a branch instruction decoded by the instruction decoding section to the instruction decoding section; a mask register that masks an instruction address from the instruction decoding section; Compares an address register in which an arbitrary address can be set with an address from the instruction decode section masked by the mask register and the value of the address register, and sends an operation control signal to the branch instruction prediction section. A data processing device comprising: a comparator for outputting data.