JPS58137048A - Branch instruction control system - Google Patents

Abstract

PURPOSE:To improve the performance of information processing remarkably, by changing the memory address of an instruction to be prefetched in response to the prefetch address information. CONSTITUTION:When the instruction of an instruction register 9 inputted at an instruction decoder 10 is interpreted other than the address instruction with a discrimination bit 1 of an instruction code, a signal line 29 is set off and an instruction buffer 3 is renewed with a signal line 24. In case of a prefetch address designation instruction, the signal line 29 is set on, and the prefetch address information and branch success/failure information are given to prefetch discrimination section 12. The section 12 compares the information 2 with the success/failure of branch due to execution and transmits a signal being set on when coincident and off when dissident to signal lines 27, 28. Thus, the memory address of the instruction to be prefetched is changed in response to the prefetch address information.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control system for branch instructions in information processing 4fc#.

In general, an information processor 4fi, * processor executes a program by repeating the remaining four steps (+2), +4) may be omitted depending on the instruction).

+1) Fetch the next instruction from memory (2)
(3) Execute an instruction (4) Write a result There are two types of conventional processor execution steps: (3) execute an instruction one after another; and (4) write a result. The first is to execute these steps in series, and the second is to fetch 7 more consecutive instructions from memory, store them in an internal memory dedicated to prefetching called an instruction buffer, and execute them sequentially. It is something. In the case of method al, the next instruction is fetched from memory after the currently executing instruction is completely completed, whereas in the case of the second method, the next instruction is fetched from memory after the execution of the previous instruction without accessing the program memory. Since the instructions already stored in the instruction buffer can be executed immediately, the time required for fetching can be significantly reduced.

But 1. In the case of method ig2, when executing a branch instruction that changes the flow of instruction execution, all subsequent instruction streams after the branch instruction stored in the instruction buffer are invalidated, and the branch destination is There is no need to fetch a new instruction from the address. Furthermore, it is particularly difficult to control in advance conditional branch instructions that operate on the operands of an instruction and determine whether or not the branch is successful or unsuccessful based on the result.

In order to overcome the above-mentioned drawbacks, in the conventional technology, two or more instruction buffers for prefetching instructions, a control circuit thereof, and a detection circuit for branch instructions are provided, thereby effectively dealing with prefetching after a branch instruction. A method is being considered. That is, it prefetches an instruction, detects whether the instruction is a branch instruction at point 9, calculates the branch destination address if it is an unconditional branch instruction, and continues prefetching from that address. , taking both cases of branch success and failure into account, the prefetch from the branch destination address, i.e., the sub-instruction stream, and the prefetch in the case of no branch, i.e., the main instruction stream, are carried out in parallel into two instruction buffers. It is something. Therefore, when actually executing a conditional branch instruction, one of the two instruction streams is selected depending on whether the branch is successful or unsuccessful, and subsequent execution is performed using that stream.

゛This method is often used in large computers that require high-speed processing, along with the so-called pipeline control method that processes many instructions in parallel. Since even the main instruction stream that must be executed after execution is completely invalidated by a successful branch, there is a drawback that the instruction must be re-executed from the branch destination instruction.

An object of the present invention is to provide a branch instruction control method that can quickly return to the main stream to be executed after execution of the sub-stream even when executing a sub-stream by a branch instruction. If the memory address of the instruction does not branch, that is, whether it is a normal address or a branch destination address, the memory has a memory set with a branch instruction that has prefetch address information in the instruction code, and the prefetch address information This makes it possible to change the memory address (of the instruction to be preempted accordingly), which effectively prevents the invalidation of the preempted 9 minutes of the main instruction stream due to a branch, and To obtain a branch instruction control method capable of shortening the time required for re-fetching or re-executing a main instruction stream, allowing the continuation of the main instruction stream to be executed continuously after branch processing, and greatly improving information processing performance. An embodiment of the present invention that can perform the following will be described in detail with reference to the drawings. Fig. 1 is an instruction code diagram showing instruction word format defects, Fig. 2 is a schematic block diagram of a processing device using only one instruction buffer, which is an embodiment of the present invention, and Fig. 3 (al) shows a loop. FIG. 3(b) is a flowchart showing five examples of progera programs including FIG. 3(b), and FIG.

In FIG. 1, the instruction word set in the memory consists of an instruction code part and an operand part, and the instruction code part contains a discrimination pin (1%) and 1% (1%) indicating whether or not the instruction specifies a preemptive sea address. Indicates that 2 bits are held for specifying whether the preemptive address is an address in case no branch is taken or a branch destination address. In Figure 2,
3 is an instruction buffer, 4 and 11 are operand calculation units, 5
is the detection circuit, 6 is the pre-emption 9 address #lJ# circuit, 7 is 7
)'res save, -(ffa, 8 is pre-emption small instruction register,
9 is an instruction register, 10 is an instruction decoder, 12 is a preemption determination circuit, 13 is a prefetch address register, 14 to 23 are buses, and 24 to 32 are control signal lines.

The determination bit l in the instruction code is 111 for a preemption addressing instruction and 101 for other instructions.

Further, determination bit 2 is 111 if the prefetch address designation is a branch destination, and is a □ I if it is a normal address.

The detection circuit 5 detects whether or not the prefetched 9 instructions are register address specified branch instructions via the memory path 16, with reference to determination pin 1. If detected, the branch destination address is calculated by the operand calculation unit 4 and transferred to the path 18, the 1+, normal destination 4L#) address is held, and its contents are transferred from the 9 first 9 address register 13 via the bus 17. and forward it.

Each of these is input to the pre-emption nine address control circuit 6.

Furthermore, the detection circuit 5 sends information 1 indicating whether or not it is a prefetch address designation command and prefetch address information 2 that determines whether the prefetch 9 designation is a branch destination or a normal address to the prefetch address control circuit via signal lines 25 and 26, respectively. Enter 6. In this prefetch address control circuit 6, the signal IIIz
If s is OFF, that is, it is not a pre-fetch 9 address designation command, the previous pre-fetch address input from bus 17 is incremented and output to bus 14.15.

If the signal lines 25 and 26 are both KON, that is, the prefetch address I designation instruction and the prefetch address information 2 is the branch destination, the branch destination address input from the bus 18 is output to the bus 14 and 15, and at the same time, the branch destination address input from the bus 18 is output to the bus 14 and 15. ]Entered normal pre-emption 9
Save the address in the address save buffer 7 via the bus 23 ◎Signal line 25 is ON and signal line 26 is OFF
F, that is, if it is a prefetch address designation command and the prefetch 9 address information 2 is a normal prefetch address, contrary to the case where the 9 signal line 26 is ON, the normal data input from the bus 17 to buses 14 and 15 is The prefetched address is output and saved in the address save buffer 7 via the branch destination 7YV bus 23 input from the bus 18 at the same time. The prefetch address output from the prefetch address control circuit 6 in this manner is latched into the prefetch address register 13 via / The next prefetch instruction is fetched into the prefetch instruction register 8 via the bus 16. At this time, the contents of the previous instruction fetched into the prefetch address register 8 are stored into the instruction buffer 3 via the bus 19. Ru.

The above prefetching is performed continuously until the instruction buffer is full, and when it is full, Axz is read from the instruction buffer 3.
This loss of place is performed once every time the instruction is output to the instruction register/9 via x.

Next, the operation when the instruction latched in the instruction register 9 is executed will be described. First, in the instruction decoder lO, if the instruction in the instruction register 9 input via the bus 22 is decoded as other than a prefetch address designation instruction by the judgment bit l of the instruction code, the signal line 29 is
F, F, this notifies the prefetch address control circuit 6 via the signal line 32 that normal prefetching is to be continued, and updates the instruction buffer 3 via the signal line 24. As a result of the decoding, if it is a prefetch address designation command, the signal line 29 is turned ON, and the prefetch address information 2 is transmitted via the signal line 30 to the obef/de arithmetic unit 11.
Information on whether the branch is successful or unsuccessful is input to the pre-emption 9 determination unit 12 via the signal line 31. The preemption 9 determination unit 12 receives the information on the signal lines 29, 30.31, outputs the fact that there is a specification to the signal line 33.34, and outputs the preemption address information 2 and the success or failure of the execution branch. A signal is output to the signal lines 27 and 28 to turn the signals OFF and OFF if they match, and to turn ON if they do not match.

If the signal line 2B is ON, the instruction buffer 3 knows that the specified prefetch has failed, and invalidates all stored instruction streams. In this case, signal line 27 is also turned on at the same time.
In response to this, the prefetch address control circuit 6 outputs the address saved in the address save buffer 7 to the buffer 14.15, and starts refilling the instruction buffer 3 anew.

The above operation will be explained using an example of a program including a loop that repeatedly executes the same process in a fixed circuit.

An example of a program flow including a loop is shown in Fig. 3 (a). ◇The program flow is as follows: After executing the instructions at addresses 100 and 101, after returning the instructions at addresses 102, 103, and 104 for a constant N times, 105 and 106 are executed. The instruction at address 104 (LOOP 102) makes the branch to address 102 successful in the first (N-1) executions, makes the branch unsuccessful in the Nth execution, and sets the prefetch address to address 102. This is an instruction to specify.

When this instruction is prefetched into the prefetch instruction register 8, it is detected that it is a prefetch address designation instruction, and the prefetch address is set to address 102 for subsequent prefetching, and the save address is set to address 105 and stored in the address save buffer 7. The prefetch after 0 (LOOP 102) to be saved is always performed from address 102 because the prefetch 9 address is specified as the branch destination. This prefetch is shown in FIG. 3+b). Out of the N executions of the instruction (LOOP102), only the last instruction stream *a is invalidated, and the instruction buffer is refilled at address 105 by referring to the address 105 saved in the address save buffer 7. However, by specifying (preemption (N-1) times), processing is performed at high speed.

If it is known that there is a high probability of branching due to the nature of the instruction, such as (LOOP) mentioned above, the preemption address may be designated as the branch destination regardless of the type of processing. Also,
In the case of a general conditional branch instruction, for example, an instruction that branches if it is I 1 g, the probability of branching is high or low depending on the type of processing, so the probability All you have to do is decide whether to use the preemption address as a branch destination or a normal address.The above example uses only one instruction buffer, but a pipeline using two or more instruction buffers can be used. According to the present invention, even in a geographical device, the main commands) IJ-
By executing a branch instruction existing on the stream, the probability of branching to the sub-instruction stream decreases, and accordingly, the probability that all pre-empted main instructions x dreams after the branch instruction will be invalidated also decreases. That is clear. □ As is clear from the above explanation, according to the present invention, it is possible to effectively prevent invalidation of the instruction stream after one branch instruction when the probability of whether or not a branch will succeed is known in advance. This can greatly improve the performance of information processing devices.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the instruction word format, Fig. 2 is a block diagram showing an embodiment of the present invention, Fig. 3 1) is a flow diagram showing a program example including a loop, and Fig. 3 1b) is a state of prefetching. FIG. 1... Prefetch address specification instruction determination bit, 2
...Preemptive furnace address specification bit, 3...°...
・Instruction buffer 1.4.11...Operand calculation unit, 5...Detection circuit, 6...Preemptive seat address control circuit, 7...Tedless save Register, 8... Prefetch instruction register, 9...
・Instruction register, 10...Instruction decoder, 12
...? . . . Preemption determination circuit, 13 . . . Preemption address register. No. 1 Bad Order Cor F# Saix Run F# 05 1ρδ Amendment of Meeting Procedures (Voluntary) 57.6-3 Showa Year Month Date Commissioner of the Japan Patent Office 1, Indication of the Case 1939 Patent Application No. 1862:
No. 1, No. 2, Title of the invention: Branch instruction control method 3, Relationship with the amended person case Applicant: 5-33-1-4, Shiba 5-chome, Minato-ku, Tokyo, Agent: 5-37 Shiba, Minato-ku, Tokyo 108 No. 8 Sumitomo Sanda Building NEC Corporation (6591) Patent Attorney Uchihara 1 Telephone Tokyo (0
3) 456-3111 (Main representative) (Contact information: NEC Corporation Patent Department) Contents of amendment in column 6 of "Detailed explanation of the invention" of the specification a) "Explanation" on page 1, line 10 of the specification Correct to "decipher". (Example) Page 4 of the specification, lines 13 to 15, ``According to...''
. . . "Return" is corrected to "It is possible to effectively select the main stream or sub stream when prefetching future instructions."

Claims (1)

[Claims] It is configured to perform processing after reading in advance.
In an information processing device, the memory of the instruction to be prefetched
A branch instruction having prefetch address information that specifies whether the address is an address when no branch is taken or a branch destination address is explained, and the memory address of the instruction to be prefetched can be changed according to the prefetch address information. A branch instruction control method.