JPH0877037A - Jamming device - Google Patents

Abstract

PURPOSE: To set a jamming code which is longer than the length of a basic instruction and to perform flexible jamming processes with plural instructions. CONSTITUTION: The jamming device which actualizes a break of a user program by an in-circuit emulator has a break point detecting means 1 which detects a break point in the user program, a jamming code holding means 3 which holds at least two instructions codes used in jamming, and an output selecting means 5 which outputs the jamming code or instruction codes of the user program and is equipped with a jamming control means 7 which outputs all instruction codes held by the jamming code holding means 3 to the output selecting means 5 in order when the break point detecting means 1 detects the break point.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an in-circuit emulator, and more particularly to a jamming device effective for realizing a break of a user program.

[0002]

2. Description of the Related Art In-circuit emulators use a technique called jamming as a means for realizing a break in execution of a user program.

A conventional jamming device will be described below. As shown in FIG. 3, the conventional jamming apparatus includes an address comparison circuit 9, a jamming memory 11 that holds one jamming instruction, and a selection circuit 13.

Next, the operation of the conventional jamming device will be described. In the conventional jamming device, when an instruction of an address targeted for a break is executed, The address comparison circuit 9 detects the instruction fetch of the address to be the break target. 2. When detected, the jamming instruction code preset in the jamming memory 11 is output to the selection circuit 13. 3. The selection circuit 13 outputs the jamming instruction code to the data bus (not shown) when the jamming instruction code is input, and otherwise outputs the user program instruction code (not shown). ) Is output. 4. The instruction output by the selection circuit is output to the CPU (not shown) via the data bus, and if necessary, the control is transferred to the debugger program and the branch instruction to the address is repeated. Then, the debugger performs necessary control.

With such a method, the instruction code of the user program is replaced by the hardware of the in-circuit emulator, so that there is no problem even if the CPU is prefetching instructions or performing pipeline processing.
It is possible to realize a break before execution. Note that this jamming is performed only when the instruction part of the instruction code is fetched.

[0006]

However, in the conventional method using the jamming apparatus, when the instruction code for setting the breakpoint has an instruction length of 2 or more and the breakpoint is set between the instruction lengths of the instructions. When the processing returns from the branch destination, the processing will start from within the instruction length of the instruction. In this case, since the instruction starts in the middle, the instruction becomes meaningless at all. Therefore, in order to avoid the above-mentioned problems, there are the following restrictions.

1. The instruction code for setting a breakpoint is the minimum instruction length of the CPU. 2. Inevitably, when jamming with a plurality of breakpoint setting instruction codes, a breakpoint cannot be set between the instruction lengths of the jamming instructions.

The above limitation is that the minimum instruction length of the CPU is 1.
A CPU having 6 bits or more may not cause any particular problem, but a basic instruction length of 8 bits (1 byte) such as Z80 cannot provide sufficient control. That is, if the basic instruction length is short, the intended processing may not be realized, so that there is a large limitation in the range that can be controlled by jamming.

The present invention has been made in view of the above circumstances, and an object thereof is to enable setting of a jamming code longer than the basic instruction length and to realize flexible jamming processing by a plurality of instructions. Is to

[0010]

To achieve the above object, the present invention relates to a jamming device for realizing a break of a user program by an in-circuit emulator, and a break point detecting means for detecting a break point in the user program. , A jamming code holding means for holding at least two instruction codes used for jamming and an output selecting means for outputting the jamming code or the instruction code of the user program, and the breakpoint detection means detects a breakpoint. In this case, a jamming control means for sequentially outputting all the instruction codes held by the jamming code holding means to the output selecting means is provided.

Here, when the output selection means outputs the instruction code held by the jamming code holding means, the break point detection means interrupts the detection of the breakpoint and the CPU branches. When the instruction is executed, it is desirable to restart the detection of the interrupted breakpoint.

[0012]

In the present invention, 1. Breakpoint detecting means for detecting a breakpoint in the user program. 2. A jamming code holding means capable of holding at least two instruction codes used for jamming. 3. Output selecting means for outputting the jamming code or the instruction code of the user program When a break point is detected by the break point detecting means, a jamming control means for sequentially outputting all the instruction codes held by the jamming code holding means to the output selecting means is provided. The holding means holds a plurality of jamming instruction codes, and the jamming control means sequentially outputs all the instruction codes held by the jamming code holding means to the output selecting means, thereby jamming by a plurality of instruction codes. Can be realized.

[0013]

FIG. 1 is a block diagram of an embodiment according to the present invention. The jamming apparatus according to the present invention holds an address comparison circuit 1 for detecting an address at which a break occurs by comparing the contents of an address bus of a CPU (not shown), and n words (n pieces) of instruction codes for jamming. The jamming memory 3 that can be used, the selection circuit 5 that selects one of the contents of the jamming memory and the user's instruction code, and when the address comparison circuit detects a match signal, the contents of the jamming memory are selected from the first address And a control circuit 7 for outputting and selectively outputting the contents of the jamming memory to the selection circuit.

The operation of the jamming apparatus according to the present invention will be specifically described below, and how the jamming break is realized will be described with reference to FIGS. 1 and 2. Note that FIG. 2 shows a case where the jamming instruction code is 4 words (pieces). 1. When the address comparison circuit 1 detects an address for which a break is desired from a CPU (not shown) via an address bus (not shown), it outputs a message to this effect to the control circuit 7. 2. In response to this, the control circuit 7 synchronizes with the instruction read signal of the CPU and synchronizes with n words (n = 2, 3, 4, ...
The signal for selecting the first word of the jamming coat is output to the jamming memory. 3. The jamming memory 3 outputs the first word of the jamming coat to the selection circuit according to this signal. 4. The control circuit 7 outputs a signal for selecting the second word to the jamming memory assuming that the first word of the jamming code has been fetched because the data obtained by the instruction fetch of the CPU becomes invalid. 5. When there is an output from the jamming memory 3, the selection circuit 5 outputs the output of the jamming memory 3 to the CPU.
Of the instruction code of the user program in other cases. 6. Hereinafter, this procedure is repeated, and C is executed by a branch instruction or the like.
This procedure is repeated until the signal when the PU fetch (prefetch) is wasted, that is, the signal in which the instruction queue is flushed is detected or all the jamming codes are output. It should be noted that the control circuit ignores the coincidence signal sent from the address comparison circuit until the instruction queue is flushed or all the jamming codes are output even if the coincidence signal is sent out. By performing the above procedure, the CPU fetches the contents of the jamming code and performs the processing.

Next, the case where the instruction fetch starts from the instruction at the address next to the breakpoint will be described. In this case, the address comparison circuit does not output the detection signal, so that a series of jamming processes is not performed. Therefore, the instruction execution to the address next to the breakpoint is not affected at all. Further, when the instruction fetch is completed in the middle due to the execution of the branch instruction or the like, the address comparison is restarted from the beginning, so that the problem does not appear from the branch instruction. With such a configuration, it is possible to easily control even when jamming requires a plurality of words of instructions.

[0016]

As described above, the jamming apparatus according to the present invention has the means for holding a plurality of jamming instruction codes, so that it is possible to perform jamming by a plurality of word instructions. Further, various processes required by the debugger program can be realized by jamming, so that more flexible and fine control is possible, and a better debugger can be constructed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a jamming device according to the present invention.

FIG. 2 is a diagram showing a time chart for explaining when jamming is being performed by the jamming apparatus according to the present invention.

FIG. 3 is a block diagram showing a schematic configuration of a conventional jamming device.

[Explanation of symbols]

 1 Address Comparison Circuit 3 Jamming Memory 5 Selection Circuit 7 Control Circuit 9 Address Comparison Circuit 11 Jamming Memory 13 Selection Circuit

Claims (2)

[Claims] 1. A jamming device for realizing a break of a user program with an in-circuit emulator, a break point detecting means for detecting a break point in the user program, and a jamming code for holding at least two instruction codes used for jamming. Holding means and output selecting means for outputting the jamming code or the instruction code of the user program are held by the jamming code holding means when a breakpoint is detected by the breakpoint detecting means. And a jamming control means for sequentially outputting all the instruction codes to the output selection means. 2. The breakpoint detecting means interrupts the detection of the breakpoint when the output selecting means outputs the instruction code held by the jamming code holding means, and the CPU branches the branch instruction. The jamming apparatus according to claim 1, wherein detection of the interrupted breakpoint is restarted when is executed.