JPS60198640A - Pipeline type information processor - Google Patents

Abstract

PURPOSE:To improve the instruction executing speed of a pipeline type information processor by using a means which decides an instruction that is executed after a repetition control instruction. CONSTITUTION:The instruction groups are stored in a main memory unit 1 and then extracted with an indication of a prefetching unit 2. The type of an extracted instruction is decoded by a decoding unit 3 and stored in a decoding queue of the unit 3. An executing unit 4 extracts successively the instructions out of the decoding queue and executes them. The instruction extracted by the unit 2 is supplied to a buffer 11 and decoded by a decoder 12 to be put into a decoding queue 13. Then the unit 4 extracts instructions out of a queue 15 and executes them. The instruction that is executed after a repetition control instruction is decided by the value of a counter 31 of the unit 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a pipeline type information processing device. In particular, the present invention relates to a pipeline information processing device that prefetches and decodes instructions in parallel with the execution of instructions.

[Description of prior art]

In a conventional pipeline information processing device in which instruction prefetching, instruction decoding, and instruction execution are performed in parallel, when a repeat control instruction is decoded, subsequent instruction prefetching and decoding are stopped, and the repeat control instruction is After waiting for execution and determining the repetition condition, fetching and decoding of the next instruction to be executed according to the condition is resumed.

Therefore, since the instruction following the repeat control instruction is fetched, decoded, and executed in series, the execution time of the instruction becomes longer.

[Purpose of the invention]

SUMMARY OF THE INVENTION The present invention aims to solve the above-mentioned drawbacks, and provides a pipeline information processing device with improved instruction execution speed.

[Key points of the invention]

The present invention provides a pipeline information processing device that performs prefetching and advance decoding of instructions, including: 1. an instruction decoder; circuit means for generating one or more decoding queues for holding information decoded by the decoder; A counter that holds the number of repetitions of an instruction sequence and performs subtraction to "1"; a first detection circuit that detects that the value of the counter is "1"; and a circuit that generates the decoding queue. A second detection circuit detects whether the instruction to execute and the currently executing instruction change the contents of the above counter, and after subtracting the value of the above counter by "1", the value of the above counter is rOJ Lt tL &t : Branches to the address specified by the operand, and if it is "0", proceeds to the next instruction.In a repeat control instruction, when the repeat control instruction is decoded, it repeats from the information of the first detection circuit and the second detection circuit. The method is characterized by comprising means for determining an instruction to be executed next to the control instruction.

[Explanation based on examples]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be explained based on the drawings.

FIG. 1 is a block diagram showing the configuration of the apparatus of this embodiment, FIG. 2 is a block diagram showing the configuration of the decoding unit in FIG. 1, and FIG. 3 is a block diagram showing the configuration of the decoding unit in FIG. FIG. 3 is a block configuration diagram showing the configuration of a counter section included in the unit.

First, the configuration of this embodiment device will be explained based on FIGS. 1, 2, and 3. This embodiment device includes a main memory unit 1, a prefetch unit 2, and a decoding unit 3.
The decode unit 3 includes an instruction buffer 11, a decoder 12, an instruction decode first queue 13, and an instruction decode second queue 14.
, an instruction decode third queue 15 , a counter change detection circuit 18 , and an execution instruction determination circuit 19 .The counter section of the execution unit 4 includes a counter 31 and a counter 31 ;
It is composed of a "1" circuit 32 and a "1" detection circuit 33.

The instruction output of main memory unit 1 is connected to the instruction input of prefetch unit 2, the instruction output of prefetch unit 2 is connected to the instruction input of decode unit 3, and the instruction output of decode unit 3 is connected to the instruction input of execution unit 4. be done. Here, in the decoding unit 3, the instruction buffer 11
The instruction output of the decoder 12 is connected to the first instruction input of the decoder 12, and the instruction output of the decoder 12 is connected to the instruction decode first queue 1.
3, the first instruction input of the second instruction decode queue 14, and the first instruction input of the third instruction decode queue 15, respectively.
The instruction output of the second instruction decode queue 14 is connected to the second instruction input of the second instruction decode queue 14, and the instruction output of the second instruction decode queue 14 is connected to the second instruction input of the third instruction decode queue 15.

A second signal output of the decoder 12 is connected to a signal input of the counter change detection circuit 18 .
The signal output of the decoder 12 is connected to the first signal input of the execution instruction determination circuit 19, and the second signal output of the decoder 12 is connected to the second signal input of the execution instruction determination circuit 19. The first signal output is connected to the signal input of the decoder, and the second signal output of the execution instruction determination circuit 19 is connected to the signal input of the execution unit. Further, in the counter section of the execution unit 4, the signal output of the counter 31 is r-
The signal input of the IJ circuit 32 and the signal input of the "1" detection circuit 33 are connected, the signal output of the r-IJ circuit 32 is connected to the input of the counter 31, and the signal output of the "1" detection circuit 33 is connected. is connected to the third signal input of the execution instruction determining circuit of the decoding unit 3.

Next, the operation of this embodiment device will be explained based on FIGS. 1 to 3.

First, as shown in FIG.
, and is retrieved from the main memory unit 1 according to instructions from the prefetch unit 2.

The instruction fetched by the prefetch unit 2 is decoded by the decode unit 3 to determine the type of instruction, and is stored in a decode queue in the decode unit 3. In the execution unit 4, the decoded instructions are taken out in order from this decode queue and executed.

Next, the operation of the counter portion included in the decoding unit 3 and execution unit 4 according to the present invention will be explained based on FIGS. 2 and 3. The instruction fetched by the prefetch unit 2 is put into the instruction buffer 11 and sent to the decoder 1.
It is decoded in 2. The decoded information is placed in the instruction decode first queue 13. Here, the contents of the instruction decode first queue 13 enter the instruction decode second queue 14 when the instruction decode second queue 14 becomes empty, and further enter the instruction decode third queue 15 when the instruction decode third queue 15 becomes empty. . However, when the first instruction decode queue 13, the second instruction decode queue 14, and the third instruction decode queue 15 are empty, the decoded result is directly put into the third instruction decode queue 15. Similarly, when the first instruction decode queue 13 and the second instruction decode queue 14 are empty and the third instruction decode queue 15 is not empty,
The decoded result is directly put into the second instruction decode queue 14. When all three instruction decode queues are not empty, decoding in the decoder is stopped until the first instruction decode queue 13 is empty.

In the execution unit 4, when the currently executed instruction is completed, the next instruction to be executed is taken out from the third instruction decode queue 15.

Here, in the counter 31 included in the execution unit 4,
The number of repetitions of the repetition control command is held. The counter change signal 16 becomes "1" when the decoder 12 decodes an instruction that changes the value of the counter 31, and becomes "0" when the decoder 12 decodes an instruction that does not change.

In the counter change detection circuit 18, the counter change signal 16
is input, and there is an instruction to change the value of the counter in the instruction decode first queue 13, instruction decode second queue 14, instruction decode third queue 15, or any of the instructions currently being executed in the execution unit 4. is stored, and if it exists, the counter change detection signal 21 is set to "1".
If it does not exist, it is output as "0". If a repetition control command exists in the command buffer 11, it is decoded by the decoder 12 and the repetition control command decode signal 17 becomes "1". Also, the value of the counter 31 is “1”.
”, the “1” detection signal 34 becomes “1”.

The execution command determination circuit 19 determines the command to be executed next to the repetition control command based on the repetition control command decode signal 17, the counter change detection signal 21, and the "1" detection signal 34. That is, when the repetition control command decode signal 17 is "1", the counter change detection signal 2I is "0", and the "1" detection signal 34 is "0", the branch signal 22 becomes 0, and the repetition control is performed. The program advances to the next instruction, and when the "1" detection signal 34 is "1", the branch signal 22 becomes 1 and the program branches to the address specified by the repeated control command. If the repetitive control instruction decode signal 17 is “1” and the counter change detection signal 21 is “1”, the instruction currently being executed by the execution unit 4 and the repetitive control instruction currently being decoded by the decode unit 3 are Since this indicates that there is an instruction that changes the value of the counter 31, the execution instruction determining circuit 19 outputs the decoding stop signal 20 at "1" and the decoding of the repeat control instruction is temporarily stopped. . counter, 31
When the execution unit 4 finishes executing the instruction to change the value of , and the value of the counter 31 is determined, the counter change detection signal 21 becomes "0" and the decoding stop signal 20 becomes "0".
Then, decoding of the repeat control command is restarted by the decoder 12.

Next, the counter 31 is decremented one by one by "-1" times*32 each time the repeated control command is executed. If the value of the counter 31 is not "0", the repetition control instruction branches to the address specified by the operand, and
If it is OJ, proceed to the next command. The "1" detection circuit 33 is a circuit that detects that the value of the counter 31 is "1", and when "1" is detected, the "1" detection signal 34 becomes "1".
become. When the value of the counter 31 is "1", it is executed next ("1" is subtracted by the repeat control command,
The counter 31 becomes "0" and the program proceeds to the next instruction without branching. Therefore, if the value of the counter 31 is not changed, by checking whether the value of the counter 31 is "1" at the time of decoding the repetition control command, the command is executed next to the repetition control command. Able to determine orders.

〔Effect of the invention〕

As described above, the present invention has the effect of shortening the execution time of an instruction executed next to a repeat control instruction in a pipelined information processing device.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing the configuration of an embodiment device. FIG. 2 is a block diagram showing the configuration of the decoding unit shown in FIG. 1. FIG. 3 is a block configuration diagram showing the configuration of a counter section included in the execution unit shown in FIG. 1. 1... Main memory unit, 2... Prefetch unit, 3
...Decode unit, 4...Execution unit, 11
...Instruction buffer, 12...Decoder, 13...
Instruction decode first queue, 14... Instruction decode second queue, 15... Instruction decode third queue, 18...
- Counter change detection circuit, 19... Execution instruction determination circuit, 31... Counter, 32... "-1" circuit, 33
..."1" detection circuit. Patent applicant: NEC Corporation Representative Patent attorney: Naotaka Ide

Claims (1)

[Claims] (1) In a pipelined information processing device that executes instruction prefetching and advance decoding, an instruction decoder, circuit means for generating one or more decoding queues for holding information decoded by the decoder, and an instruction sequence. a counter that decrements by ``1'' every time ``1'' is repeated; a first detection circuit that detects that the value of the counter is ``1''; an instruction existing in the circuit means that generates the decoding queue; a second detection circuit that detects whether the currently executed instruction changes the contents of the counter; and a second detection circuit that is specified by an operand if the value of the counter is not "0" after subtracting the value of the counter by rIJ. In a repetition control instruction that branches to an address and proceeds to the next instruction if it is "0", execution is executed next to the repetition control instruction based on the information of the first detection circuit and the second detection circuit at the time of decoding the repetition control instruction. 1. A pipeline information processing device, comprising: means for determining an instruction to be executed.