JPS6257028A - Branch control system in information processor of pipeline control - Google Patents

Abstract

PURPOSE:To decrease the execution cycle after release of interlock by executing the calculation of a branch destination address and the fetch of a target instruction precedingly when a branch instruction is interlocked. CONSTITUTION:In the flow of a branch-on counter instruction (BCT), when the instruction is interlocked in the AW cycle of the instruction just before, an address computing element (OEAG) 24 is used, the address of branch destination is calculated at the 2nd cycle D. In the flow of the target instruction next, an address from the BCT instruction is sent as an output of the OEAG 24, it is given in an instruction effective address register IEAR 30a to apply the instruction fetch from an instruction fetch local buffer memory IF-LBS 30 and the result is set to an instruction address register IARB 33 for the succeeding instruction fetch. The fetched instruction enters an instruction word register 31 or 32, whether or not the BCT instruction is to be fetched is executed to select either of the register 31, 32 and an instruction is given to the pipeline.

Description

[Detailed Description of the Invention] [Summary] In a pipeline-controlled information processing device, when a branch instruction becomes interlocked in an address calculation cycle, calculation of the branch destination address and fetch of the target instruction are performed in advance. By executing this, the execution cycle after the interlock is released is shortened.

[Industrial application field]

The present invention relates to an instruction execution control method in a pipeline-controlled information processing device, and particularly to a control method for branch instructions during a preceding instruction interlock.

[Conventional technology]

In an information processing device that uses one-cycle pipeline control, the pipeline is basically made up of multiple stages.
Provides instructions every cycle.

By processing multiple instructions in parallel by shifting them stage by stage in each cycle, processing speed is increased.

For example, an operation sequence as shown in the first-order flow is taken.

Command → DATBEW Command → DATBEW Command → DATBEW here.

D = instruction decode A near address generation T-near address conversion B: Buffer E: Execute W:Write represents each cycle.

Such pipeline-controlled information processing devices often use a BCT (branch on counter) instruction, which is one of the branch instructions, to construct a loop that repeats the same process a certain number of times. .

This BCT instruction subtracts "1" from the specified general-purpose register (loop counter) when executed.

If the reduction result is not "0", branch and execute the instruction at the branch destination (called the target instruction),
If the value of the subtraction result is "O", the next instruction in the loop is executed. for example.

A loop using BCT instructions is expressed as follows.

LOOP AR BCT R1, LOOP By the way, if an arithmetic instruction that requires a large number of cycles, such as a floating point arithmetic instruction, is placed before the 'BCT instruction, the preceding instruction is interlocked as shown in Figure 3. By doing that.

The instruction immediately before the BCT instruction is forced to wait in A cycle.

A situation is often seen in which the BCT instruction is forced to wait in the D cycle.

Note that 1. of the target commands in Figure 3. IT and IB indicate instruction fetch cycles. In other words, the BCT instruction is executed when the branch condition is satisfied after the wait state in the D cycle is released (loop counter value = O).
, the branch destination address is generated, and the target instruction is fetched and executed.

[Problem that the invention seeks to solve]

If there is an instruction that causes an interlock during a program loop, there is a problem in that the execution time of subsequent instructions is significantly delayed, resulting in a significant decrease in processing speed.

[Means for solving problems]

The present invention takes advantage of the fact that when a branch instruction follows an instruction that causes an interlock, it is possible to calculate and fetch the address of the target instruction at the branch destination while the branch instruction is waiting in an instruction decode cycle. ,
This is intended to recover from delays caused by interlocks.

FIG. 1 is an example flow of a pipeline instruction execution control sequence illustrating the principle of the present invention.

In the figure, D is instruction decoding, A is address generation, and T
indicates address conversion, B indicates buffer, E indicates execution, W indicates write, and I, IT, and IB indicate instruction fetch cycles. Also, BCT is a branch on counter instruction.

The instruction in ■ is an instruction that requires multiple cycles to perform the operation.
An interlock is applied in the E (execution) cycle. Therefore, the subsequent commands ■ through ■ are B, respectively.
It enters a waiting state in each cycle of T, A, and D.

The BCT' instruction (2) enters the wait state in the D cycle.

The BCT instruction calculates the operand address in the D cycle, holds the result in a register, calculates the branch destination address first, and executes the I, IT, and IB cycles to fetch the target instruction in ■. .

Thereafter, when the interlock is released, the target instruction can be executed immediately if the branch condition is satisfied.

[Effect]

According to the present invention, when an interlock occurs in a preceding instruction, in the optimal situation where the subsequent branch instruction waits in D cycles, the time lost due to fetching the target instruction at the branch destination is reduced by the branch instruction during the interlock period. Since it is absorbed by the instruction waiting time, execution of the target instruction after the interlock is released is accelerated.

〔Example〕

FIG. 2 is a diagram showing a pipeline flow according to one embodiment of the present invention.

In the figure, (a) is a branch on counter instruction B.
Pipeline flow of the instruction immediately before CT.

(bl shows the pipeline flow of the branch-on-counter instruction BCT, and (C) shows the pipeline flow of the target instruction.

Further, 21 is a pace register BR, 22 is an index register XR, 23 is a displacement register DR,
24 is an operand effective address calculator 0EAG, 25 is an operand effective address copy register 0EAR-CO
PY, 26 is operand local buffer memory 0P-
LBS, 26a is operand effective address register 0E
A.R.

27 is an operand write register OWR, 28 is an instruction address register IARA, 33 is an instruction address register IARB, 29 is an instruction effective address calculator IEAG,
30 is an instruction fetch local buffer memory IF-LB
S, 30a is an instruction effective address register IEAR, 31
is instruction word register IWRA, 3°2 is instruction word register I
It represents WRB.

In this embodiment, operands and instructions are handled by separate address calculation units (OEAG and IEAG) and buffer memories (OP-LBS and IF-LBS).
and have.

The first flow (a) is for an instruction that involves an operand fetch, and in cycle A, the operand address is set to 0.
Calculated by EAG24 and the result is 0EAR-COPY2
5 and interlocked in A cycle (A
W cycle).

After the interlock is released, the contents of 0EAR-COPY25 are copied to 0EA for operand access.
The data is read from 0P-LBS26 to 0WR27.

Next flow (bl is the flow of BCT instruction.

Previous flow (When al is interlocked in the AW cycle, 0EAG24 can be used, so in the first D cycle, put the base, index, and displacement values of the second operand into BR21, XR22, and DR23, respectively, and perform 2 cycles At step D, the branch destination address is calculated using 0EAG24.

And then the interlock is released.

The process proceeds to cycles A, T, B, E, and W in order.

In the embodiment shown in this figure, it is assumed that the decision as to whether to branch or not can be made in the D cycle.

The next flow (C) shows the target instruction flow.

If the address from the BCT instruction of flow (bl is 0EA
It is sent as the output of G24 and is put into the I EAR 30a to perform an instruction fetch from the I F-LBS 30 and at the same time for fetching subsequent instructions.

Set to IARB33.

The fetched instruction is IWRA3”1 or IWRB
32 and, in accordance with the branch-or-no-branch decision of the BCT instruction, IWRA 31. One of the IWRBs 32 is selected and an instruction is input to the pipeline.

The figure shows instructions in the normal execution order in IW'RA31, I
It is shown that the IWRB 32 on the target side is selected because the WRB 32 contains the target instruction of the branch destination and it has been decided to branch.

In this case, that is, in the case of branching, IARB33 is selected as the instruction address register, and subsequent instructions are fetched.

On the other hand, if there is no branch, IARA 28 is selected as the instruction address register, and subsequent instructions are fetched.

〔Effect of the invention〕

According to the present invention, since the calculation of the branch destination address of the branch instruction in the loop and the fetch of the target instruction are executed during the interlock period of the preceding instruction, the branch after the interlock is released.

In other words, since execution of the target instruction can be started immediately, the instruction execution time can be shortened, and the processing speed of the information processing device can be improved.

[Brief explanation of drawings]

Fig. 1 is a flow diagram of a pipeline control sequence according to the principle of the present invention, Fig. 2 is a flow diagram of a pipeline according to an embodiment of the present invention, and Fig. 3 is a flow diagram of a pipeline control sequence according to a conventional method. It is. In Figure 1. D=Instruction decode cycle A Near address generation cycle T Near address conversion cycle B: Buffer cycle E: Execution cycle W: Write cycle

Claims (1)

[Claims] In a pipeline-controlled information processing device, when the immediately preceding instruction is interlocked in an address calculation cycle, this operation result is stored in a register, the arithmetic unit used in address calculation is released, and the above interlocked If there is a branch instruction immediately after a branch instruction, the freed arithmetic unit calculates the branch destination address in the cycle of decoding the instruction, and fetches the target instruction.