JPH04276827A - pipeline processing equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a pipeline processing device that processes instructions using a pipeline, and more specifically, data obtained by executing an instruction is passed to another instruction at high speed for processing. The present invention relates to a pipeline processing device.

0002

2. Description of the Related Art Conventionally, in an information processing device, one instruction is divided into a plurality of stages, and when one instruction completes the execution of one stage, the next instruction executes that stage, thereby completing one stage. Performance is improved by making it possible to obtain the result of an instruction every time the instruction is executed. An information processing device that performs such processing is called a pipeline processing device.

FIG. 5 shows a block diagram of a conventional pipeline processing device. Here, one instruction is IF, DEC,
The process is divided into five stages: EX, MEM, and WB. The IF stage reads the instruction, the DEC stage decodes the instruction and reads the register, the EX stage performs the operation indicated by the instruction, and the MEM stage reads the memory if the instruction is a load or store instruction. is accessed, and data is stored in the WB stage.

In FIG. 5, 1a is a register file including a plurality of registers, which accesses two registers designated by an instruction to the DEC stage and outputs their contents, data a and data b. Reference numeral 2 denotes an EX stage arithmetic unit, which performs arithmetic operations specified by instructions on data a and data b in an EX stage. Reference numeral 4 denotes a MEM stage holding circuit, which temporarily holds the calculation results of the EX stage calculation device 2 in the MEM stage. 5 is a selection circuit;
If the instruction is an arithmetic instruction, it selects the output of the MEM stage holding circuit 4, that is, the arithmetic result, and if the instruction is a load instruction, it selects the load data 10 read from the memory device 9 and outputs it to the register file 1a. , the register file 1a writes the data output from the selection circuit 5 at the WB stage. If there is a data dependency between instructions, that is, if the next instruction uses the result of the previous operation instruction,
The operation result is applied to the input of the EX stage arithmetic unit 2 via the bypass path 20, and is operated on data a or data b read from the register file 1a. Further, when the previous instruction is a load instruction and the next arithmetic instruction uses data read from the memory device 9, the read data is given to the EX stage arithmetic device 2 via the bypass path 21, and the data a Alternatively, an operation is performed with data b.

FIG. 6 shows the operation of this pipeline processing device. The first instruction ADD consists of register r1 and register r
2 data is added and the result is stored in register r3. The second instruction SUB subtracts the data in register r4 from register r3 and stores the result in register r5. Register r3 read by second instruction SUB at DEC stage
is the data before being rewritten by the first instruction ADD, so the operation of the second instruction SUB is the same as that of the first instruction ADD.
have to wait for completion. Normally, in a high-performance pipeline processing device, the result of the operation is obtained at the end of the EX stage, so the result of the operation is immediately transferred to the next instruction SUB without waiting for the end of the WB stage of the first instruction ADD. By using it as input data, the second instruction SUB can be operated without having to wait. This way of passing data is called bypass.

However, the third instruction LD is
If data is read from the memory address indicated by and stored in register r2, and the fourth instruction SUB subtracts the data in register r3 from register r2 and stores the result in register r4, The data read by the LD instruction is obtained at the WB stage of the LD instruction, so
Even if the instruction is immediately bypassed to the arithmetic unit, execution of the next instruction SUB will be delayed for one cycle.

Next, as another conventional example, a pipeline processing device having two arithmetic units and executing two arithmetic instructions at the same time will be described. FIG. 7 shows its block diagram.

The register file 1b simultaneously reads out the contents data a, data b, data c, and data d of four registers necessary for two operations, and the data a and data b are processed by the EX stage operation device 2a. c and data d are calculated by the EX stage calculation device 2b, and the results are sent to the MEM stage holding circuits 4a and 4b, respectively.
, selection circuits 5a and 5b, and stored in the register file 1b.

If the instruction is a load instruction, the memory device 9
The load data 10 read out is selected by the selection circuit 5a or 5b and stored in the register file 1b. If there is data dependence between arithmetic instructions, the data is transferred via the bypass path 20a or 20b
If there is a data dependency between a load instruction and an arithmetic instruction, the data is provided to the EX stage arithmetic unit 2a or 2b via a bypass 21a or 21b.

FIG. 8 is a diagram showing the pipeline operation of the pipeline processing device shown in FIG. 7. 1st command and 2nd command
Since there are no data dependencies, these instructions are executed in parallel. However, since data dependence occurs between the third and fourth instructions, the fourth operation is delayed until the operation of the third instruction is completed.

[0011]

[Problems to be Solved by the Invention] As described above, in conventional pipeline processing devices, when there is a data dependency between two instructions, the execution of the next instruction is forced to wait, resulting in a decrease in performance. there were.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a pipeline processing device capable of reducing the waiting time for execution of instructions when there is data dependence between instructions. With the goal.

[0013]

[Means for Solving the Problems] A pipeline processing device of the present invention includes a first arithmetic device that performs an arithmetic operation in the Nth stage of pipeline processing consisting of a plurality of stages;
+ a second arithmetic device that performs an arithmetic operation at the first stage;
comprising a data dependence detection device and a control device, when the data dependence detection device detects that the data used for the operation instructed by the instruction is updated by the previous instruction and will not be in time for the Nth stage operation; The control device controls the calculation using the second calculation device, and when the data dependence detection device detects that the data is in time for the calculation of the Nth stage, the control device performs the calculation using the first calculation device. It is controlled so that

[0014]

[Operation] With the above-described configuration, the present invention allows operations when there is data dependence between instructions to be performed at a stage subsequent to the stage for operations when there is no dependence. is shortened.

[0015]

Embodiment (Embodiment 1) FIG. 1 shows a block diagram of a first embodiment of the present invention.

In this figure, 2 is an EX stage arithmetic unit, 3a is an MEM stage arithmetic unit, and 6 is a unit that holds instructions being executed. It is a data dependence detection device to investigate.

[0017] The instruction read at the IF stage is
The data is decoded at the stage, and data a and data b designated by the instruction are read from the register file 1a at the same DEC stage according to the decoding result. Also, the calculation indicated by the instruction is executed by the EX stage calculation unit 2.
executed on stage. The calculation result is M at the MEM stage.
The signal is temporarily held in the EM stage holding circuit 4, selected by the selection circuit 5, sent to the register file 1a, and stored in the register 1a specified by the instruction in the WB stage. 20
is a bypass path when the next instruction uses the operation result of the previous instruction.

When the previous instruction is a load instruction and the next instruction uses the data read from the memory 9 as input data for the operation, that is, the data read from the memory device 9 is used as the input data for the EX stage of the next operation. The data dependence detection device 6 detects that the data is not in time. When the data dependence detection device 6 detects a mismatch, it outputs a detection signal 7 to the control device 8, and the control device 8 outputs a control signal 9 to transfer the data 10 read by the load instruction to the MEM stage of the next instruction. Then, the data is passed to the MEM stage calculation device 3a for calculation.

FIG. 2 shows the pipeline operation of the pipeline processing device of FIG. 1. The third instruction LD is register r
The data at the memory address indicated by 1 is read out at the MEM stage and stored in register r2. Third instruction ADD
receives the data read out by the third instruction LD at the MEM stage, adds it to the contents of register r3 at the MEM stage, and stores it in register r4 at the WB stage. In this way, completion of the fourth instruction ADD is the same as in the case where there is no data dependence.

As described above, according to this embodiment, even if it is delayed to obtain data necessary for an operation due to data dependence between instructions, the delay in completing the instruction can be eliminated or reduced. It is possible to improve the performance of the pipeline processing device, and is extremely useful in practice.

(Embodiment 2) FIG. 3 shows a block diagram of a pipeline processing device according to a second embodiment of the present invention.

2a and 2b are EX stage arithmetic units, both of which perform arithmetic operations in the EX stage. 3b is ME
This is an M stage arithmetic device.

[0023] If there is no data dependency between instructions,
Two calculations are performed every cycle using the two EX stage calculation devices 2a and 2b.

When the data dependence detection device 6 detects that there is a data dependence relationship between instructions and the data will not arrive in time for the calculation of the EX stage, the data dependence detection device 6 outputs a detection signal 7 to the control device 8. Then, by the control device 8,
The previous instruction of the two instructions is executed by the EX stage arithmetic unit 2a.
The calculation is performed at the MEM stage, and the result is sent to the MEM stage calculation device 3b, where the calculation is performed at the MEM stage. At this time, the EX stage arithmetic unit 2b outputs data c and data d.
Among them, necessary data is sent as is to the MEM stage arithmetic unit 3b. The calculation results of the MEM stage calculation device 3b are selected by the selection circuit 5b and stored in the register file 1b.
is stored in

FIG. 4 shows the pipeline operation in this case. Register r3 used by the fourth instruction SUB is updated by the immediately preceding third instruction ADD. In this case, the third instruction ADD performs an operation in the EX stage, the fourth instruction SUB uses the result to perform an operation in the MEM stage, and stores the result in the register r5 in the WB stage. Even if there is data dependence between two operation instructions in this way, the WB stage is completed in the same time as when there is no dependence.

As described above, according to this embodiment, even if it is delayed to obtain data necessary for an operation due to data dependence between instructions, the delay in completing the instruction can be eliminated or reduced. This makes it possible to improve the performance of the pipeline processing device, which is extremely useful in practice.

[0027]

As described above, according to the present invention, even if it is delayed to obtain data necessary for an operation due to data dependence between instructions, the delay in completing an instruction can be eliminated. It is possible to increase the performance of the pipeline processing device, which is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a pipeline processing device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing the operation of the pipeline processing device shown in FIG. 1 in the same embodiment.

FIG. 3 is a block diagram of a pipeline processing device according to a second embodiment of the present invention.

FIG. 4 is a diagram showing the operation of the pipeline processing device shown in FIG. 3 in the same embodiment.

FIG. 5 is a block diagram of a conventional pipeline processing device.

FIG. 6 is a diagram showing the operation of the pipeline processing device shown in FIG. 5;

FIG. 7 is a block diagram of another conventional pipeline processing device.

8 is a diagram showing the operation of the pipeline processing device shown in FIG. 7. FIG.

[Explanation of symbols]

1a, 1b Register file 2, 2a, 2b EX stage calculation device 3a, 3b
MEM stage calculation device 4, 4a, 4b MEM stage holding circuit 5, 5a, 5b selection circuit 6 data dependence detection circuit 8 control circuit

Claims (1)

[Claims] Claim 1: A pipeline processing device that divides one instruction into a plurality of stages and performs pipeline processing, comprising:
A first arithmetic unit that performs an operation on the Nth stage of the plurality of stages, a second arithmetic unit that performs an operation on the N+1st stage of the plurality of stages, and data that detects a data dependency relationship between instructions. A dependence detection device and a control device are provided, and for data dependence between two instructions,
When the data dependence detection device detects that the data required by the later instruction among the two instructions will not arrive in time for the Nth stage, the control device causes the second arithmetic device to perform the operation of the later instruction. When the data dependence detection device detects that the data required by the later instruction of the two instructions is in time for the Nth stage, the control device controls the operation of the later instruction to A pipeline processing device characterized by performing control so as to be performed by a first arithmetic unit.