JPH04316127A - Information processor - Google Patents

Abstract

PURPOSE:To reduce the time required by an information processor for converting data of an intermediate from into data of a prescribed form so as to improve the performance of the processor by performing arithmetic operation by using the data of the intermediate form. CONSTITUTION:The information processor is provided with a register file 1 for storing data of an intermediate form or prescribed final form and the format indicating the form of the data, adder 3 which outputs results of arithmetic operation in an intermediate form, and data converter 7 which normalizes the data of the inetemediate form in accordance with the format and the adder 3 and a multiplier 4 performs arithmetic operation on the data read out of the file 2 by judging the form of the data from the format. The converter 7 inputs the data of a register read out of the file 1 and their format and, when the format/indicates that the data is of the intermediate form, converts the data into the data of the final form. When the format indicates that the data are of the final form, the converter 7 outputs the data as they are.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to an information processing device that has an arithmetic unit and a register file and performs operations specified by instructions, and in particular, an information processing device that performs high-speed processing using intermediate results of operations. It is related to the device.

0002

2. Description of the Related Art Conventionally, in information processing apparatuses, when an operation instructed by an instruction is complex, the operation is often performed using multiple cycles. For example, in the case of floating point arithmetic, the arithmetic is performed in one or more cycles, and the resulting intermediate format result is rounded and converted into a predetermined format (referred to as normalization) in the next cycle. An information processing device that performs such floating point operations will be described.

FIG. 5 shows a block diagram of a conventional information processing device. In FIG. 5, 20 is a register file,
It has multiple registers to store data. 21 is an adder that performs floating point addition and subtraction; 22 is a multiplier that performs floating point multiplication and division; 23 is a data dependency detector that detects data dependence between two instructions; 24 is adder 21 or multiplier 22 25 is a memory device that stores data.

[0004] The operation will be briefly explained. Data is loaded from the memory device 25 into the register file 20 using a load instruction. Using an arithmetic instruction, necessary data is read from the register file 20, and the adder 21 or multiplier 2
2, performs the operation specified by the operation instruction, selects the result in the selection circuit 24, and stores it in the register file 20. After repeating the operation and obtaining the desired result, use a store instruction to store data from the register file 20 in the memory device 2.
Write the result to 5. Normally, in order to perform these processes at high speed, the processing of one instruction is divided into multiple stages.
Pipeline processing is performed in which multiple instructions are processed in an overlapping manner.

In this conventional example, floating point addition/subtraction instructions and multiplication/division instructions are processed by a fetch stage F, a decode stage D, a first arithmetic stage E1, a second arithmetic stage E2, and a store stage S. The fetch stage F fetches the instruction, the decode stage D decodes the instruction, reads the data necessary for the operation from the register file, the first operation stage E1 performs the operation specified by the instruction, and the second operation stage E1 performs the operation specified by the instruction. In the calculation stage E2, the lower digits of the intermediate format result obtained in the first calculation stage are rounded and normalized to a predetermined format. In the store stage S, the normalized result is stored in the register specified by the instruction. In addition, if a data dependency occurs between two instructions by the data dependency detector 23, for example, if the next addition instruction uses the result of a multiplication instruction to perform an operation, the next cycle of the store stage S of the multiplication instruction Instead of performing an addition instruction operation from
By bypassing the adder,
The first calculation stage E1 of the addition instruction can be started simultaneously with the store stage S of the multiplication instruction.

FIG. 6 shows a pipeline operation in a conventional information processing device. FADDr1, r2, and r3 add the data in register r1 and register r2 by an addition instruction, and store the result in register r3. In Figure 6, the first instruction and the second
This shows a case where there is no data dependence between the instructions of , and there is data dependence between the second instruction and the third instruction. In the third command,
Since the data necessary for the calculation cannot be obtained immediately, the operation is forced to wait for one cycle.

Conventional information processing devices always perform conversion into a predetermined format, such as rounding and normalization of lower digits that are not directly necessary for calculations.

[0008]

[Problems to be Solved by the Invention] As described above, in conventional information processing devices, although it is possible to perform calculations on data in an intermediate format before conversion to a predetermined format, There is a problem in that an extra cycle is required for the conversion, resulting in an increase in processing time, that is, a decrease in performance.

The present invention has been made in view of these problems, and an object of the present invention is to provide an information processing device that can perform calculations using intermediate format data and shorten the calculation processing time. .

0010

[Means for Solving the Problems] An information processing device according to claim 1 of the present invention includes a computing unit that performs an operation specified by an instruction and outputs the result in an intermediate format, and an intermediate format or a predetermined final format. a register file having a plurality of registers storing data and a format indicating whether the data is in an intermediate format or a predetermined final format, and according to the format,
a data converter for normalizing data in an intermediate format;
The arithmetic unit receives the register data and format read from the register file as input, and performs an operation on the data according to the data format indicated by the format, and the data converter receives the register data and format read from the register file. Taking the data and format of the register as input, converting the data to the final format if the format indicates that the data is in the intermediate format, and converting the data to the final format if the format indicates that the data is in the final format. is output as is.

Further, the information processing device according to claim 2 of the present invention includes one or more arithmetic units that perform an operation specified by an instruction and output a result in an intermediate format and a result in a final format; a register file having a plurality of registers for storing data, and a data dependence detector for detecting data dependence between the first and second instructions, and the data dependence detector detects the result of the first instruction. When it is detected that the second instruction is used, the arithmetic unit that performs the calculation of the second instruction performs the calculation using the intermediate format result of the calculation unit that performed the calculation of the first instruction. It is.

0012

[Operation] With the above-described configuration, the present invention can perform calculations using data in an intermediate format, so that the time required to convert from the intermediate format to the final format can be shortened.

[0013]

【Example】

(Example 1) FIG. 1 shows Example 1 of the information processing apparatus of the present invention.
The block diagram is shown below.

In this figure, 1 is a register file, which consists of a plurality of registers 2. Each register 2 consists of a data section 2a and a format section 2b.
The intermediate format or normalized data is stored in the format section 2b, and the format indicating whether the data in the data section 2a is in the intermediate format or normalized format is stored in the format section 2b. In this embodiment, if the format is 0, it is normalized data, and if the format is 1, it is intermediate format data. 3 is an adder which performs addition and subtraction of floating point numbers and outputs the result in an intermediate format. 4 is a multiplier which performs floating point multiplication and division and outputs the result in an intermediate format. A selection circuit 5 selects either the result of the adder 3 or the result of the multiplier 4 and outputs it to the register file 1 according to an instruction. A memory device 25 stores data in a normalized format as in the conventional example. A data converter 7 normalizes the intermediate format data according to the format of the register 2 and outputs the normalized data to the memory device 25.

The operation of the information processing apparatus of this embodiment will be briefly explained below. The normalized data stored in the memory device 25 is loaded into the register file 1 using a load instruction.
is stored in the data section 2b of the register specified by the instruction. Since this data has been normalized, 0 is stored in the format section 2a.

Next, addition is performed on this data using an addition instruction. The register specified by the addition instruction is read out, and the data is given to the adder 3 along with the format. The adder 3 performs calculations assuming that the data has been normalized by the format. The calculation result is output as an intermediate format, selected by the selection circuit 5, and given to the register file 1. The operation result is stored in intermediate format in the register specified by the addition instruction. At this time, 1 is stored in the corresponding format section 2a.

Next, when an addition is performed on this data using an addition instruction, the calculation is performed assuming that the data is in an intermediate format due to the format. After repeating the necessary operations, the operation results are stored in the memory device 2 using a store instruction.
Store in 5. At this time, the data in the register specified by the store instruction is read out along with the format and sent to the data converter 7. When the data converter 7 finds that the data is normalized by the format, it outputs the data as is to the memory device 25, and when it finds that the data is in an intermediate format, it normalizes it and outputs it to the memory device 25. . Since data conversion can be performed in parallel with memory address calculation, the execution time of a store instruction does not become longer than in the past. When a programmer refers to register data, he writes the register data to the memory device using a store instruction, so there is no problem with the program even if there are two types of data in the register file. In a system in which register file data is directly transferred to another processing device without going through a memory device, a data converter may be placed between the register file and the other processing device.

FIG. 2 shows the pipeline operation of the embodiment of FIG. There are four operation instructions: fetch stage F, decode stage D, execution stage E, and store stage S.
Processed in two stages.

In this way, in this embodiment, the lower digits are not rounded or normalized at the execution stage of the floating-point operation, so the instruction is completed one cycle earlier than in the conventional example, and the result is stored in the register file. be able to. Furthermore, according to the present embodiment, since the intermediate format data is data before rounding of lower digits, it is possible to reduce the decrease in data accuracy due to rounding.

(Embodiment 2) FIG. 3 shows a block diagram of an information processing apparatus according to Embodiment 2 of the present invention.

A register file 20 stores normalized data as in the conventional example. Reference numeral 10 denotes an adder that performs addition and subtraction of floating point numbers, and is composed of an arithmetic unit 11 that performs operations and outputs results in an intermediate format, and a conversion unit 12 that performs rounding and normalization of the results in the intermediate format. A multiplier 13 performs floating point multiplication and division, and like the adder 10, it is composed of an arithmetic unit 14 and a conversion unit 15. Normally, an operation instruction reads normalized data from the register file 20 and sends it to the adder 10 or multiplier 13, as in the conventional example.
and selects the normalized result in the selection circuit 24,
Store it in the register file 20.

[0022] If there is a data dependency between two instructions,
For example, when the first instruction is an addition instruction and the second instruction performs multiplication using the operation result of the first instruction, if the data dependence detector 23 detects the data dependence shown above, the multiplication The unit 13 uses the intermediate-format calculation result outputted by the calculation unit 11 of the adder 10 as one input data, and performs calculations using the normalized data read from the register file 20 as other input data. In this way adder 10
The next calculation can be performed without waiting for the calculation result to be normalized by the conversion unit 12. However, if the result of the first instruction is stored in the register file 20 when the second instruction is executed, the stored result of the first instruction can also be used.

FIG. 4 shows the pipeline operation of the information processing apparatus in the embodiment of FIG. The pipeline is composed of five stages: F, D, E1, E2, and S, as in the conventional example. A normal operation instruction is finished in the same cycle as the conventional example, but if there is a data dependency between two instructions, the E1 stage of the next instruction can be started at the same time as the E2 stage of the first instruction. Compared to the conventional example, the subsequent instructions are completed one cycle earlier. Further, since the intermediate format data is data before rounding of lower digits, it is possible to reduce the decrease in data accuracy due to rounding.

Note that in this embodiment, the multiplier 13 is the adder 1
In the above example, the calculation result in the intermediate format output by the calculation unit 11 of 0 is used as one input data, and the normalized data read from the register file 20 is used as other input data to perform the calculation. The present invention can also be applied to an information processing device that has one processor and uses the intermediate result of the processor as an input to the processor itself.

In addition, in the first and second embodiments, two of the adders and multipliers are
Although one arithmetic unit is shown, the effects of each embodiment can be obtained even in the case of three or more arithmetic units. It is also possible to have the configurations of the first and second embodiments in arithmetic units such as format converters and shifters other than adders and multipliers. Furthermore, Examples 1 and 2
Although the case where floating-point operations are performed has been described above, the present invention can be applied to information processing devices such as devices that perform integer operations that can be performed in an intermediate format.

[0026]

As described above, according to the present invention, there is no need to convert the calculation result in an intermediate format into a predetermined final format, and therefore the calculation processing time is shortened. Furthermore, the number of converters from intermediate format to final format, which were included in a plurality of arithmetic units, can be reduced to one, and the amount of circuitry can be reduced. Thus, the present invention is extremely useful in practice.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an information processing device according to an embodiment of the present invention.

FIG. 2 is an operational diagram of the information processing device shown in FIG. 1;

FIG. 3 is a block diagram of an information processing device according to another embodiment of the present invention.

FIG. 4 is an operational diagram of the information processing device shown in FIG. 3;

FIG. 5 is a block diagram of a conventional information processing device.

FIG. 6 is an operational diagram of the information processing device shown in FIG. 5;

[Explanation of symbols]

1,20 Register file 2 Register 3,10 Adder 4,13 Multiplier 5, 24 Selection circuit 7 Data converter 11, 14 Arithmetic unit 12, 15 Conversion section 23 Data dependent detector 25 Memory device

Claims (2)

[Claims] Claim 1: A computing unit that performs an operation specified by an instruction and outputs the result in an intermediate format, data in an intermediate format or a predetermined final format, and a format indicating whether the data is an intermediate format or a predetermined final format. a register file having a plurality of registers for storing the data, and a data converter that normalizes data in an intermediate format according to the format, and the arithmetic unit receives the register data and format read from the register file as input. , the data converter performs an operation on the data according to the data format indicated by the format, and the data converter inputs the register data and format read from the register file, and determines that the data is in an intermediate format according to the format. An information processing apparatus characterized in that when the format indicates that the data is in the final format, the data is converted into a final format, and when the format indicates that the data is in the final format, the data is output as is. 2. A register file comprising one or more arithmetic units that perform operations specified by instructions and output results in intermediate format and final format, and a plurality of registers that store data in final format. , a data dependence detector for detecting data dependence between the first and second instructions, and the data dependence detector detects the result of the first instruction in the second instruction.
When it is detected that the instruction is used, the arithmetic unit that performs the operation of the second instruction performs the operation using the intermediate format result of the arithmetic unit that performed the operation of the first instruction. information processing equipment.