JP2925842B2 - Pipeline processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline processing apparatus for dividing each instruction into a plurality of stages and performing pipeline processing. The present invention relates to a pipeline processing device for passing and processing.

[0002]

2. Description of the Related Art Conventionally, in an information processing apparatus, each instruction is divided into a plurality of stages, and when the execution of a stage of a certain instruction is completed, the stage of the next instruction corresponding to the stage is executed. It has been attempted to obtain a result of one instruction every execution time of one stage, thereby improving the processing speed. Such an information processing device that executes each instruction by dividing it into a plurality of stages is called a pipeline processing device.

In such a conventional pipeline processing apparatus, each instruction includes an instruction read stage (IF stage), an instruction decode stage (DEC stage), an execution stage (EX stage), a memory stage (MEM stage), and a write stage. (WB stage) and executed. In the IF stage, the instruction is read, the DEC stage decodes the instruction and reads the register, the EX stage performs the operation specified by the instruction, and the MEM stage accesses the memory when the instruction is a load instruction or a store instruction. In the WB stage, data is stored in the register file.

Hereinafter, a specific example of a conventional pipeline processing apparatus will be described with reference to the drawings.

FIG. 5 is a block diagram showing a first conventional pipeline processing apparatus. In FIG. 1, a first conventional pipeline processing device includes first and second arithmetic devices 60a and 60b, and the first arithmetic device 60a processes a first instruction to be executed first by pipeline processing. At the same time, the second arithmetic unit 60b performs a pipeline process on a second instruction to be executed next to the first instruction. The first arithmetic unit 60a includes a first EX stage arithmetic unit 53a and a first EX stage arithmetic unit 53a.
MEM stage holding circuit 54a and first selection circuit 55
a and a first WB stage holding circuit 56a. Similarly, the second arithmetic unit 60b includes the second EX stage arithmetic unit 53b and the second MEM stage holding circuit 5
4b, a second selection circuit 55b, and a second WB stage holding circuit 56b.

The first conventional pipeline processing device includes a register file 51 shared by the first and second arithmetic units 60a and 60b. The register file 51 includes a large number of registers 52a, 52b, 52c, and 52. 52d
…have. Here, the registers 52a and 52b
Are used for the operation of the first instruction in the first EX stage operation device 53a, and the data stored in the registers 52c and 52d are the second EX stage operation device 53a.
It is assumed that it is used for the operation of the second instruction in the stage operation device 53b. First EX stage arithmetic unit 53
The calculation result at a is stored in the register file 51 via the first MEM stage holding circuit 54a, the first selecting circuit 55a, and the first WB stage holding circuit 56a. Similarly, the operation result in the second EX stage operation device 53b is based on the second MEM stage holding circuit 54b, the second selection circuit 55b, and the second WB stage holding circuit 5
6b and stored in the register file 51.

In the first conventional pipeline processing apparatus, the first instruction to be executed first is a load instruction LD, the second instruction to be executed next is an operation instruction, and When there is a data dependency between the instruction and the second instruction, that is, the load data loaded from the memory device 58 by the load instruction LD as the first instruction is used in the operation instruction as the second instruction. In this case, the load data read from the memory device 58 by the load instruction LD, which is the first instruction, is stored in the bypass path 59a or 59b.
Through the first EX stage operation device 53a or the second EX stage operation device 53a
Is input to the EX stage arithmetic unit 53b.

FIG. 6 is a diagram showing the operation of the pipeline processing apparatus according to the first conventional example. In the figure, the first instruction to be executed first among the two instructions is a load instruction LD, and the load instruction LD is composed of the data stored in the register r1 and the data stored in the register r2. The instruction is to set the sum as an address of the memory device 58, read data stored at the address from the memory device 58, and store the load data read from the memory device 58 in the register r3. The second instruction to be executed next to the first instruction is an addition instruction ADD, and the addition instruction AD
D is an instruction to add the data stored in the register r3 and the data stored in the register r4 and store the result of the operation in the register r5. However, the data read from the register r3 in the DEC stage of the addition instruction ADD as the second instruction is data before being rewritten by the execution of the load instruction LD as the first instruction, and thus the addition instruction ADD as the second instruction. Cannot be used for the calculation of Load instruction L, which is the first instruction
The load data obtained by the execution of D is the W of the first instruction.
The data is stored in the register r3 in the B stage. Therefore, the load data read from the memory device 58 in the MEM stage of the first instruction before being stored in the register r3 is transferred to the second EX stage operation device 53b. However, the EX stage of the second instruction that executes the operation of the addition instruction ADD, which is the second instruction, is delayed by two cycles. Here, the stage indicated by STALL is a stage waiting for execution of an operation.

FIG. 7 is a block diagram showing a pipeline processing apparatus according to a second conventional example. As shown in the figure, the second conventional pipeline processing device is a first EX stage arithmetic device 53a and a first MEM of the first arithmetic device 60a in the first conventional pipeline processing device. Instead of the stage holding circuit 54a, the first arithmetic unit 60
c is provided with a multiplication device 53c. The second conventional pipeline processing device includes first and second arithmetic units 6.
0c and 60b, the first arithmetic unit 60c pipelines the first instruction to be executed first,
The second arithmetic unit 60b pipelines a second instruction to be executed next to the first instruction.

Here, it is assumed that the data stored in the registers 52a and 52b of the register file 51 is used for the operation of the first instruction in the multiplier 53c. The calculation result in the multiplication device 53c is stored in the register file 51 via the first selection circuit 55a and the first WB stage holding circuit 56a.

In the second conventional pipeline processing apparatus, the first instruction to be executed first is a multiplication instruction MUL, and the second instruction to be executed next is an operation instruction,
When there is a data dependency between the first instruction and the second instruction, that is, when the operation result of the multiplication instruction MUL as the first instruction is used in the operation instruction as the second instruction,
The operation result of the multiplication instruction MUL, which is the first instruction, is input to the multiplication device 53c or the EX stage operation device 53b via the bypass path 59a or 59b.

FIG. 8 is a diagram showing the operation of a second conventional pipeline processing apparatus. In the figure, of the two instructions, the first instruction to be executed first is a multiplication instruction MUL, and the multiplication instruction MUL is composed of the data stored in the register r1 and the data stored in the register r2. This instruction stores the product in the register r3, and requires two cycles of time to execute the multiplication operation. The second instruction to be executed next to the first instruction is an addition instruction ADD. The addition instruction ADD adds the data stored in the register r3 and the data stored in the register r4, This is an instruction to store the operation result in the register r5. However, D of the second instruction, the add instruction ADD,
The data read from the register r3 in the EC stage is data before being rewritten by the execution of the multiplication instruction MUL as the first instruction, and thus cannot be used for the operation of the addition instruction ADD as the second instruction. The operation result of the multiplication instruction MUL, which is the first instruction, is stored in the register r3 in the WB stage of the first instruction. Therefore, in the EX2 stage of the first instruction before storing the result in the register r3, the result of the multiplication is stored in the EX stage operation device 53b.
Is forwarded to However, the second instruction, the addition instruction AD
The EX stage of the second instruction for executing the operation of D is 2
The cycle will be delayed. Here, the stages EX1 and EX2 in the first instruction are execution stages of the multiplication instruction MUL in two cycles, and the stage indicated by STALL is a stage waiting for execution of an operation.

[0013]

As shown in the above conventional example, in a conventional pipeline processing apparatus, a first instruction and a second instruction to be executed next to the first instruction are executed. If there is a data dependency between them, there is a problem that execution of the second instruction is waited and the processing speed is reduced.

The present invention has been made in view of such a problem, and has been made in the case where there is a data dependency between a first instruction and a second instruction to be executed next to the first instruction. Also,
It is an object of the present invention to provide a pipeline processing device capable of reducing the execution waiting time of the second instruction.

[0015]

In order to achieve the above object, the invention according to claim 1 comprises a first instruction and a second instruction which is an ALU operation instruction to be executed next to the first instruction. Between the second instruction and the second instruction.
Is executed in a stage after the execution stage of the instruction.

Specifically, the first aspect of the present invention provides a first instruction and an ALU to be executed next to the first instruction.
The present invention is directed to a pipeline processing apparatus that divides a second instruction, which is an operation instruction, into a plurality of stages and performs pipeline processing, and performs a processing of the second instruction at a stage subsequent to an execution stage of the second instruction. Stage operation means for performing an operation, data dependence detection means for detecting a data dependence between the first instruction and the second instruction,
Control means for controlling the stage calculation means to execute the operation of the second instruction when the data dependency detection means detects the data dependency.

The invention according to claim 2 is specifically described in claim 1
In the configuration, the execution time of the first instruction is equal to the execution time of the second instruction or the execution time of the second instruction is
This is to add a configuration that is an instruction longer than the execution time of the instruction.

The invention according to claim 3 is specifically described in claim 2
The first instruction is added to the configuration of (1) above, which is a load instruction.

The invention according to claim 4 specifically relates to claim 3
In the above configuration, the stage operation means is a write stage operation means for executing the operation of the second instruction in a write stage after the execution stage of the second instruction.

In order to achieve the above object, the invention of claim 5 detects a data dependency between a first instruction which is simultaneously pipelined and a second instruction which is an ALU operation instruction. Thus, the operation of the second instruction is executed in a stage after the execution stage of the second instruction.

[0021] Specifically, the solution taken by the invention of claim 5 is a first instruction and an ALU to be executed next to the first instruction.
A first arithmetic unit for pipeline-processing the first instruction, wherein the first instruction is for a pipeline processing device that divides a second instruction, which is an arithmetic instruction, into a plurality of stages and performs pipeline processing at the same time; A second arithmetic unit for performing pipeline processing on the second instruction; and a second arithmetic unit provided in the second arithmetic unit and executing the operation of the second instruction in a stage subsequent to the execution stage of the second instruction. Stage operation means, data dependency detection means for detecting a data dependency between the first instruction and the second instruction, and second data processing when the data dependency detection means detects the data dependency. And control means for controlling the above-described operation of the instruction to be executed by the stage operation means.

The invention according to claim 6 specifically relates to claim 5
In the configuration, the execution time of the first instruction is equal to the execution time of the second instruction or the execution time of the second instruction is
This is to add a configuration that is an instruction longer than the execution time of the instruction.

The invention according to claim 7 is specifically described in claim 6
The first instruction is added to the configuration of (1) above, which is a load instruction.

The invention according to claim 8 is specifically described in claim 7
In the above configuration, the stage operation means is a write stage operation means for executing the operation of the second instruction in a write stage after the execution stage of the second instruction.

[0025]

According to the structure of the first aspect of the present invention, the first instruction and the second instruction which is an ALU operation instruction to be executed next to the first instruction are provided .
If there is a data dependency with the instruction of the second instruction, the data dependency detecting means detects the data dependency, and the control of the control means causes the stage calculation means to execute the data dependency in a stage after the execution stage of the second instruction. The operation of the second instruction can be performed. Thus, the operation of the second instruction is
Even if the acquisition of data required for the operation of the second instruction is delayed due to the data dependency, the second instruction can be executed in a stage after the execution stage of the second instruction.

According to the second aspect of the present invention, for example, when the first instruction is a multiplication instruction whose execution time is longer than the execution time of the operation of the second instruction, the first instruction The data dependency between the second instruction and the second instruction is such that the operation result of the multiplication instruction as the first instruction is used for the operation in the second instruction. When the data dependence is detected by the data dependence detection unit, the operation result of the first instruction is also input to the stage operation unit, and the stage operation unit performs the operation at a stage after the execution stage of the second instruction. The operation of the second instruction can be performed.

According to the third aspect of the present invention, since the first instruction is a load instruction, the data dependency between the first instruction and the second instruction is loaded by executing the first instruction. This load data is used for the operation in the second instruction. When the data dependence is detected by the data dependence detection means, the load data to be loaded in the first instruction is also input to the stage operation means, and the stage operation means is provided after the execution stage of the second instruction. In the stage, the operation of the second instruction can be executed.

According to the structure of the fourth aspect of the present invention, the operation of the second instruction using the load data loaded by the execution of the first instruction is executed in a write stage after the execution stage of the second instruction. can do.

According to the fifth aspect of the present invention, the first
When the first instruction and the second instruction are simultaneously pipelined, the first instruction and the ALU to be executed next to the first instruction
If there is a data dependency with the second instruction, which is an operation instruction , the data dependency detection means detects the data dependency, and the stage calculation means of the second processing device controls the stage calculation means under the control of the control means. The operation of the second instruction can be executed at a stage after the execution stage of the second instruction.

According to the configuration of the sixth aspect of the present invention, when the first instruction and the second instruction are simultaneously pipelined, for example, the execution time of the first instruction may be longer than that of the second instruction. If the multiplication instruction is longer than the execution time of the operation,
The data dependency between the first instruction and the second instruction is such that the operation result of the multiplication instruction, which is the first instruction, is used for the operation in the second instruction. When the data dependence is detected by the data dependence detection unit, the operation result of the first instruction is also input to the stage operation unit of the second arithmetic unit, and the stage operation unit executes the execution instruction of the second instruction. The operation of the second instruction can be executed at a later stage.

According to the seventh aspect of the present invention, when the first instruction and the second instruction are simultaneously pipelined, the first instruction is a load instruction. The data dependency between the instruction and the instruction is such that load data loaded into the first arithmetic unit by execution of the first instruction is used for an operation in the second instruction. When the data dependence is detected by the data dependence detection means, the load data to be loaded into the first arithmetic unit in the first instruction is also input to the stage arithmetic means of the second arithmetic unit, and the stage arithmetic operation is performed. The means can execute the operation of the second instruction at a stage after the execution stage of the second instruction.

According to the eighth aspect of the present invention, when the first instruction and the second instruction are simultaneously pipelined, the load data loaded into the first arithmetic unit by executing the first instruction is used. The operation of the second instruction can be executed in a write stage after the execution stage of the second instruction.

[0033]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a pipeline processing apparatus according to a first embodiment of the present invention. In the figure, the pipeline processing device of the first embodiment includes first and second arithmetic devices 20a and 20b, and the first arithmetic device 20a processes the first instruction while simultaneously executing the second instruction. The arithmetic unit 20b performs pipeline processing of the second instruction. The first arithmetic unit 20a includes a first EX stage arithmetic unit 3a, a first MEM stage holding circuit 4a, a first selecting circuit 5a, and a first WB stage holding circuit 6a.
And a third selection circuit 5c.
The second arithmetic device 20b includes a second EX stage arithmetic device 3b, a second MEM stage holding circuit 4b, a second selecting circuit 5b, and a second WB stage holding circuit 6b.
Further, it has a fourth selection circuit 5d, a fifth selection circuit 5e, and a WB stage operation device 10 as a write stage operation means.

Further, the pipeline processing device of the first embodiment includes a register file 1 shared by the first and second arithmetic units 20a and 20b, and the register file 1 has a large number of registers 2a, 2b, 2c, 2d ... Here, the data stored in the registers 2a and 2b are stored in the first EX stage operation device 3a in the first EX stage operation device 3a.
And the data stored in the registers 2c and 2d are used for the operation of the second instruction in the second EX stage operation device 3b.

Further, the pipeline processing apparatus of the first embodiment includes a data dependence detection device 11 as data dependence detection means and a control device 13 as control means.
The data dependence detection device 11 determines that the first instruction is a load instruction L
D and the second instruction is an operation instruction such as an addition instruction ADD, there is a data dependency between the first instruction and the second instruction, that is, the first instruction is a load instruction. When detecting that the load data loaded from the memory device 8 is used by the instruction LD in the operation of the second instruction, a detection signal is sent to the control device 13. When the control device 13 receives the detection signal from the data dependency detection device 11, the first and second WB stage holding circuits 6b, 6b, the first, second,
Third, fourth and fifth selection circuits 5a, 5b, 5c, 5
Output control signals to d, 5e, etc.

FIG. 2 is a diagram showing the operation of the pipeline processing device according to the first embodiment of the present invention. In the figure, 2
The first instruction to be executed first among the three instructions is a load instruction LD, and the load instruction LD stores the sum of the data stored in the register r1 and the data stored in the register r2 in the memory device 8. , The data stored at the address is read from the memory device 8 and the load data read from the memory device 8 is stored in the register r3. The second instruction to be executed next to the first instruction is an addition instruction ADD, and the addition instruction AD
D is an instruction to add the data stored in the register r3 and the data stored in the register r4, and store the operation result in the register r5. In the pipeline processing device of the first embodiment, the load data read from the memory device 8 by the load instruction LD, which is the first instruction, is stored in the register r3 by the execution of the load instruction LD, and is executed by the second instruction. It is also used for the operation of a certain addition instruction ADD.

ALU operation such as addition instruction ADD
In general, in the first half of the system clock cycle,
Executes the operation and transfers the operation result in the second half
ing.

As described above, the pipeline processing device of the first embodiment simultaneously executes the first instruction and the second instruction. In the IF stage of the first instruction, the first instruction
Of the first instruction reads out the first instruction. Then, in the DEC stage of the first instruction, the first arithmetic unit 20a decodes that the first instruction is the load instruction LD and , Register 2 of register file 1
The data stored in a and 2b are input to the first EX stage processing unit 3a. Next, the first instruction E
In the X stage, the first EX stage operation device 3a of the first operation device 20a adds the data read from the register 2a of the register file 1 and the data read from the register 2b of the register file 1. . Next, in the MEM stage of the first instruction, the first arithmetic unit 20a specifies the operation result of the first instruction in the EX stage as an address of the memory device 8, and stores the data stored in the address. The data is read from the memory device 8, and the load data read from the memory device 8 is input to the first WB stage holding circuit 6a and the WB stage operation device 10. Next, in the WB stage of the first instruction, the load data read from the memory device 8 is stored in the register file 1 through the first WB stage holding circuit 6a and the third selection circuit 5c.

Similarly, in the IF stage of the second instruction, the second arithmetic unit 20b reads the second instruction, and in the DEC stage of the second instruction, the second arithmetic unit 20b reads the second instruction. The second instruction is decoded to be the addition instruction ADD. Further, the first and second instructions are also input to the data dependency detection device 11, and the data dependency detection device 11
Is whether or not there is a data dependency between the first instruction and the second instruction, that is, the load data read from the memory device 8 by executing the load instruction LD as the first instruction is the second instruction. It is checked whether or not it is used in the operation of the addition instruction ADD, which is the instruction of FIG. The data dependence detection device 11 outputs a detection signal to the control device 13 when detecting that there is a data dependence between the load instruction LD as the first instruction and the addition instruction ADD as the second instruction. As described above, when there is a data dependency between the first instruction and the second instruction, in the DEC stage of the second instruction, only the data stored in the register 2d of the register file 1 is stored in the second instruction. , And the data stored in the register 2c of the register file 1 is not read.

Then, in the EX stage of the second instruction, no addition is performed, and in the MEM stage of the next second instruction, the data input to the second EX stage operation device 3b is replaced by the fifth selection circuit 5e. Are input to the WB stage arithmetic unit 10 through As mentioned above, the first instruction M
Load data read from the memory device 8 in the EM stage is input to the WB stage operation device 10.
Therefore, in the WB stage of the second instruction, the WB stage arithmetic unit 10 performs the addition, whereby the operation result of the addition instruction ADD, which is the second instruction, is obtained. Similarly,
In the WB stage of the second instruction, the operation result of the addition instruction ADD, which is the second instruction, is stored in the register file 1.

As described above, in the pipeline processing device of the first embodiment, when the first instruction is a load instruction LD and the second instruction is an addition instruction ADD, the data dependence detection device 11 Detects that the load data loaded from the memory device 8 by the first instruction is used for the operation of the second instruction, the load data loaded from the memory device 8 by the first instruction The second WB stage arithmetic device 10 is also input to the WB stage arithmetic device 10 of the second arithmetic device 20b, and the WB stage arithmetic device 10 performs addition of the second instruction in the WB stage after the EX stage in the second instruction. In this instruction, there is no need to provide a stage waiting for execution.

FIG. 3 is a block diagram showing a pipeline processing apparatus according to a second embodiment of the present invention. As shown in the figure, the pipeline processing device of the second embodiment is different from the pipeline processing device of the first embodiment in that the first EX stage arithmetic device 3a and the first M
Instead of the EM stage holding circuit 4a, a first arithmetic unit 20c is provided with a multiplier 3c. The pipeline processing device of the second embodiment includes first and second arithmetic devices 20c and 20b, and the first arithmetic device 20c
At the same time as the second instruction is pipelined, the second arithmetic unit 20b pipelines the second instruction. The first arithmetic unit 20c includes a multiplication unit 3c and a first selection circuit 5a.
And a first WB stage holding circuit 6a.
It has a third selection circuit 5c.

Here, it is assumed that the data stored in the registers 2a and 2b of the register file 1 is used for the operation of the first instruction in the multiplier 3c.

In the data dependence detection device 11, the first instruction is a multiplication instruction MUL and the second instruction is an addition instruction ADD.
And the like, there is a data dependency between the first instruction and the second instruction, that is, the operation result of the multiplication instruction MUL as the first instruction is the operation of the second instruction. When the control signal is detected, the control unit 13 sends a detection signal to the control device 13. When the control device 13 receives the detection signal from the data dependency detection device 11, the first and second WB stage holding circuits 6b and 6b, the first, second, third, fourth and fifth selection circuits 5a and 5b, Control signals are output to 5c, 5d, 5e, etc.

FIG. 4 is a diagram showing the operation of the pipeline processing device according to the second embodiment of the present invention. In the figure, 2
The first instruction to be executed first among the two instructions is a multiplication instruction M
The multiplication instruction MUL is an instruction to store the product of the data stored in the register r1 and the data stored in the register r2 in the register r3. The multiplication instruction MUL takes two cycles to execute the multiplication operation. Needs time. The second instruction to be executed next to the first instruction is an ADD instruction. The ADD instruction adds the data stored in the register r3 and the data stored in the register r4, and calculates the operation result. Is stored in the register r5. In the pipeline processing device of the second embodiment, the operation result of the multiplication instruction MUL as the first instruction is stored in the register r
3 and a second instruction, an add instruction ADD
Is also used for the calculation of

The pipeline processing apparatus of the second embodiment is
As described above, the first instruction and the second instruction are executed simultaneously. In the IF stage of the first instruction, the first arithmetic unit 20c reads the first instruction, and then, in the DEC stage of the first instruction, the first arithmetic unit 20c reads the first instruction. It decodes that the instruction is a multiplication instruction MUL, and inputs data stored in the registers 2a and 2b of the register file 1 to the multiplication device 3c. Next, in the EX1 and EX2 stages of the first instruction, the multiplier 3c of the first arithmetic unit 20c uses the time of two cycles to read the data read from the register 2a of the register file 1 and the register file 1 is multiplied by the data read from the register 2b. Further, in the EX2 stage of the first instruction, the operation result of the multiplication is input to the first WB stage holding circuit 6a and the WB stage operation device 10. Next, the first instruction W
In the B stage, the result of the multiplication operation is stored in the register file 1 via the first WB stage holding circuit 6a and the third selection circuit 5c.

Similarly, in the IF stage of the second instruction, the second arithmetic unit 20b reads the second instruction, and in the DEC stage of the second instruction, the second arithmetic unit 20b reads the second instruction. The second instruction is decoded to be the addition instruction ADD. Further, the first and second instructions are also input to the data dependency detection device 11, and the data dependency detection device 11
Is whether there is a data dependency between the first instruction and the second instruction, that is, the operation result obtained by executing the multiplication instruction MUL which is the first instruction is the second instruction It is checked whether or not it is used in the operation of the addition instruction ADD.
The data dependence detection device 11 is a multiplication instruction MU which is the first instruction.
When detecting that there is a data dependency between L and the addition instruction ADD as the second instruction, a detection signal is output to the control device 13. When there is a data dependency between the first instruction and the second instruction in this way, in the DEC stage of the second instruction, only the data stored in the register 2d of the register file 1 is stored in the EX stage. Arithmetic unit 3b
And the data stored in the register 2c of the register file 1 is not read.

Then, in the EX stage of the second instruction, no addition is performed, and in the MEM stage of the next second instruction, the data input to the EX stage arithmetic unit 3b passes through the fifth selection circuit 5e to the WB. Stage operation device 1
Input to 0. As described above, in the EX2 stage of the first instruction, the operation result of the multiplication instruction MUL, which is the first instruction, is input to the WB stage operation device 10. Therefore, in the WB stage of the second instruction, the WB stage arithmetic unit 10 performs the addition, whereby the operation result of the addition instruction ADD, which is the second instruction, is obtained. Similarly, the second
In the WB stage of the instruction, the operation result of the addition instruction ADD, which is the second instruction, is stored in the register file 1.

As described above, in the pipeline processing device of the second embodiment, when the first instruction is a multiplication instruction MUL and the second instruction is an addition instruction ADD, the data dependence detection device 11 But the operation result of the first instruction is the second
When the data dependency that is used for the operation of the first instruction is detected, the operation result of the first instruction is
Of the second instruction, the WB stage arithmetic device 10 executes addition of the second instruction in the WB stage after the EX stage in the second instruction. There is no need to provide a waiting stage.

The pipeline processing apparatus according to the first and second embodiments uses the two pipelines to simultaneously execute a first instruction and a second instruction to be executed next to the first instruction. Although the processing is performed, the same effect can be obtained even when the first instruction and the second instruction are pipeline processed by one pipeline.

In the first and second embodiments,
Describes the case where the second instruction is an addition instruction ADD.
As described above, other ALU operation instructions such as SUB and AN
Perform in one cycle such as D, OR, SHIFT, CMP
The same effect can be obtained if the instruction can be executed.
You.

[0053]

As described above, according to the pipeline processing apparatus of the first aspect of the present invention, the first instruction and the second instruction which is the ALU operation instruction to be executed next to the first instruction By detecting a data dependency between
The operation of the second instruction is executed in a stage after the execution stage of the second instruction. Thereby, the operation of the second instruction is executed in a stage after the execution stage of the second instruction even if acquisition of data necessary for the operation of the second instruction is delayed due to the data dependency. Therefore, the time during which the execution of the second instruction is waited is reduced, so that the processing speed of the pipeline processing device can be improved.

According to the pipeline processing apparatus of the second aspect, for example, when the first instruction is a multiplication instruction whose execution time is longer than the execution time of the second instruction, When the data dependency between the first instruction and the second instruction is detected, the operation result of the first instruction is also input to the stage operation means, and the stage operation means The operation of the second instruction can be executed in a stage subsequent to the execution stage. Therefore, the operation of the second instruction can be executed together with the first instruction without providing the second instruction with an execution waiting stage.

According to the pipeline processing device of the third aspect, since the first instruction is a load instruction, the first instruction is a load instruction.
When the data dependency between the first instruction and the second instruction is detected, the load data to be loaded in the first instruction is also input to the stage operation means, and the stage operation means The operation of the second instruction can be executed in a stage subsequent to the execution stage. Therefore, the operation of the second instruction can be executed together with the first instruction without providing the second instruction with an execution waiting stage.

According to the pipeline processing device of the fourth aspect, the operation of the second instruction can be executed in the write stage after the execution stage of the second instruction. Therefore, the operation of the second instruction can be executed without providing the second instruction with a stage waiting for execution.

Therefore, the processing speed of the pipeline processing device can be significantly improved.

[0058] According to the pipeline processing apparatus according to the invention of claim 5, when simultaneously pipelining <br/> second instruction and a first instruction and A LU operation instruction, the first
By detecting the data dependency between the second instruction and the second instruction, the operation of the second instruction is executed in a stage after the execution stage of the second instruction. Thereby, even if the acquisition of data required for the operation of the second instruction is delayed due to the data dependency, the operation of the second instruction is performed in the second stage after the execution stage of the second instruction. Can be executed. Therefore, the time during which the execution of the second instruction is waited is reduced, and the processing speed of the pipeline processing device can be improved.

According to the pipeline processing device of the present invention, when the first instruction and the second instruction are simultaneously pipeline-processed, for example, the execution time of the first instruction is If the multiplication instruction is longer than the execution time of the operation of the second instruction, the data dependency between the first instruction and the second instruction is detected, and the operation result of the first instruction is detected. Is also input to the stage operation means of the second operation device, and the stage operation means can execute the operation of the second instruction in a stage subsequent to the execution stage of the second instruction. Therefore, the operation of the second instruction can be executed simultaneously with the first instruction without providing the second instruction with an execution waiting stage.

According to the pipeline processing apparatus of the present invention, when the first instruction and the second instruction are simultaneously pipelined, the first instruction is a load instruction, so that the first instruction is a load instruction. When the data dependency between the instruction and the second instruction is detected, the load data to be loaded into the first arithmetic device in the first instruction is also input to the stage arithmetic means of the second arithmetic device. The stage operation means can execute the operation of the second instruction in a stage after the execution stage of the second instruction. Therefore, the operation of the second instruction can be executed simultaneously with the first instruction without providing the second instruction with an execution waiting stage.

According to the pipeline processing apparatus of the present invention, when the first instruction and the second instruction are simultaneously pipelined, the operation of the second instruction is executed by executing the second instruction. It can be performed in a write stage after the stage. For this reason, the operation of the second instruction is performed in the first instruction without providing an execution waiting stage in the second instruction.
Instructions can be executed simultaneously.

Accordingly, the processing speed of the pipeline processing device can be significantly improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a pipeline processing device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an operation of the pipeline processing device according to the first embodiment.

FIG. 3 is a block diagram showing a pipeline processing device according to a second embodiment of the present invention.

FIG. 4 is a diagram illustrating an operation of the pipeline processing device according to the second embodiment.

FIG. 5 is a block diagram showing a pipeline processing device according to a first conventional example.

FIG. 6 is a diagram showing an operation of the pipeline processing device according to the first conventional example.

FIG. 7 is a block diagram showing a pipeline processing device according to a second conventional example.

FIG. 8 is a diagram showing an operation of the pipeline processing device according to the second conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Register file 2a, 2b, 2c, 2d Register 3a, 3b EX stage arithmetic unit 3c Multiplier 4a, 4b MEM stage holding circuit 5a, 5b, 5c, 5d, 5e Selection circuit 6a, 6b WB stage holding circuit 8 Memory device 10 WB stage arithmetic unit (write stage arithmetic unit) 11 Data dependence detection unit (data dependence detection unit) 13 Control unit (control unit) 20a First arithmetic unit 20b Second arithmetic unit

Claims (8)

(57) [Claims] 1. A pipeline processing apparatus for performing a pipeline process by dividing a first instruction and a second instruction which is an ALU operation instruction to be executed next to the first instruction into a plurality of stages. A stage operation means for executing the operation of the second instruction at a stage subsequent to the execution stage of the second instruction; and a data dependence relationship between the first instruction and the second instruction. Data dependency detection means for detecting, and control means for controlling the stage calculation means to execute the operation of the second instruction when the data dependency detection means detects the data dependency. A pipeline processing device characterized by the above-mentioned. 2. The method according to claim 1, wherein the execution time of the first instruction is equal to or longer than the execution time of the second instruction. The pipeline processing apparatus according to claim 1, wherein 3. The pipeline processing device according to claim 2, wherein said first instruction is a load instruction. 4. The stage operation means according to claim 3, wherein said stage operation means is a write stage operation means for executing an operation of said second instruction in a write stage subsequent to an execution stage of said second instruction. The pipeline processing device as described in the above. 5. A pipeline processing apparatus for dividing a first instruction and a second instruction, which is an ALU operation instruction to be executed next to the first instruction, into a plurality of stages and performing pipeline processing at the same time. A first arithmetic unit for pipeline-processing the first instruction; a second arithmetic unit for pipeline-processing the second instruction; and a second arithmetic unit provided in the second arithmetic unit. Stage operation means for executing the operation of the second instruction in a stage subsequent to the execution stage of the first instruction, and data dependence detection for detecting the data dependence between the first instruction and the second instruction Means, and control means for controlling the stage operation means to execute the operation of the second instruction when the data dependence detection means detects the data dependence. Spline processing apparatus. 6. The method according to claim 1, wherein the execution time of the first instruction is equal to or longer than the execution time of the second instruction. The pipeline processing device according to claim 5, wherein 7. The pipeline processing device according to claim 6, wherein said first instruction is a load instruction. 8. The stage operation means according to claim 7, wherein said stage operation means is a write stage operation means for executing an operation of said second instruction in a write stage subsequent to an execution stage of said second instruction. The pipeline processing apparatus according to the above.