JPH05181642A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To provide an arithmetic unit for simplifying a circuit configuration of a detecting part of the maximum value and the minimum value of vector data with a mask. CONSTITUTION:This arithmetic unit calculates the maximum value or the minimum value in prescribed data, based on prescribed data, and mask data to the prescribed data. This unit is constituted by providing a selecting means 20 for selecting and outputting one of fixed value data set by which of the maximum value or the minimum value is calculated, and the prescribed data, based on the mask data, a deciding means 21 for outputting its output value as it is when an output value from the selecting means 20 is a first element, and deciding which of its output value and an output value outputted previously is larger or smaller, based on which of the maximum value or the minimum value is calculated, when the output value from the selecting means 20 is other element than a first element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit, and more specifically, for example, a super computer, a super EWS
The present invention relates to an arithmetic device suitable for use in fields such as (Engineering Work Station) and for performing vector processing at high speed. In recent years, in scientific calculation, for example, a DO loop in the FORTRAN language, that is, DO 10 I = 0,100 C (I) = A (I) * B (I) F (I) = D (I) + E ( I) In many cases, a large number of operations are concentrated in a specific loop process, such as repeated operations represented by 10 CONTINUE.

A process of repeating a certain operation on a plurality of data is called a vector process, and a large amount of scientific calculation is executed. For example, in an arithmetic unit such as a vector processor, the vector process can be executed at high speed. Required.

[0003]

2. Description of the Related Art A conventional processor of this type is, for example, a vector processor as shown in FIG. In the figure, 1 is a vector processor, 2 is an instruction control unit, 3 is an instruction register, 4 is a multiplier, 5 is an adder, 6 is a vector register, 7 is a mask register, 8 is an input / output control unit, and 9 is A CPU (Central Processing Unit) 10 is a main memory.

An outline of the operation of vector processing in the above configuration will be described. First, the CPU 9 transfers a predetermined instruction sequence and operation data on the main memory 10 to the vector processor 1, the instruction sequence is stored in the instruction register 3, and the operation data is stored in the vector register 6. Next, when the CPU 9 activates the vector processor 1, the instruction control unit 2 in the vector processor 1 fetches instructions one by one from the instruction register 3 and outputs the control signals necessary for execution.

In each unit, data input / output and calculation are executed according to these control signals. For example, when executing multiplication, the calculation data is read from the vector register 6 and transferred to the multiplier 4 and then the multiplier 4 The multiplication is performed on the calculated data. The multiplication result by the multiplier 4 is transferred to the vector register 6, and the multiplication result is stored in the vector register 6. The above-mentioned control signal also includes read / write timings necessary for these operations.

Finally, if the instruction fetched from the instruction register 3 is an end instruction, the operation is interrupted and the vector processor 1 enters a standby state. Let us now consider masked arithmetic. The operation with mask means that mask data is set for each element of the vector data and the operation is not performed on the masked data.

That is, A (I) is the operand and B (I)
Is the number of operations, and M (I) is mask data, as shown in FIG. 6, when the value of A (I) × B (I) is stored in C (I), the value of M (I) is referred to. However, when "M (I) = 1", the masked operation is such that the result is not written in C (I). Normally, when performing operations such as multiplication and addition, the operation data, the operated data, and the mask data are transferred from the vector register 6 and the mask register 7 to the operation unit including the multiplier 4 and the adder 5 for each processing cycle, and the operation is performed. Pipeline processing is performed in which the result calculated by the container is transferred to the vector register 6 every processing cycle.

Here, the data handled in the vector processing is an index, that is, the related data distinguished by the value of I in the above-mentioned formula, and therefore, the maximum value or the minimum value among them is calculated. Can be considered. Even in such processing, as in the case of the vector processing described above, the data for each processing cycle is transferred to the arithmetic unit that compares large and small, and this arithmetic unit receives two data at the same time and compares them. The size is judged.

FIG. 7 shows the concept of masked arithmetic in calculating the maximum value or the minimum value. However, when all the data are masked, the minimum value is output as the result when the maximum value is detected, and the maximum value is output as the result when the minimum value is detected. FIG. 8 is a block diagram showing an arithmetic circuit for obtaining the maximum value or the minimum value of vector data.

This arithmetic circuit includes input latches 11, 12,
13, a fixed value generator 14, a magnitude comparator 15, a first selector 16, a second selector 17, a temporary latch 18, and an output latch 19. In the figure, D'is the output signal of the input latch 11, M'is the output signal of the input latch 12, C2 'is the output signal of the input latch 13, K is the output signal of the fixed value generator 14, and S is the magnitude comparison. Output signal of the device 15,
Q is the output signal of the first selector 16 and R is the second selector 1
7, the output signal of T is the output signal of the temporary latch 18, and the output signal of O is the output signal of the output latch 19.

The input latch 11 is a latch circuit for temporarily holding the vector data D to be operated, and data for one element is transferred from the vector register 6 as vector data D in one cycle. The input latch 12 is a latch circuit that temporarily holds the mask information M for the vector data D. The mask information M is transferred from the mask register 7 in synchronization with the vector data D, and the mask is valid when the value is "1". Suppose

The input latch 13 is a latch circuit for temporarily holding a signal C2 indicating that the transferred vector data D is the first element, and the signal C2 is "1" in synchronization with the vector data D of the first element. Is transferred from the instruction control unit 2. The fixed value generator 14 receives the input vector data D
Is a circuit for generating the maximum value or the minimum value of the data used in the arithmetic circuit based on the signal C1 indicating which of the maximum value and the minimum value is to be detected.

FIG. 9A is a block diagram showing the configuration of the main part of the fixed value generator 14, in which the data used in this operation is 4
The operation is described as an integer in the two's complement representation of bits. That is, as shown in FIG. 9B, C1 = "0"
If the maximum value is detected, the selector selects "1".
000 ”(minimum value) is selected, while when C1 =“ 1 ”, the selector selects“ 01 ”as the minimum value detection.
11 "(maximum value) is selected and output as the signal K.

As shown in FIG. 10A, the magnitude comparator 15 is a circuit for comparing the magnitudes of two inputs A and B and outputting the comparison result. Its operation is shown in FIG. 10B. It will be explained based on. When C2 ′ = “1”, that is, when the input data is the first element, the output of the signal S is S = “0” regardless of the value of the signal C1.

On the other hand, when C2 '= "0", that is, when the input data is the second and subsequent elements, the maximum value detection (C1 =
In the case of “0”), when A−B ≧ 0, S = “0”, A
-When B <0, S = “1”, and the minimum value is detected (C1 =
In the case of “1”), when A−B ≧ 0, S = “1”, A
When -B <0, S = “0”. First selector 16
11A, as shown in FIG. 11A, the output signal S of the magnitude comparator 15, the output signal M ′ of the input latch 12 (mask signal for the current data), and the output signal T of the temporary latch 18 (previous data). The output signal D ′ of the input latch 11, the output signal O of the output latch 19, and the output signal K of the fixed value generator 14 are selected based on the mask signal).

That is, as shown in FIG. 11B, when only the current input is masked, the maximum value or the minimum value selected before that is selected, and only the previous data is masked. Current input is selected. Further, when both the current and previous data are selected, a fixed value is selected, and when neither data is masked, the signal D ′ or the signal O is selected based on the output signal S of the magnitude comparator 15. To be done.

As shown in FIG. 12A, the second selector 17 is a circuit for selecting either the signal M ′ or the signal T based on the output signal S of the magnitude comparator 15, and FIG.
As shown in (b), when S = “0”, R = M ′, S
If = "1", R = T is selected. Temporary latch 18
Is a latch circuit for temporarily holding the output signal R from the second selector 17 for use as a mask signal for previous data.

The output latch 19 is a latch circuit for temporarily holding the output signal Q from the first selector 16 for use as previous data, and its output signal is the signal O.
Is fed back to the magnitude comparator 15 and the first selector 16.

[0019]

However, in such a conventional arithmetic unit, even the mask information for the previously input data is latched, so that the mask information is retained. There is a problem that two latch circuits are required. Further, since the first selector 16 and the second selector 17 are operated based on the two types of mask information, there is a problem that the configuration of the selector becomes complicated.

[Purpose] Therefore, an object of the present invention is to provide an arithmetic unit which simplifies the circuit configuration of the detection part of the maximum value and the minimum value of vector data with a mask.

[0021]

In order to achieve the above-mentioned object, an arithmetic unit according to the present invention has the principle diagram shown in FIG.
A calculation device for calculating a maximum value or a minimum value in the predetermined data based on predetermined data and mask data for the predetermined data, and which of the maximum value and the minimum value is calculated based on the mask data. Selecting means 20 for selecting and outputting any one of the fixed value data set by the above and the predetermined data, and when the output value from the selecting means 20 is the first element, the output value is If the output value from the selecting means 20 is an element other than the first element, the output value and the previously output value are output based on whether the maximum value or the minimum value is calculated. And a determination means 21 for determining which is larger or smaller.

[0022]

According to the present invention, since the mask data is applied only to the currently input predetermined data, the number of latch circuits for holding the mask information is reduced.
It is possible to prevent the configuration of the selector or the like that operates based on the mask information from becoming complicated.

That is, the circuit configuration of the portion for detecting the maximum value and the minimum value of the vector data with mask is simplified.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing an embodiment of an arithmetic unit according to the present invention,
It is a block diagram which shows schematic structure of the arithmetic unit of a present Example. First, the configuration will be described.

In FIG. 2, the same numbers as the numbers given to the principle diagram shown in FIG. 1 and the conventional example shown in FIGS. 8 to 10 indicate the same parts. The arithmetic unit according to the present embodiment includes the input latches 11 and 12, the fixed value generator 14, the selecting means 20 including the third selector 22, the selecting means 20, and the determining means 21, the input latch 13, the magnitude comparator 15, and the fourth comparator. It is composed of a selector 23 and a judging means 21 composed of an output latch 19.

In the figure, P is the output signal of the third selector 22, and Q'is the output signal of the fourth selector 23. Third
As shown in FIG. 3A, the selector 22 outputs the output signal D ′ of the input latch 11 and the fixed value generator 14 based on the output signal M ′ of the input latch 12 (mask signal for the current data). One of the output signals K is selected, and more specifically, as shown in FIG. 3B, M ′ =
“0”, that is, when the current input is not masked, the current input D ′ is directly selected and output as the output signal P, while when it is masked (M ′ = “1”) , The output K of the fixed value generator 14 is selected and output as the output signal P.

As shown in FIG. 4A, the fourth selector 23 outputs the output signal P of the third selector 22 (corresponding to the current data) and the output latch based on the output signal S of the magnitude comparator 15. This is a circuit for selecting any one of the 19 output signals O (corresponding to the previous data). As shown in FIG. 4B, when S = “0”, Q = P and S = “1”. In case of Q
= O is selected.

Next, the operation will be described. First, the instruction control unit 2
The vector data is read out from the vector register 6 and the mask data is read out from the mask register 7 according to the instruction, and transferred to the arithmetic circuit in this embodiment as signals D and M, respectively, and latched by the input latches 11 and 12, respectively. ..

Then, the input data and the fixed value are selected by the third selector 22 based on the value of the output signal M'from the input latch 12. Here, when the maximum value is detected, if the vector data that is the input data is masked, the value is compared as the minimum value, so it is possible to ignore even if the input value is large.

Next, based on the output signal S of the magnitude comparator 15, the fourth selector 23 selects either the input data (fixed value if masked) or the previous maximum or minimum value. By doing so, the maximum value or the minimum value of all the vector data input so far is selected. The output Q ′ of the fourth selector 23 is latched by the output latch 19 and is output as the output O by the magnitude comparator 1
5, and transferred to the outside.

As described above, in this embodiment, an extra latch circuit for holding mask information can be omitted, and the number of elements in the entire circuit can be reduced. Therefore, the circuit scale of the arithmetic circuit for calculating the maximum value or the minimum value of the masked vector data can be reduced. In the above embodiment, the data used in the calculation is described as the data represented by the 4-bit 2's complement, but the data is not limited to this, and the actual data may be, for example, floating point data. It goes without saying that the bit length is also arbitrary.

[0032]

According to the present invention, by applying the mask data only to the predetermined data that is currently input, it is possible to reduce the latch circuit for holding the mask information, and operate based on this mask information. It is possible to prevent the configuration of the selectors, etc., to be complicated. Therefore, it is possible to simplify the circuit configuration of the detection unit of the maximum value and the minimum value of the masked vector data.

[Brief description of drawings]

FIG. 1 is a principle diagram of an arithmetic unit according to the present invention.

FIG. 2 is a block diagram showing a schematic configuration of an arithmetic unit of this embodiment.

FIG. 3 is a diagram for explaining the configuration and operation of a third selector.

FIG. 4 is a diagram for explaining the configuration and operation of a fourth selector.

FIG. 5 is a schematic diagram of a vector processor.

FIG. 6 is a diagram for explaining an operation with a mask.

FIG. 7 is a diagram for explaining a masked operation for detecting a maximum value and a minimum value.

FIG. 8 is a block diagram showing a schematic configuration of a conventional arithmetic device.

FIG. 9 is a diagram for explaining the configuration and operation of a fixed value generator.

FIG. 10 is a diagram for explaining the configuration and operation of a size comparator.

FIG. 11 is a diagram for explaining the configuration and operation of the first selector.

FIG. 12 is a diagram for explaining the configuration and operation of a second selector.

[Explanation of symbols]

 1 vector processor 2 instruction control unit 3 instruction register 4 multiplier 5 adder 6 vector register 7 mask register 8 input / output control unit 9 CPU 10 main memory 11 input latch 12 input latch 13 input latch 14 fixed value generator 15 large / small comparator 16 First Selector 17 Second Selector 18 Temporary Latch 19 Output Latch 20 Selection Means 21 Judging Means 22 Third Selector 23 Fourth Selector

Claims (1)

[Claims] 1. An arithmetic unit for calculating a maximum value or a minimum value in predetermined data based on predetermined data and mask data for the predetermined data, wherein the maximum value or the minimum value is calculated based on the mask data. Fixed value data set depending on which is calculated,
Selecting means for selecting and outputting any one of the predetermined data, and if the output value from the selecting means is the first element, the output value is output as it is, and the output value from the selecting means Is an element other than the first element, the determination means for determining which of the output value and the output value output previously is larger or smaller, based on which of the maximum value and the minimum value is calculated. An arithmetic unit comprising: