JP2542120B2 - Information processing device - Google Patents

Description

The present invention relates to an information processing device using an electronic computer.

[Conventional technology]

FIG. 5 shows a block diagram of a conventional information processing apparatus. In FIG. 5, 101 is an instruction decoding unit that decodes instructions, 102 is a register interference detection unit that detects register interference between consecutive instructions, and 103 is composed of a plurality of registers and holds 32-bit 0 data. A register unit having a zero value register, 104 is an integer operation unit, 105 is a data transfer control unit that controls data transfer with a data cache (not shown), and 501 is a data address generation unit that generates a data address. Is. 110 is an instruction bus for transferring instructions, 111 is a 32-bit immediate data bus for transferring immediate data, 112 is a 32-bit first internal data bus, 113 is a 32-bit second internal data bus, and 114 is a 32-bit Third internal data bus, 115 is a 32-bit data address bus, 116 is a 32-bit store data bus for transferring to the data cache, 117 is a 32-bit load data bus transferred from the data cache, 118 is an instruction decoding unit 1
This is a control signal sent from 01.

FIG. 6 is a block diagram showing the internal configuration of the data address generation unit 501 of the conventional information processing apparatus in FIG. In FIG. 6, 601 and 203 are 32-bit multiplexers, 202 is a 32-bit adder, and 204 is a 32-bit feedback latch. 111 is a 32-bit immediate data bus, 112 is a 32-bit first internal data bus, and 113 is a 32-bit second internal data bus, which respectively correspond to the buses of the same name in FIG. 210 is an output of the multiplexer 601 and is a 32-bit data bus input to the adder 202, and 211 is an output of the adder 202, which is an addition result output bus. 115 is a data address bus, which is the data address bus in FIG.
Corresponds to 115. Reference numeral 212 is a hold data bus for outputting the data of the data address bus 115 one clock before, which is held in the feedback latch 204. 213 and 214
Are a data select signal and an address hold signal for instructing the select conditions of the multiplexers 301 and 203, respectively, both of which are part of the control signal 118 in FIG.

The operation of the conventional information processing apparatus configured as described above will be described below.

This conventional information processing device has a four-stage pipeline configuration, performs an operation only between the data of two 32-bit registers, performs the inter-register operation of storing the result in the register again, and exchanges the data with the memory. Is an information processing device having a load / store architecture that is performed only between a memory and a register.

FIG. 7 is a timing chart showing the operation of the arithmetic instruction of the conventional information processing apparatus. In FIG. 7, C1, C2, etc. represent processing cycles of a conventional information processing apparatus, and A, B represent arithmetic instructions to be processed.

First, the operation of the operation instruction of the conventional information processing apparatus will be described with reference to FIGS. 5 and 7.

C1 cycle: The operation instruction A is fetched and sent to the instruction bus 110.

C2 cycle: The instruction decoding unit 101 converts the operation instruction A sent to the instruction bus 110.
Deciphers. The instruction decoding unit 101 sends the control information according to the decoded instruction as the control signal 118, but the processing is divided into the following two types of processing depending on the type of the operation instruction A.

(1) When the operation instruction A is an operation between data in two 32-bit registers, the register unit 103 transfers the data in the two 32-bit registers designated by the control signal 118 to the first internal data bus.
112, to the second internal data bus 113.

(2) When the operation instruction A is an instruction to set the immediate data designated in the instruction to a specific register: The instruction decoding unit 101 sends the immediate data to the immediate data bus 111. Further, the register unit 103 sends the data of the 32-bit zero value register designated by the control signal 118 to the first internal data bus 112.

Also, the operation instruction B is fetched and sent to the instruction bus 110.

C3 cycle: The integer operation unit 104 executes the operation designated by the control signal 118 sent from the instruction decoding unit 101 in the C2 cycle. At this time, the data used for this calculation differs between the two types described in the C2 cycle.

(1) When the operation instruction A is an operation between the data of two 32-bit registers The integer operation unit 104 has the first register unit 103 in the C2 cycle.
The data sent to the internal data bus 112 and the second internal data bus 113 is input and the operation is executed. After the operation is completed, the operation result is sent to the 32-bit third internal data bus 114.

(2) When the operation instruction A is an instruction to set the immediate data specified in the instruction to a specific register: The integer operation unit 104 inputs the immediate data sent to the immediate data bus 111 by the instruction decoding unit 101 in the C2 cycle. Then, the register unit 103 executes addition with 0 sent to the first internal data bus 112. After the operation is completed, the operation result is sent to the 32-bit third internal data bus 114.

Since the processing for the arithmetic instruction B is the same as that for the arithmetic instruction A in the C2 cycle, detailed description will be omitted.

C4 cycle: In the register unit 103, the integer arithmetic unit 104 is the third in the C3 cycle.
The data sent to the internal data bus 114 is stored in the register designated by the control signal 118 in the C2 cycle.

Since the processing for the arithmetic instruction B is the same as that for the arithmetic instruction A in the C3 cycle, detailed description will be omitted.

Next, the operation of an instruction that requires memory address calculation in the conventional information processing apparatus will be described. As an example, a store instruction for storing the data of the register in the memory is given.

8 and 9 are timing charts showing the operation of a store instruction for storing data in the memory of the conventional information processing apparatus. Here, FIG. 8 shows the case where the data of one 32-bit register and the immediate data designated by the store instruction are summed to calculate the memory address for storing the data (hereinafter referred to as 1-clock store). , FIG. 9 shows the case where the sum of the data of two 32-bit registers is taken to calculate the memory address for storing the data (hereinafter referred to as 2-clock store).

First, the operation of the 1-clock store of the conventional information processing apparatus will be described with reference to FIGS. 5, 6 and 8. For simplicity of explanation, the data of the register used for the address calculation at the time of 1-clock store (r1) and the immediate data (imm
A), register data to be stored is (r2).

C1 cycle: The store instruction A is fetched and sent to the instruction bus 110.

C2 cycle: Store instruction A sent to instruction bus 110 receives instruction decode unit 1
01 deciphers. The instruction decoding unit 101 sends the control information to the control signal 1
18 and send immediate data (immA) as immediate data bus
Send to 111. Also, the register 103 sends the 32-bit register data (r1) used for the memory address calculation designated by the control signal 118 to the second internal data bus 113, and the 32-bit register data (r1) to be stored in the memory ( r2) is sent to the first internal data bus 112.

Next, the operation of the data address generation unit 501 will be described. The multiplexer 601 outputs the immediate data (immA) of the immediate data bus 111 to the data bus 210 according to the information of the data select signal 213 sent as the control signal 118. The adder 202 outputs immediate data (imm output to the 32-bit data bus 210 and the second internal data bus 113, respectively).
A) and data (r1) are added, and the result is added. Result output bus 2
Output to 11. The multiplexer 203 uses the information of the address hold signal 214 sent as the control signal 118,
The data of the addition result output bus 211 is output to the data address bus 115. Thus, the address (immA) + (r1) of the data to be stored on the data address bus 115 is transmitted.

C3 cycle: Address sent to data address bus 115 (imm
A) + (r1) is used to access the data cache.
Assume that the data cache hits here. Further, the data transfer control unit 105 latches the data (r2) sent to the first internal data bus 112.

C4 cycle: The data transfer control unit 105 sends the data (r2) latched in the C3 cycle to the store data bus 116 and stores it in the data cache.

Next, the operation of the 2-clock store of the conventional information processing apparatus will be described with reference to FIGS. 5, 6 and 9.
For simplicity of explanation, it is assumed that the register data used for the address calculation at the time of storing two clocks is (r1) and (r2), and the register data to be stored is (r3).

C1 cycle: The store instruction A is fetched and sent to the instruction bus 110.

C2 cycle: Store instruction A sent to instruction bus 110 receives instruction decode unit 1
01 decodes and sends control information as control signal 118.
The register unit 103 uses two 32-bit register data (r
1) and (r2) are sent to the first internal data bus 112 and the second internal data bus 113.

Next, the operation of the data address generation unit 501 will be described. The multiplexer 601 outputs the data of the first internal data bus 112 to the data bus 210 according to the information of the data select signal 213 sent as the control signal 118. The adder 202 outputs the data (r1) and (r2) output to the 32-bit data bus 210 and the second internal data bus 113, respectively.
Are added and the result is output to the addition result output bus 211. The multiplexer 203 outputs the data of the addition result output bus 211 to the data address bus 115 according to the information of the address hold signal 214 sent as the control signal 118. Thus, the address (r1) + (r2) of the data to be stored on the data address bus 115 is transmitted.

C3 cycle: Since the store instruction A decoded in the C2 cycle is the 2 clock store, the instruction decoding unit 101 outputs the control information indicating the operation of the 2nd cycle of the 2 clock store as the control signal.
Send as 118.

The register unit 103 sends the data (r3) of the 32-bit register to be stored in the memory designated by the control signal 118 to the second internal data bus 112. The data address generation unit 501
Address hold signal 214 sent as control signal 118
The data (r1) + (r2) of the hold data bus 212 is kept in the data address bus 115 in order to continuously send the result of addition in the C3 cycle to the data address bus 115 according to the information of
The multiplexer 203 is controlled to output to. Further, the instruction decoding unit 101 does not decode the next instruction (nop) because the instruction decoded in the C2 cycle is a 2-clock store instruction.

C4 cycle: Address sent to data address bus 115 (r1)
Use + (r2) to access the data cache. Now assume that the data cache is hit. Also,
The data transfer control unit 105 has a first internal data bus 112.
Latch the data (r3) sent to.

C5 cycle: The data transfer control unit 105 sends the data (r3) latched in the C4 cycle to the store data bus 116,
Store in data cache.

As described above, the 2-clock store instruction requires data in three registers, and therefore requires five cycles for execution. Therefore, there is a blank in the pipeline for one cycle.

Next, the operation instruction for setting the immediate data of the conventional information processing apparatus to a specific register and the instruction requiring the memory address calculation are continuous, and the register used for the memory address calculation of the subsequent instruction is the preceding operation. When the instruction matches the register that should set immediate data,
The operation will be described.

A store instruction is given as an example of an instruction that requires memory address calculation.

10 and 11 show an arithmetic instruction A and a store instruction B for setting immediate data of a conventional information processing device in a specific register.
6 is a timing chart showing an operation in the case where and are consecutive and the register used for calculating the memory address of the subsequent store instruction b matches the register in which the immediate data is to be set in the preceding arithmetic instruction A (register interference). FIG. 10 shows the case where the store instruction B is one clock store, and FIG. 11 shows the case where the store instruction B is two clock store.

Using FIG. 5, FIG. 6 and FIG. 10, the operation instruction A for setting the immediate data of the conventional information processing apparatus to a specific register and the 1-clock store instruction B are consecutive, and the memory address of the store instruction B is set. The operation when register interference occurs between the register used for calculation and the register for which immediate data is to be set by the preceding arithmetic instruction A will be described. For simplicity of explanation, the register in which interference occurs is r1, the operation instruction A
(ImmA), the immediate data used for the address calculation of the one-clock store instruction B is (immB), and the data of the register to be stored is (r2).

C1 cycle: (1) Processing for operation instruction A The operation instruction A is fetched and sent to the instruction bus 110.

C2 cycle: (1) Processing for operation instruction A The operation instruction A sent to the instruction bus 110 is transferred to the instruction decoding unit 101.
Deciphers. The instruction decoding unit 101 transmits the control information to the control signal 118.
And send immediate data (immA) as immediate data bus 11
Send to 1. Further, the register unit 103 sends the data of the 32-bit zero value register designated by the control signal 118 to the first internal data bus 112.

(2) Processing for store instruction B The store instruction B is fetched and sent to the instruction bus 110.

C3 cycle: (1) Processing for operation instruction A The integer operation unit 104 inputs the immediate data (immA) sent by the instruction decoding unit 101 to the immediate data bus 111 in the C2 cycle, and the register unit 103 outputs the first internal data bus. The addition with 0 sent to 112 is executed. After the operation is completed, the operation result is sent to the 32-bit third internal data bus 114.

(2) Processing for store instruction B The instruction decoding unit 1 stores the store instruction B sent to the instruction bus 110.
01 deciphers. The instruction decoding unit 101 sends the control information to the control signal 1
18 and send immediate data (immB) as immediate data bus
Send to 111. Further, the register unit 103 controls the control signal 118.
The 32-bit register data (r1) used for calculating the memory address specified in step 1 is sent to the second internal data bus 113, and the 32-bit register data (r2) to be stored in the memory is sent to the first internal data bus 112. Send to. However,
The data (r1) of the second internal data bus 113 is invalid because the operation instruction A has not been completed. In parallel with the processing of the instruction decoding unit 101, the register interference detection unit 102 and the register r1 used to calculate the memory address of the store instruction B and the register r1 that should set the immediate data by the preceding arithmetic instruction A.
The register interference is detected and the result is notified to the instruction decoding unit 101.

C4 cycle: (1) Processing for operation instruction A The register unit 103 has a third integer operation unit 104 in the C3 cycle.
Immediate value data (immA) sent to internal data bus 114 is C2
It is stored in the register r1 designated by the control signal 118 in a cycle.

(2) Processing for store instruction B In the instruction decoding unit 101, since the register interference detection unit 102 detects the interference of the register r1 of the store instruction B in the C3 cycle,
As in the C3 cycle, decoding of store instruction B is continued, control information is sent as control signal 118, and immediate data (immB)
Is sent to the immediate data bus 111. The register unit 103 is used to calculate the memory address specified by the control signal 118 32
Bit register data (r1) is transferred to the second internal data bus
The data (r2) of the 32-bit register to be stored in the memory is sent to the first internal data bus 112.

Next, the operation of the data address generation unit 501 will be described. The multiplexer 601 outputs the immediate data (immB) of the immediate data bus 111 to the data bus 210 according to the information of the data select signal 213 sent as the control signal 118. The adder 202 has a 32-bit data bus 210
And the immediate data (i) output to the second internal data bus 113
mmB) and the data (r1) are added, and the result is output to the addition result output bus 211. Multiplexer 203 controls signal 11
The data of the addition result output bus 211 is output to the data address bus 115 according to the information of the address hold signal 214 transferred as 8. Thus, the address (immB) + (r1) of the data to be stored on the data address bus 115 is transmitted.

The operation of the C5 and C6 cycles is the same as that of the C3 and C4 cycles described for the one-clock store, so the description thereof will be omitted (see the description of FIG. 8).

As described above, when register interference occurs between the register r1 used for calculating the memory address of the one-clock store instruction B and the register r1 in which the immediate data should be set by the preceding arithmetic instruction, one cycle is left blank in the pipeline. You can Here, the 1-clock store instruction is given as an example of the instruction requiring the memory address calculation, but if the above-mentioned interference occurs even if another instruction such as a load instruction or a branch instruction requiring the memory address calculation is used for the same reason. 1
A blank occurs in the pipeline for cycles.

Similarly, when register interference occurs between the register used for calculating the memory address of the two-clock store instruction B and the register for which the immediate data is to be set in the preceding arithmetic instruction A, there is a blank in the pipeline for two cycles. Regarding this operation, only one clock store is changed to two clock stores, so detailed description will be omitted.
Figure 11 shows the timing chart.

[Problems to be Solved by the Invention]

However, in the above configuration, if register interference occurs between a register used for memory address calculation of an instruction requiring memory address calculation and a register to which immediate data is to be set by a preceding arithmetic instruction, one cycle is required. If there is a blank space in the pipeline, especially if there is register interference between the register used to calculate the memory address of the two-clock store instruction and the register to which the immediate data should be set in the preceding arithmetic instruction, there is a blank space in the pipeline for two cycles. It had a problem that it could be done.

It is an object of the present invention to provide an information processing device that eliminates blank spaces in a pipeline and enables high speed processing.

[Means for solving the problem]

The information processing apparatus of the present invention has three types of data: an immediate data latch that holds immediate data designated in an instruction, an output of the immediate data latch, immediate data designated in the command, and first data from a register. A first multiplexer for selecting any one of the data, a second multiplexer for selecting one of the output of the immediate data latch and the second data from the register, and an output of the first and second multiplexers And an register adder that detects register interference between consecutive instructions, and when an instruction that stores immediate data in a specific register and an instruction that requires memory address calculation are consecutive, One of a register used for memory address calculation by a subsequent instruction of the register interference detection unit and a register storing immediate data by a preceding instruction. Upon detection of a, the memory address calculated using immediate data of the instruction the adder preceding the immediate data latch is output is held from the first or second one of the multiplexers.

Further, the information processing apparatus of the present invention includes an immediate data latch that holds immediate data designated in an instruction, an output of the immediate data latch, an immediate data designated in the instruction, and a first data from a register. A first multiplexer for selecting any one of the three data, a second multiplexer for selecting any of the second data from the output of the immediate data latch and the register, and the first and second multiplexers It is equipped with an adder that adds the outputs of the above and a register interference detection unit that detects register interference between consecutive instructions, and an instruction that stores immediate data in a specific register and data in a specific register When the instruction to be stored in the memory at the address specified by the sum of register data is linked, the register interference detection unit executes the subsequent memory instruction. When a match between the register used for the address calculation and the register storing the immediate data in the preceding instruction is detected, the adder outputs the immediate data of the preceding instruction held by the immediate data latch which is the output from the second multiplexer. And the immediate data of the subsequent instruction, which is the output from the first multiplexer, are added to calculate the address.

Further, the information processing apparatus of the present invention includes an immediate data latch for holding immediate data designated in an instruction, an output of the immediate data latch, immediate data designated in the instruction, and first data from a register. A first multiplexer for selecting any one of the three data, a second multiplexer for selecting any of the second data from the output of the immediate data latch and the register, and the first and second multiplexers Is provided with an adder for adding the outputs of the registers, a register interference detection unit for detecting register interference between consecutive instructions, and a register unit composed of a plurality of registers capable of outputting the data of two registers at the same time. The instruction to store in the register and the data in the specific register are stored in the memory at the address specified by the sum of the data in the other two registers. When the instructions to be stored are consecutive, if the register interference detection unit detects a match between one register used for memory address calculation in a subsequent instruction and a register storing immediate data in the preceding instruction, the register unit detects The preceding data held by the immediate data latch, which outputs the data of the other register and the data of the register to be stored in the memory, and which is output from the multiplexer of the first or second multiplexer The immediate address data of the instruction to be added and the data of the other register of the subsequent instruction, which is output from the other multiplexer and does not match, are added to calculate the memory address.

[Action]

According to the present invention, according to the above configuration, when an instruction for storing immediate data in a specific register and an instruction requiring memory address calculation are consecutive, the register used by the register interference detection unit for memory address calculation by a subsequent instruction. And the preceding instruction detects a match with the register that stores the immediate data, the adder outputs the immediate value of the preceding instruction held by the immediate data latch which is the output from either the first or second multiplexer. Calculate the memory address using the data.

Further, the present invention is characterized in that, when an instruction for storing immediate data in a specific register and an instruction for storing data in a specific register in a memory at an address designated by a sum of data in other registers are consecutive, When the register interference detection unit detects a match between a register used for memory address calculation in a subsequent instruction and a register storing immediate data in a preceding instruction, the adder outputs the immediate data which is an output from the second multiplexer. The address calculation is performed by adding the immediate data of the preceding instruction held by the latch and the immediate data of the following instruction which is the output from the first multiplexer.

Furthermore, according to the present invention, when an instruction to store immediate data in a specific register and an instruction to store data in a specific register in a memory at an address designated by the sum of data in two other registers are consecutive, When the register interference detection unit detects a match between one register used for memory address calculation in a subsequent instruction and a register that stores immediate data in a preceding instruction, the register unit detects that the register unit does not match the data in the other register. Immediate data of the preceding instruction output by the register to be stored in the memory, and the adder outputs the immediate data latch from the first or second multiplexer;
The memory address is calculated by adding the data of the other register, which is not matched, of the subsequent instruction output from the other multiplexer.

〔Example〕

FIG. 1 shows a block diagram of an information processing apparatus in an embodiment of the present invention. In FIG. 1, 101 is an instruction decoding unit that decodes instructions, 102 is a register interference detection unit that detects register interference between consecutive instructions, and 10
3 is composed of a plurality of registers, a register unit having a zero value register that holds 32-bit 0 data, 104 is an integer operation unit, and 105 is a data transfer that controls data transfer with a data cache (not shown). The control unit 106 is a data address generation unit that generates a data address. 110 is an instruction bus for transferring instructions, 111 is a 32-bit immediate data bus for transferring immediate data, 112 is a 32-bit first internal data bus, 113 is a 32-bit second internal data bus, and 114 is a 32-bit Third internal data bus, 115 is a 32-bit data address bus, 116 is a 32-bit store data bus for transfer to the data cache, 117 is a 32-bit load data bus transferred from the data cache,
Reference numeral 118 is a control signal transmitted from the instruction decoding unit 101, and 119 is a register interference detection signal transmitted from the register interference detection unit 102.

FIG. 2 is a block diagram showing the internal configuration of the data address generation unit 106 of the information processing apparatus in the embodiment of FIG. In the figure, 201, 203, and 205 are 32-bit multiplexers, 202 is a 32-bit adder, 204 is a 32-bit feedback latch, and 206 is a 32-bit immediate data latch. 111 is a 32-bit immediate data bus, 112 is a 32-bit first internal data bus, and 113 is a 32-bit second internal data bus, each of which corresponds to the bus of the same name in FIG. 210 is the output of the multiplexer 201 and the adder 202
Is a 32-bit data bus input to the input terminal 211, and 211 is an output of the adder 202, which is an addition result output bus. A data address bus 115 corresponds to the data address bus 115 in FIG. Reference numeral 212 is a hold data bus for outputting the data of the data address bus 115 one clock before, which is held in the feedback latch 204. Reference numerals 213 and 214 denote a data select signal and an address hold signal for instructing the select conditions of the multiplexers 201 and 203, respectively, both of which are part of the control signal 118 in FIG. 215 and 216 are the first to indicate the selection conditions of the multiplexers 201 and 205, respectively.
The register interference detection signal and the second register interference detection signal, both of which are part of the register interference detection signal 119 in FIG. Reference numeral 217 is a 32-bit data bus which is output from the multiplexer 205 and input to the adder 203.

The operation of the information processing apparatus in the embodiment of the present invention configured as above will be described below.

The information processing apparatus according to the embodiment of the present invention has a four-stage pipeline structure, performs an operation only between the data of two 32-bit registers, and takes an inter-register operation for storing the result in the register again, and performs the operation with the memory. An information processing apparatus adopting a load / store architecture that exchanges data only between a memory and a register.

The operation of the operation instruction and the operation of the 1-clock store and 2-clock store instruction of the information processing apparatus according to the embodiment of the present invention are the same as the operation of the conventional information processing apparatus described in the background art, and thus detailed description will be given. Is omitted.

The operation of the information processing apparatus according to the embodiment of the present invention when an instruction for setting immediate data in a specific register and an instruction requiring memory address calculation are consecutive will be described below. As an example of an instruction requiring memory address calculation, a 1-clock store instruction, a 2-clock store instruction, and a load instruction will be described.

FIG. 3 and FIG. 4 show calculation of the memory address of the store instruction B following the arithmetic instruction A and the store instruction B for setting the immediate data of the information processing device in a specific register in the embodiment of the present invention. FIG. 11 is a timing chart showing an operation when a register to be used coincides with a register to which immediate data is to be set in the preceding arithmetic instruction A (register interference). FIG. 3 shows that when the store instruction B is one clock store,
FIG. 4 shows the case where the store instruction B is a 2-clock store.

Further, FIG. 12 shows an arithmetic instruction A for setting immediate data of the information processing apparatus in a specific register in the embodiment of the present invention.
And the load instruction B are consecutive, and the register used for the memory address calculation of the subsequent load instruction B is the timing diagram showing the operation in the case where the preceding arithmetic instruction A matches the register in which the immediate data should be set.

Using FIG. 1, FIG. 2 and FIG. 3, the operation instruction A for setting the immediate data of the information processing apparatus in this embodiment and the 1-clock store instruction B are consecutive, and the store instruction B The operation when register interference occurs between the register used for memory address calculation and the register for which immediate value data should be set by the preceding arithmetic instruction A will be described. For the sake of simplicity of explanation, the registers that cause interference are
r1, immediate data of operation instruction A (immA), immediate data used for address calculation of 1 clock store instruction B (imm
B), the register data to be stored is (r2).

C1 cycle: (1) Processing for operation instruction A The operation instruction A is fetched and sent to the instruction bus 110.

C2 cycle: (1) Processing for operation instruction A The operation instruction A sent to the instruction bus 110 is transferred to the instruction decoding unit 101.
Deciphers. The instruction decoding unit 101 transmits the control information to the control signal 118.
And send immediate data (immA) as immediate data bus 11
Send to 1. Further, the register unit 103 sends the data of the 32-bit zero value register designated by the control signal 118 to the first internal data bus 112.

(2) Processing for store instruction B The store instruction B is fetched and sent to the instruction bus 110.

C3 cycle: (1) Processing for operation instruction A The integer operation unit 104 inputs the immediate data (immA) sent by the instruction decoding unit 101 to the immediate data bus 111 in the C2 cycle, and the register unit 103 outputs the first internal data bus. The addition with 0 sent to 112 is executed. After the operation is completed, the operation result is sent to the 32-bit third internal data bus 114. At the same time, the immediate data (immA) sent from the instruction decoding unit 101 to the immediate data bus 111 in the C2 cycle is a 32-bit immediate data latch 206.
Latches.

(2) Processing for store instruction B The instruction decoding unit 1 stores the store instruction B sent to the instruction bus 110.
01 deciphers. The instruction decoding unit 101 sends the control information to the control signal 1
18 and send immediate data (immB) as immediate data bus
Send to 111. In parallel with the processing of the instruction decoding unit 101, the register interference detection unit 102 detects the register interference between the register r1 used for calculating the memory address of the store instruction B and the register r1 to which immediate data should be set by the preceding arithmetic instruction A. , Register interference detection signal 119. At this time, the second register interference detection signal 2 in the register interference detection signal 119
16 outputs a signal for the multiplexer 205 to select the output of the immediate data latch 206. The register unit 103 is used to calculate the memory address specified by the control signal 118.
2-bit register data (r1) is sent to the second internal data bus 113, and 32-bit register data (r2) to be stored in the memory is sent to the first internal data bus 112. However, the 32-bit register data (r1) is invalid data because the execution of the arithmetic instruction A is not completed.

Next, the operation of the data address generation unit 106 will be described. The multiplexer 21 uses the information of the data select signal 213 sent as the control signal 118 to determine the data bus 2
The immediate data (immB) of the immediate data bus 111 is output to 10. The multiplexer 205 uses the second register interference detection signal 2
The immediate data latch 206 is provided on the data bus 217 by the information of 16
Output the data (immA) of (corresponding to correct (r1)).
Adder 202 includes 32-bit data buses 210 and 217, respectively.
Add the data output to and add the result to the result output bus
Output to 211. The multiplexer 203 outputs the data of the addition result output bus 211 to the data address bus 115 according to the information of the address hold signal 214 sent as the control signal 118. Thus, the address (immB) + (r1) of the data to be stored on the data address bus 115 is transmitted.

C4 cycle: (1) Processing for operation instruction A The register unit 103 has a third integer operation unit 104 in the C3 cycle.
The data (immA) sent to the internal data bus 114 is stored in the register r1 designated by the control signal 118 in the C2 cycle.

(2) Processing for store instruction B Address sent to data address bus 115 (imm
B) + (r1) is used to access the data cache.
Now assume that the data cache is hit. Further, the data transfer control unit 105 latches the data (r2) sent to the first internal data bus 112.

C5 cycle: (1) Processing for store instruction B The data transfer control unit 105 sends the data (r2) latched in the C4 cycle to the store data bus 116,
Store in data cache.

As described above, in the information processing apparatus according to this embodiment, the arithmetic instruction A for setting immediate data in a specific register
And 1 clock store instruction B continue, and when register interference occurs between the register used for calculating the memory address of the store instruction B and the register to which the immediate operation data should be set in the preceding arithmetic instruction A, the immediate data latch 206 is set. By providing and controlling the multiplexer 205 with the register interference detection signal 119, the processing speed can be increased by one clock as compared with the conventional information processing apparatus.

Next, using FIG. 1, FIG. 2 and FIG. 4, the arithmetic instruction A for setting the immediate data of the information processing apparatus in this embodiment to a specific register and the two-clock store instruction B are consecutive and stored. The operation when register interference occurs between the register used for calculating the memory address of the instruction B and the register for which immediate data should be set in the preceding arithmetic instruction A will be described. For simplification of explanation, register data required for address calculation at 2 clock store is (r1) and (r
2) The data of the register to be stored is (r1), the register in which interference occurs is r1, and the immediate data of the operation instruction A is (immA).

C1 cycle: (1) Processing for operation instruction A The operation instruction A is fetched and sent to the instruction bus 110.

C2 cycle: (1) Processing for operation instruction A The operation instruction A sent to the instruction bus 110 is transferred to the instruction decoding unit 101.
Deciphers. The instruction decoding unit 101 transmits the control information to the control signal 118.
And send immediate data (immA) as immediate data bus 11
Send to 1. Further, the register unit 103 sends the data of the 32-bit zero value register designated by the control signal 118 to the first internal data bus 112.

(2) Processing for store instruction B The store instruction B is fetched and sent to the instruction bus 110.

C3 cycle: (1) Processing for operation instruction A The integer operation unit 104 receives the immediate data (immA) sent by the instruction decoding unit 101 to the immediate data bus 111 in the C2 cycle, and the register unit 103 uses the first internal data bus. The addition with 0 sent to 112 is executed. After the operation is completed, the operation result is sent to the 32-bit third internal data bus 114. At the same time, the immediate data (immA) sent from the instruction decoding unit 101 to the immediate data bus 111 in the C2 cycle is transferred to the 32-bit immediate data latch 206.
Latches.

(2) Processing for store instruction B The instruction decoding unit 1 stores the store instruction B sent to the instruction bus 110.
01 deciphers. The instruction decoding unit 101 sends the control information to the control signal 1
Send as 18. In parallel with the processing of the instruction decoding unit 101, the register interference detection unit 102 detects the register interference between the register r1 used for calculating the memory address of the store instruction B and the register r1 to which the preceding arithmetic instruction A should set the immediate data. Then, the register interference detection signal 119 is transmitted. At this time, the multiplexer 201 outputs the first register interference detection signal 215 in the register interference detection signal 119 to the immediate data latch 20.
The signal for selecting 6 and the signal for the register unit 103 to output the data (r3) of the 32-bit register to be stored in the memory to the first internal data bus 112 are output. The register unit 103 sends the 32-bit register data (r2) used for the memory address calculation designated by the control signal 118 to the second internal data bus 113 and stores it in the memory.
Bit register data (r3) to the first internal data bus
Send to 112.

Next, the operation of the data address generation unit 106 will be described. The multiplexer 201 outputs the data (immA) of the immediate data latch 206 (corresponding to correct (r1)) to the data bus 210 according to the information of the first register interference detection signal 215. The multiplexer 205 outputs the data (r2) of the second internal data bus 113 to the data bus 217 according to the information of the second register interference detection signal 216. The adder 202 adds the data output to the 32-bit data buses 210 and 217, respectively, and outputs the result to the addition result output bus 211. The multiplexer 203 outputs the data of the addition result output bus 211 to the data address bus 115 according to the information of the address hold signal 214 sent as the control signal 118. Thus, the address (r1) + (r2) of the data to be stored on the data address bus 15 is transmitted.

C4 cycle: (1) Processing for operation instruction A The register unit 103 has a third integer operation unit 104 in the C3 cycle.
The data (immA) sent to the internal data bus 114 is stored in the register r1 designated by the control signal 118 in the C2 cycle.

(2) Processing for store instruction B Address sent to data address bus 115 (r1)
Use + (r2) to access the data cache. Now assume that the data cache is hit. Also,
The data transfer control unit 105 uses the first internal data bus 1
Latch the data (r3) sent to 12.

C5 cycle: (1) Processing for store instruction B The data transfer control unit 105 sends the data (r3) latched in the C4 cycle to the store data bus 116,
Store in data cache.

As described above, in the information processing apparatus according to the embodiment of the present invention, the operation instruction A for setting immediate data in a specific register and the two-clock store instruction B are consecutive, and the store instruction B is stored.
When a register interference occurs between the register used for calculating the memory address and the register in which the immediate data should be set by the preceding arithmetic instruction A, the immediate data latch 206 is provided,
By controlling the multiplexer 205 and the register unit 103 with the register interference detection signal 119, compared to a conventional information processing device,
It is possible to speed up the processing for two clocks.

Finally, with reference to FIGS. 1 and 2 and FIG. 12, the operation instruction A and the load instruction B for setting the immediate data of the information processing apparatus in this embodiment to a specific register are consecutive,
An operation will be described when register interference occurs between the register used for calculating the memory address of the load instruction B and the register to which the immediate data is set in the preceding arithmetic instruction A. For the sake of simplicity of explanation, the register causing interference is r1,
The immediate data of the operation instruction A is (immA), the immediate data used for the address calculation of the load instruction B is (immB), and the register to which the data is to be loaded is r2.

C1 cycle: (1) Processing for operation instruction A The operation instruction A is fetched and sent to the instruction bus 110.

C2 cycle: (1) Processing for operation instruction A The operation instruction A sent to the instruction bus 110 is transferred to the instruction decoding unit 101.
Deciphers. The instruction decoding unit 101 transmits the control information to the control signal 118.
And send immediate data (immA) as immediate data bus 11
Send to 1. Further, the register unit 103 sends the data of the 32-bit zero value register designated by the control signal 118 to the first internal data bus 112.

(2) Processing for load instruction B The load instruction B is fetched and sent to the instruction bus 110.

C3 cycle: (1) Processing for operation instruction A The integer operation unit 104 inputs the immediate data (immA) sent by the instruction decoding unit 101 to the immediate data bus 111 in the C2 cycle, and the register unit 103 outputs the first internal data bus. The addition with 0 sent to 112 is executed. After the operation is completed, the operation result is sent to the 32-bit third internal data bus 114. At the same time, the immediate data (immA) sent from the instruction decoding unit 101 to the immediate data bus 111 in the C2 cycle is transferred to the 32-bit immediate data latch 206.
Latches.

(2) Processing for load instruction B The instruction decoding unit 1 receives the load instruction B sent to the instruction bus 110.
01 deciphers. The instruction decoding unit 101 sends the control information to the control signal 1
18 and send immediate data (immB) as immediate data bus
Send to 111. In parallel with the processing of the instruction decoding unit 101, the register interference detection unit 102 detects the register interference between the register r1 used for calculating the memory address of the load instruction B and the register r1 to which immediate data should be set by the preceding arithmetic instruction A. , Register interference detection signal 119. At this time, the second register interference detection signal 2 in the register interference detection signal 119
16 outputs a signal for the multiplexer 205 to select the output of the immediate data clutch 206. The register unit 103 is
The data (r1) of the 32-bit register used for calculating the memory address designated by the control signal 118 is sent to the second internal data bus 113. However, the 32-bit register data (r1) is invalid data because the execution of the arithmetic instruction A is not completed.

Next, the operation of the data address generation unit 106 will be described. The multiplexer 201 uses the information of the data select signal 213 sent as the control signal 118 to determine the data bus 2
The immediate data (immB) of the immediate data bus 111 is output to 10. The multiplexer 205 uses the second register interference detection signal 2
According to the information of 16 the immediate data latch 206
Output the data (immA) of (corresponding to correct (r1)).
Adder 202 includes 32-bit data buses 210 and 217, respectively.
Add the data output to and add the result to the result output bus
Output to 211. The multiplexer 203 outputs the data of the addition result output bus 211 to the data address bus 115 according to the information of the address hold signal 214 sent as the control signal 118. In this way, the address (immB) + (r1) of the data to be loaded on the data address bus 115 is transmitted.

C4 cycle: (1) Processing for operation instruction A The register unit 103 has a third integer operation unit 104 in the C3 cycle.
The data (immA) sent to the internal data bus 114 is stored in the register r1 designated by the control signal 118 in the C2 cycle.

(2) Processing for load instruction B Address sent to data address bus 115 (imm
B) + (r1) is used to access the data cache.
Now assume that the data cache is hit. Data cache hit address (immB) + (r1)
Data is output to the load data bus 117.

C4 cycle: The data transfer control unit 105 sends the data sent from the data cache to the load data bus 117 in the C3 cycle to the third internal data bus 114. The register unit 103 stores the data of the third internal data bus 114 as the control signal 118 in the register r2 of the transmitted address.

Further, the load instruction in which the address of the data to be loaded is the sum (r1) + (r2) of the data in the two registers may be the same as in the case of (r1) + (immB) described above, so a detailed description will be given. Is omitted. In this case, register section
103 outputs the data of two registers used for address calculation to the first internal data bus and the second internal data bus, respectively, and the data address generation unit 106 outputs the first data to the data bus 210.
The point that data on the internal data bus is output is different from the above description.

As described above, in the information processing apparatus according to this embodiment, the arithmetic instruction A for setting immediate data in a specific register
And the load instruction B are consecutive, and when register interference occurs between the register used for calculating the memory address of the load instruction B and the register to which the immediate operation data should be set by the preceding operation instruction A, the immediate data latch 206 is provided, By controlling the multiplexer 205 with the register interference detection signal 119, the processing speed can be increased by one clock as compared with the conventional information processing apparatus.

Although the one-clock store instruction, the two-clock store instruction, and the load instruction have been described as examples of the instructions requiring memory address calculation, the same applies to other instructions such as branch instructions requiring memory address calculation. By controlling, the processing can be speeded up by one clock as compared with the conventional information processing apparatus.

〔The invention's effect〕

According to the information processing apparatus of the present invention, in an instruction (load instruction, 1-clock store instruction or branch instruction) that requires memory address calculation, immediate data of the register used for memory address calculation and the preceding operation instruction should be set. When register interference with a register occurs, one clock processing can be speeded up, and further register interference occurs between the register used for memory address calculation with the two clock store instruction and the register to which the immediate data of the preceding operation instruction should be set. In some cases, the 2-clock processing can be speeded up, and its practical value is great.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing apparatus in an embodiment of the present invention, FIG. 2 is a block diagram of a data address generation unit in FIG. 1, and FIG. 3 is an immediate data of an information processing apparatus in an embodiment of the present invention. Operation when an arithmetic instruction to be set in a specific register and a 1-clock store instruction are consecutive and register interference occurs between the register used for memory address calculation of the store instruction and the register to which immediate data should be set by the preceding arithmetic instruction FIG. 4 is a timing diagram showing a register used for calculating a memory address of a store instruction, in which an arithmetic instruction for setting immediate data of an information processing apparatus in a specific register and a two-clock store instruction are consecutive. Timing diagram showing the operation when register interference with the register that should set immediate data in the preceding arithmetic instruction, FIG. 5 is a block diagram of a conventional information processing apparatus, FIG. 6 is a block diagram of a data address generation unit in FIG. 5, FIG. 7 is a timing diagram showing the operation of an arithmetic instruction of the conventional information processing apparatus, and FIG. Is a timing diagram showing the operation of a 1-clock store instruction of a conventional information processing device,
FIG. 9 is a timing chart showing the operation of a 2-clock store instruction of a conventional information processing apparatus, and FIG. 10 shows an operation instruction and a 1-clock store instruction for setting immediate data in a specific register of the conventional information processing apparatus. FIG. 11 is a timing chart showing the operation in the case where there is continuous register interference between a register used for memory address calculation of a store instruction and a register to which immediate data is to be set by a preceding arithmetic instruction. An operation instruction for setting immediate data to a specific register and a two-clock store instruction are consecutive, and register interference occurs between the register used for calculating the memory address of the store instruction and the register to which the immediate operation data should be set by the preceding operation instruction. FIG. 12 is a timing chart showing the operation in the case of setting the immediate data of the information processing device in the embodiment of the present invention in a specific register. Operation instruction code instruction and are continuous to a timing chart showing an operation when the register conflict between the registers to be set immediate data in arithmetic instructions preceding a register used for memory address calculation of the load instruction is generated. 101 ... Instruction decoding unit, 102 ... Register interference detection unit, 103
...... Register part, 106 ...... Data address generation part, 118 ...
… Control signal, 119… Register interference detection signal, 206… Immediate data latch.

Claims (4)

(57) [Claims] 1. An immediate data latch for holding immediate data designated in an instruction, an output of the immediate data latch, immediate data designated in an instruction, and first data from a register The first multiplexer for selecting any one, the second multiplexer for selecting any one of the output of the immediate data latch and the second data from the register, and the outputs of the first and second multiplexers are added. Includes an adder and a register interference detection unit that detects register interference between consecutive instructions, and detects register interference when an instruction that stores immediate data in a specific register and an instruction that requires memory address calculation are consecutive. Section detects a match between the register used for memory address calculation in the subsequent instruction and the register storing immediate data in the preceding instruction, An information processing device, wherein the adder uses the immediate data of the preceding instruction held by the immediate data latch, which is the output from the first or second multiplexer, to calculate a memory address. . 2. An information processing apparatus, wherein the instruction requiring memory address calculation according to claim 1 is a load instruction, a store instruction or a branch instruction. 3. An immediate data latch for holding immediate data designated in an instruction, an output of the immediate data latch, immediate data designated in the instruction, and first data from a register. A first multiplexer that selects any one, a second multiplexer that selects one of the output of the immediate data latch and the second data from the register, and an addition that adds the outputs of the first and second multiplexers And a register interference detection unit that detects register interference between consecutive instructions.The instruction that stores immediate data in a specific register and the data in the specific register are the sum of the immediate data and the data in another register. When the instruction to be stored in the memory of the specified address continues, the register interference detection unit uses the register used for the memory address calculation by the subsequent instruction. If a match between the register and the register that stores immediate data in the preceding instruction is detected,
The adder adds the immediate data of the preceding instruction held by the immediate data latch, which is the output from the second multiplexer, and the immediate data of the subsequent instruction, which is the output from the first multiplexer, and adds it to the address. An information processing device characterized by performing a calculation. 4. An immediate data latch that holds immediate data specified in an instruction, an output of the immediate data latch, immediate data specified in the instruction, and first data from a register. The first multiplexer for selecting any one, the second multiplexer for selecting any one of the output of the immediate data latch and the second data from the register, and the outputs of the first and second multiplexers are added. An instruction for storing immediate data in a specific register, which includes an adder, a register interference detection unit for selecting register interference between consecutive instructions, and a register unit including a plurality of registers capable of simultaneously outputting data of two registers And the instruction to store the data of the specific register in the memory of the address specified by the sum of the data of the other two registers When the register interference detection unit detects a match between one register used for memory address calculation in a subsequent instruction and a register storing immediate data in a preceding instruction, the register unit does not match the data in the other register. And the data of the register to be stored in the memory, and the adder outputs the immediate data of the preceding instruction held by the immediate data latch output from the first or second multiplexer and the other An information processing device, characterized in that a memory address is calculated by adding the data of the other register, which is not matched, of the subsequent instruction output from the multiplexer.