JP3102399B2 - Data processing apparatus and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU such as a minicomputer or a microcomputer, and more particularly to a data processing apparatus and method suitable for high-speed operation.

[0002]

2. Description of the Related Art Conventionally, various devices have been devised to increase the speed of a computer. A typical approach is a pipeline. The pipeline is not to start the next instruction after completely processing one instruction, but to divide one instruction into multiple stages, and when the first instruction reaches the second stage, the next In this method, processing is performed in a bucket-relay manner, such as starting processing of the first stage of an instruction. For such a method, see Shinji Tomita, "Parallel Computer Configuration Theory", Shokodo p. 25-68. When the n-stage pipeline method is used, one instruction is processed in each pipeline stage. However, n instructions can be simultaneously processed as a whole, and one instruction is provided for each pipeline pitch. Processing of the instruction can be completed.

It is well known that the instruction architecture of a computer has a great effect on its processing method and processing performance. Computers are classified from the viewpoint of instruction architecture.
r) and RISC (Reduced Instruction Computer). In CISC, complicated instructions are processed using microinstructions. On the other hand, in RISC, instead of narrowing down instructions to simple ones, the speed is increased by control using hard-wired logic without using micro-instructions. Hereinafter, the hardware outline and the pipeline operation of both the conventional CISC and RISC will be described.

FIG. 2 is a diagram for explaining a general configuration of a CISC type computer. 200 is a memory interface, 20
1 is a program counter (PC), 202 is an instruction cache, 203 is an instruction register, 204 is an instruction decoder,
205, an address calculation control circuit; 206, a control storage (CS) for storing microinstructions; 207, a microinstruction counter; 208, a microinstruction register;
09 is a decoder, 210 is a register MDR (Memory Dtata Register) for exchanging data with the memory, and 211 is a register MAR (Mem) indicating an operand address on the memory.
ory AddressRegister), 212 is an address adder, 2
13 is a register file, 214 is an ALU (Arithmetic
Logical Unit).

An outline of the operation will be described. The instruction indicated by the PC 201 is fetched from the instruction cache and set in the instruction register 203 through a signal 217. The instruction decoder 204 receives the instruction via a signal 218 and sets the start address of the microinstruction via a signal 220 to the microprogram counter 207. Further, an address calculation method is instructed to the address calculation control circuit 205 through a signal 219. The address calculation control circuit 205 performs reading of registers necessary for address calculation, control of the address adder 212, and the like. The registers required for the address calculation are sent from the register file 213 to the address adder 212 through the buses 226 and 227. On the other hand, the micro instruction is read from the CS 206 every machine cycle, decoded by the decoder 209, and used for controlling the ALU 214 and the register file 213. Reference numeral 224 denotes these control signals. AL
The U 214 calculates the data sent from the register through the buses 228 and 229 and stores the data in the register file 213 again. The memory interface 200 is a circuit that exchanges data with the memory, such as fetching instructions and fetching operands.

Next, the pipeline operation of the computer shown in FIG. 2 will be described with reference to FIGS. 3, 4, and 5. The pipeline has six stages. At the IF (Instruction Fetch) stage, an instruction is read from the instruction cache 202 and set in the instruction register 203. In the D (Decode) stage, the instruction decoder 204 decodes the instruction. In the A (Address) stage, the address adder 2
12, the address of the operand is calculated. O
In the F (Operand Fetch) stage, the operand at the address pointed to by the MAR 211 is fetched through the memory interface 200 and set in the MDR 210. Next, E
In the X (Execution) stage, register file 21
3, and data is read from the MDR 210, sent to the ALU 214, and calculated. Finally, in the W (Write) stage,
The operation result is stored in one register in the register file 213 via the bus 230.

FIG. 3 shows a state in which an addition instruction ADD, which is one of the basic instructions, is continuously processed. One instruction is processed for each machine cycle,
The ALU 214 and the address adder 212 operate in parallel every cycle.

[0008] Figure 4 is a diagram showing the state of a process of conditional branch instruction BRA _CC. A flag is generated by the TEST instruction. FIG. 4 shows a flow when the condition is satisfied. Since the flag is generated in the EX stage, three wait cycles occur before the jump destination instruction is fetched. As the number of pipeline stages increases, the number of waiting cycles increases, and this is a net for performance improvement.

FIG. 5 shows an execution flow of a complicated instruction. Instruction 1 is a complicated instruction. A complicated instruction is an instruction having a large number of memory accesses, such as a string copy, and is usually processed by extending the EX stage many times. The EX stage is controlled by a micro program. The microprogram is accessed once in one machine cycle. Immediately, complicated instructions are processed by reading the microprogram a plurality of times. At this time, since only one instruction enters the EX stage, the next instruction (instruction 2 in FIG. 5) is awaited. In such a case, the ALU 214 is always running, but the address adder 212
Will have play.

Next, the RISC computer will be described.
FIG. 6 is a diagram illustrating a general configuration of a RISC-type computer. 601 is a memory interface, 602 is a program counter, 603 is an instruction cache, 604 is a sequencer, 605 is an instruction register, 606 is a decoder, 60
7 is a register file, 608 is ALU, 609 is MD
R and 610 are MARs.

FIG. 7 shows a processing flow of the basic instruction. IF
In the (instruction Fetch) stage, the instruction pointed to by the program counter 602 is read from the instruction cache and set in the instruction register 605. In addition, the sequencer 604 receives the flag signal 6 from the instruction signal 615 and ALU608.
16, the program counter 602 is controlled.

In the R (Read) stage, the register indicated by the instruction is transferred from the register file 607 to the bus 618,
Through 619, it is transferred to ALU 608. Also, E (Execu
In the stage), an operation is performed by the ALU 608.
Finally, in the W (Write) stage, the calculated result is stored in the register file 607 via the bus 620.

In the RISC type computer, instructions are limited to only basic instructions. The operation is limited between the registers, and instructions involving operand fetch are only load instructions and store instructions. Complex instructions are realized by combining basic instructions. Further, the micro instruction is not used, and the contents of the instruction register 605 are directly decoded by the decoder 606 to control the ALU 608 and the like.

FIG. 7 shows a processing flow of a register-register operation. The pipeline has simple instructions,
It has 4 steps.

FIG. 8 shows a processing flow at the time of a conditional branch. Since the number of pipeline stages is smaller than that of the CISC type computer, the number of waiting cycles is small. In the example of FIG. 8, there is only one waiting cycle. However, it is not always necessary to load operands from a memory and store operands in a memory, in addition to operations between registers. In the CISC type computer, the load of the operand from the memory can be executed in one machine cycle because of the presence of the address adder. However, in the RISC type computer shown in FIG. 6, the load instruction is decomposed into the address calculation instruction and the load instruction. Therefore, two machine cycles are required.

[0016]

The problems of the prior art described above will be summarized and described. In the CISC type computer, an instruction between a memory and a register can be executed in one machine cycle because of the presence of an address adder, but the overhead at the time of branching is large because the number of pipeline stages is large. Further, when executing a complicated instruction, only the E stage moves, so that there is a problem that play occurs in the address adder.

In the RISC type computer, the overhead at the time of branching is small because the number of pipeline stages is small. However, there is no address adder, and there is a problem that two instructions, a load instruction and an instruction for operation between registers, are required for the operation between the memory and the register.

A first object of the present invention is to increase the processing capacity by operating a plurality of arithmetic units without waste.

A second object of the present invention is to reduce the overhead at the time of branching.

A third object of the present invention is to reduce the processing time of complicated instructions such as operations between memories and registers.

[0021]

In order to achieve the above object, the present invention provides an instruction unit for storing a plurality of instructions, decoding means for decoding instructions stored in the instruction unit, and a register file for storing data. And a data processing device having a plurality of arithmetic units connected to the register file and executing an operation based on the decoded instruction, wherein the register file is connected to the plurality of registers and each register, and stores data in each of the arithmetic units. A first signal line for sending, a second signal line connected to the register for receiving data from each arithmetic unit, and a second signal line for connecting the first signal group and the second signal line group. And a switch.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below.

FIG. 9 is a list of instructions of the processor described in this embodiment. All basic instructions are register-to-register operations.
The branch instructions include an unconditional branch instruction BRA, a conditional branch instruction BRA _CC (cc indicates a branch condition), a branch instruction CALL to a subroutine, and a return instruction RT from the subroutine.
There are four of N. In addition, there are a load instruction LOAD and a store instruction STOR. For convenience of explanation, the data type is limited to a 32-bit integer, but is not limited to this.
The address is assigned every 32 bits (4 bytes). For simplicity, the number of instructions is limited as described above, but this does not limit the invention,
If the contents can be processed in one machine cycle, the number of instructions may be further increased.

FIG. 10 shows the instruction format. All instructions have a fixed length of 32 bits. Under the basic instruction, S
The 1, 1, and 2 fields are a bit for indicating whether or not the operation result is reflected in the flag, a field for indicating the first source register, a field for indicating the second source register, and a field for indicating the destination register, respectively. is there.

FIG. 1 shows the configuration of this embodiment. 100 is a memory interface, 101 is a 32-bit program counter, 102 is a sequencer, 103
Is an instruction unit, 104 is a 32-bit first instruction register, 105 is a 32-bit second instruction register, 106 is a first decoder, 107 is a second decoder, and 108 is MD
R, 109 are MAR, 110 is the first arithmetic unit, 11
1 is a register file, and 112 is a second operation unit.

In this embodiment, two cycles are performed during one machine cycle.
Two instructions are read and executed in parallel. FIGS. 11 to 1 show the state of the pipeline processing in this embodiment.
4. The pipeline is IF (Instruction Fetch),
There are four stages: R (Read), EX (Execution), and W (Write).

The operation of this embodiment will be described with reference to FIG.

In the IF stage, two instructions pointed to by the program counter are read, and the bus 115,
Through the steps 117, they are set in the first instruction register 104 and the second instruction register 105, respectively. When the PC is an even number, the instruction at the PC address is stored in the first instruction register in the PC + 1.
The instruction at the address is stored in the second instruction register. Also, P
When C is an odd number, the NOP instruction is set in the first instruction register, and the instruction at the PC address is set in the first instruction register. The sequencer 102 is a circuit that controls a program counter. When neither the first instruction register nor the second instruction register is a branch instruction, the program counter includes:
The value of the previous program counter value + 2 is set. At the time of branching, the branch address is calculated and set in the program counter. At the time of the conditional branch, the success or failure of the branch is determined based on the flag information 123 from the first arithmetic unit and the flag information 124 from the second arithmetic unit. The signal 116 sent from the instruction unit is a competition signal indicating various kinds of competition between the first instruction and the second instruction. When a conflict signal is asserted, hardware control is performed to avoid the conflict. The conflict avoidance method will be described later in detail.

Next, the operation of the R stage during basic instruction processing will be described. In the R stage, the first instruction register 1
04 is decoded by the first decoder 106, and the contents of the second instruction register 105 are
7 is decoded. As a result, the first instruction register 10
4, the contents of the register pointed to by the first source register field S1 are transmitted through the bus 125, and the contents of the register pointed to by the second source register field S2 are transmitted to the bus 126.
To the first operation unit 110 through Also,
The contents of the register pointed to by the first source register S1 of the second instruction register are transferred via the bus 127, and the contents of the register pointed to by the second source register field S2 are transferred to the bus 1
The data is sent to the second arithmetic unit 112 through 28.

Next, the operation of the EX stage will be described.

In the EX stage, the first operation unit 110 performs an operation between the data transmitted by the buses 125 and 126 in accordance with the contents of the operation code of the first instruction register. In parallel, according to the contents of the operation code of the second instruction register 105, the second arithmetic unit 112 performs an arithmetic operation between the data transmitted by the buses 127 and 128.

Finally, the operation of the W stage will be described. In the W stage, the operation result of the first operation unit 110 is stored in the register indicated by the destination field D of the first instruction register via the bus 129. Also, the operation result of the second operation unit 112 is
Is stored in the register pointed to by the destination field D of the second instruction register.

FIG. 11 shows a flow of processing basic instructions continuously. Two instructions are processed in one machine cycle. In this example, the first operation unit and the second operation unit always operate in parallel.

FIG. 12 shows a flow for processing a load instruction or a store instruction as the first instruction and a basic instruction as the second instruction in succession. When the load instruction is executed, the contents of the register pointed to by the S2 field of the first instruction register are transferred to the MA through the bus 126 at the R stage.
Forwarded to R109.

Next, in the EX stage, the operand is fetched through the memory interface 100. Finally, the operand fetched in the W stage is
Through 29, it is stored in the register pointed to by the destination field D of the first instruction register. EX
Fetching an operand in one stage, one machine cycle, is possible if the memory interface has a high-speed cache. In particular, it is easy when the entire computer is integrated on a semiconductor substrate and both the instruction cache and the data cache are on-chip as shown in FIG. Of course, if the cache misses, the operand fetch cannot be completed in one machine cycle. In such a case, the EX stage may be extended by stopping the system clock. This is what is done with conventional computers.

Next, when a store instruction is executed, the contents of the register pointed to by the first source register field S1 of the first instruction register are transferred to the MDR 108 through the bus 125 as data in the R stage. At the same time, the content of the register pointed to by the second lease register field S2 of the first instruction register is used as an address as the bus 126
Through to the MAR109. Next, on the EX stage, MA
The data in the MDR 108 is written to the address indicated by R109. As shown in FIG. 12, even when a load instruction and a store instruction are included in the first instruction, two instructions can be processed in one machine cycle. The processing when a load instruction and a store instruction appear in the second instruction will be described later in detail.

FIG. 13 shows a processing flow when the unconditional jump BRA instruction is executed as the second instruction. B
When the RA instruction is read, in the R stage, the sequencer 102 adds the displacement field d and the program counter, and the program counter 1
Set to 01. During this time, the instruction at the address next to the BRA instruction and the instruction at the next address (instruction 1 and instruction 2 in FIG. 13)
Is read. In the next cycle, jump 2
The instruction is read. In the present embodiment, hardware capable of executing both the instructions 1 and 2 is used. That is, a wait cycle does not occur during the jump instruction processing. This method is called a delayed branch, and is also used in a conventional RISC type computer. However, in the conventional RISC type computer, only one instruction can be executed during the address calculation of the jump instruction. However, in the present embodiment, two instructions are simultaneously processed during the address calculation of the jump instruction. You can improve your ability. The same applies to the processing flow of the CALL instruction and the RTN instruction. A code is generated by a compiler so as to be able to execute a valid instruction as much as possible during the calculation of the address of the branch instruction, but when there is nothing to do, the instructions 1 and 2 in FIG. At this time, a wait of substantially one machine cycle occurs. However, since the number of pipeline stages is small, there is an advantage that overhead at the time of branching can be reduced as compared with the CISC type computer described in the conventional example.

[0038] FIG. 14 shows a processing flow of the conditional branch instruction BRA _CC. The instruction ADD ₁ F sets a flag, and determines the success or failure of the branch according to the result. In this case also, the next instruction address which is likewise placed the BRA _CC instruction and when an unconditional branch instruction processing described with reference to FIG. 13, and FIG. 14 instructions 1, the next instruction, read out in FIG. 142 And processed. However, in the processing flow in the W stage of the two instructions, write to BRA _CC instruction at the branch condition is not satisfied only when the operation result register file is performed. That is, when the branch instruction is taken, the writing of the operation result is suppressed.

As described above with reference to FIGS. 11 to 14, in this embodiment, since two instructions are processed in one machine cycle, there is an advantage that the processing capacity is doubled at the maximum. Further, since the instructions are simple and the number of pipeline stages is as small as four under the control of wired logic, the overhead at the time of branching can be reduced to a maximum of one machine cycle. If the compiler succeeds in optimizing the delayed branch, the overhead can be eliminated.

Further, since complicated processing is executed by a combination of simple instructions, the first arithmetic unit 110 shown in FIG. 1 is compared with the parallel operation of the address adder and the ALU by the pipeline parallel in the conventional CISC type computer. And the parallel operation of the second arithmetic unit 112 can be performed without play. This point will be explained a little more. When loading data from a memory to a register is repeated, the conventional CISC computer can load data one by one in one machine cycle as shown in FIG.
On the other hand, in the present embodiment, two instructions of the ADD instruction for calculating the address and the LOAD instruction using the address are required to load one data. However, as shown in FIG. Since it can be executed, data can be loaded one by one in one machine cycle. In the sense of the parallel operation of the arithmetic units, in both cases, two arithmetic units are operating in parallel at the same time, which is the same in this example.

The more complicated processing was compared.
17 and 18. The instruction 1 shown in FIG. 17 which required six cycles of processing in the EX stage in the conventional CISC type computer can be completed in three cycles in this embodiment as shown in FIG. This is because the operation of the address adder stops during the execution of the instruction 1 in the conventional CISC computer, but in this embodiment, the two arithmetic units can operate in parallel every cycle. .

FIG. 1 illustrates the inside of the first arithmetic unit 110 in FIG. 1500 is an ALU, 1501 is a barrel shifter, and 1502 is a flag generation circuit. Bus 12
The data transferred from 5,126 is processed by the ALU 1500 at the time of addition / subtraction and logical operation, and processed by the barrel shifter at the time of SFT instruction. The processing result is sent to the bus 130.
A flag is generated by the flag generation circuit 1502 based on the operation result, and is transmitted as a signal 123.

FIG. 20 shows an example of the inside of the second arithmetic unit 112 as shown in FIG.

Reference numeral 1600 denotes an ALU, and 1601 denotes a flag generation circuit. The difference from the first arithmetic unit is that there is no barrel shifter. This is omitted because the SFT instruction has a lower frequency of occurrence than the arithmetic and logic operation instruction. This makes it impossible to execute two SFT instructions in one machine cycle, but has the advantage of reducing the amount of hardware. A control method when two SFT instructions appear will be described later.

FIG. 21 shows the contents of the register file 111 of FIG. 1708 is a register, 1700 to 1700
Reference numeral 1709 denotes a bus switch. Each register has four read ports and two write ports. The bus switch is used to bypass the register file when the register pointed to by the destination field of the previous instruction is used immediately in the next instruction. For example, the bus switch 1702 is a bypass switch from the bus 129 to the bus 127, and may be opened when the destination register field D of the first instruction matches the first source register field S1 of the second instruction.

Next, a method for resolving conflict between the first instruction and the second instruction will be described with reference to FIGS. Depending on the combination of the first instruction and the second instruction, both instructions may not be executed simultaneously. This is called a conflict. Conflicts occur in the following cases:

1. When a load or store instruction appears as a second instruction.

2. When the SFT instruction appears as the second instruction.

3. A register pointed by the destination register field D of the first instruction, a register pointed by the first source register field S1 of the second instruction,
Or, the second source register field S2 of the second instruction
When the register pointed to by matches.

Among the above-mentioned conflicts, 1 and 2 are problems peculiar to the present embodiment caused by the inability of the second arithmetic unit to process the load, store and SFT instructions.
In FIG. 1, if the second MDR is added to the bus 127 and the second MAR is added to the bus 128 so that two data can be accessed in one machine cycle by the memory interface, the first race condition can be solved. In addition, if the barrel shifter is also provided in the second arithmetic unit, the second competition condition can be solved. In this embodiment, in order to reduce hardware,
The above race condition has arisen. In such a case, as will be described later, the conflict can be easily resolved. Therefore, according to the required performance and the allowable hardware amount, it is difficult to duplicate only the hardware corresponding to the instruction of the large simultaneous processing. There is an advantage that hardware can be reduced without substantially reducing performance.

A control method when the SFT instruction appears as the second instruction will be described with reference to FIG. In the upper part of FIG. 22, there is a case where the SFT instruction is at the address “3” serving as the second instruction. The lower part of FIG. 22 shows instructions entering the first instruction register and the second instruction register during execution. At the time of the program counter 2, it is detected by hardware that the second instruction is an SFT instruction, and the instruction at address 2 is set in the first instruction register and the NOP instruction is set in the second instruction register. Further, in the next machine cycle, the program counter is incremented by "1" and address 3 is set. Then, the SFT instruction at address 3 is set in the first instruction register, and the NOP instruction is set in the second instruction register. By performing processing in two machine cycles in this way, correct processing can be performed. Of course, it is preferable to perform optimization by a compiler so that the SFT instruction does not appear in the second instruction as much as possible.

Another conflict resolution method will be described with reference to FIG. That is, the odd address serving as the second instruction includes SF
The T instruction is prohibited, and the NOP instruction is inserted when there is no other instruction to execute. In this case, although the program size is slightly increased, there is a good advantage that hardware for resolving conflicts can be omitted.

FIG. 24 shows a processing method when a load instruction appears as a second instruction. There is a load instruction at address 3. The processing method is the same as that for the SFT instruction.

FIG. 25 shows a processing method at the time of register contention. The instruction at address 2 is writing to register 8, and the instruction at address 3 is reading the same register 8. Also in this case, similarly to the SFT instruction, the instruction is executed in two machine cycles.

Load and store instructions and register conflicts may be prevented from being placed at odd addresses to eliminate the conflict. The effect is the same as described above for the SFT instruction.

Next, a description will be given of a hardware method for realizing the processing method described with reference to FIGS. FIG.
FIG. 3 is a diagram showing the configuration of the instruction unit 103 for this purpose. 2300 is a conflict detection circuit, 2301 is a cache memory, 2302 is a first mask circuit, and 2303 is a second mask circuit. The value of the normal program counter is input from the bus 113, and the instruction indicated by the program counter and the instruction at the next address are sent to the bus 2305 and the bus 2306. At the time of a cache mishit, an instruction is fetched by the memory interface 100 and written to the cache 2301 via the bus 113. At this time, the conflict detection circuit checks the conflict between the first instruction and the second instruction, and if there is a conflict, a conflict signal 2304
Assert The cache is provided with a bit indicating a conflict state between the two instructions, one bit at a time for every two instructions, and stores a conflict signal 2304 upon a cache miss. The first mask circuit receives, as inputs, a first instruction, a second instruction, a conflict bit, and the least significant bit of a program counter.
As shown in (1), a signal 115 to the first instruction register 104 is controlled. The second mask circuit receives the second instruction, the conflict bit, and the least significant bit of the program counter as inputs, and also sends out a signal 117 to the second instruction register 105 as shown in FIG.

As shown in FIG. 27, when both the conflict bit and the least significant bit of the PC are 0, the first instruction is stored in the first instruction register.
The second instruction is sent to the second instruction register. This is usually the case. When the conflict bit is 1 and the PC least significant bit is 0, the first instruction is sent to the first instruction register and the NOP instruction is sent to the second instruction register. This is a process in the first machine cycle at the time of competing instruction processing. Next, when the contention bit is 1 and the PC least significant bit is 1, the second instruction is sent to the first instruction register and the NOP is sent to the second instruction register. This is a process in the second machine cycle at the time of competing instruction processing. By the above processing, the processing flow of the conflicting instruction described in FIGS. 22, 23, and 25 is realized. When the branch instruction branches to an odd address, as shown in FIG. 27, only the second instruction is executed irrespective of the value of the conflict bit, so that correct processing can be performed. The cache read is performed every cycle, but the write to the cache is performed only when the cache has a mishit and over several machine cycles. Therefore, it is effective to operate the conflict detection circuit at the time of cache writing and to hold the conflict bit in the cache in order to reduce the machine cycle.

FIG. 28 shows an instruction cache 2301 for the 26th instruction.
This is a diagram showing the configuration of FIG. 2500 is a directory, 25
01 is a data memory, 2502 is a selector, 2503 is an address register, 2504 is a write register, 250
Reference numeral 5 denotes a comparator, and reference numeral 2506 denotes a cache control circuit. The cache shown in FIG. 28 has almost the same configuration as that of a normal cache.
Each byte has a contention bit holding field. When reading the cache, the PC bottom is ignored.
Always the first instruction 2305, the second instruction 2306 and the conflict signal 1
16 is different.

In FIG. 28, the data memory has 8K words and the block size is 32 bytes. The signal 113 sent from the program counter is stored in the address register 2503.
Is set to The directory 2500 and the data memory 2501 are looked up with 3 to 12 bits of the address. The comparator 2505 compares the directory output with bits 13 to 32 of the address register. If they do not match, a signal 2508 causes the cache control circuit 2506 to
Let it know. The cache control circuit 2506 reads the block containing the missed instruction from the main memory, and sets the read block in the data memory 2501. On the other hand, the selector 2502 uses the first and second bits of the address register to select necessary two instructions from the block. First
The instruction and the second instruction are always in the same block, and only one of them does not miss.

FIG. 29 shows another example of the configuration of the instruction unit 103 in FIG. 2600 is cache memory,
2601 is a conflict detection circuit, 2302 is a first mask circuit,
2303 is a second mask circuit. The difference from the configuration of FIG. 26 is that there is no conflict bit holding field in the hash,
First instruction 2601 and second instruction 2602 of cache output
Is monitored by the conflict detection circuit 2601 every cycle. First mask circuit 2302, second mask circuit 2
The operation of 303 is the same as that of FIG. According to this embodiment, since the conflict detection circuit operates every cycle after the cache is read, there is a disadvantage that the machine cycle is extended, but there is an advantage that there is no need for a conflict bit field in the cache.

Furthermore, in the present embodiment, by taking advantage of the fact that two instructions are processed in one machine cycle, it is possible to further speed up conditional branch instructions in special cases as shown in FIG. That is, in the conditional branch instruction, when the branch destination at the time when the condition is satisfied is the next instruction (instruction 2 in FIG. 30), the instructions 2 and 3 are executed regardless of whether or not the condition is satisfied. By controlling whether the W stage of instruction 1 is suppressed, it is possible to eliminate a waiting cycle when the condition is satisfied. However, in this case, the conditional branch instruction is always placed on the first instruction side. In the ordinary conditional branch, as described with reference to FIG. 14, when the branch is taken, one wait cycle occurs. In other words, in the present invention, two instructions are processed in one machine cycle, so that the condition of the conditional branch instruction on the first instruction side is satisfied without affecting the instruction processing flow in units of two instructions. Thus, the execution of the instruction on the second instruction side can be controlled.

Further, in this embodiment, "atomic" processing can be easily realized by taking advantage of processing two instructions in one machine cycle. Atomic processing is processing that is always performed continuously, and is used for synchronization between processes. FIG. 31A illustrates the case of a conventional computer, and FIG. 31B illustrates the present embodiment. In (a), there is a possibility that an interrupt occurs between the instructions, but in (b), no interrupt occurs between the instructions 1 and 2 and between the instructions 3 and 4. For this reason,
In (a), there is a possibility that a program for processing another process may be inserted in the space between arbitrary instructions, but in (b),
There is an advantage that instructions 1 and 2 and instructions 3 and 4 are guaranteed to be executed in succession.

FIG. 32 is a diagram showing the configuration of another embodiment of the present invention. In this embodiment, four instructions can be processed in one machine cycle. 3200 is a memory interface, 3201 is a program counter, 3202 is a sequencer, 3203 is an instruction unit, 3204 to 32
07 is the first to fourth instruction registers, 3208 to 3211
Are first to fourth decoders, 3212 is MDR, 3213 is MAR, 3214, 3215, 3217, and 3218 are first decoders.
4 operation units and 3216 are register files. Each operation unit shares the register file 3216. The description of the operation of each unit is the same as that of the embodiment shown in FIG.

Similarly, although it is possible to further increase the degree of parallelism, there are also programs in which a branch instruction is present at a rate of one in several instructions. In such a program, even if the degree of parallelism is extremely increased, , Not very effective. Two
About four instructions simultaneous processing is reasonable. For programs with fewer branches and less contention, increasing the degree of parallelism will effectively improve performance. In addition, the degree of parallelism is 2 ⁿ (n is a natural number)
Thus, control of the instruction unit can be facilitated.

Further, another embodiment of the present invention will be described. In the above embodiments, simultaneous processing of a plurality of instructions has always been performed. Normally, one instruction is processed in one machine cycle, and a benefit can also be obtained by partially processing a plurality of instructions simultaneously. FIG. 33 shows three examples. FIG.
In 3 (a), the first instruction is in the main memory, the second instruction is only at the head of the address space, and is stored in ROM. In (b), both the first instruction and the second instruction are ROMized at the head of the address space. Other parts are first
Only the instructions are in main memory. (C) is almost the same as (a), except that the ROMized part of the second instruction is in the middle of the address space. The configuration of the entire computer is the same as that of FIG. 1, and the instruction unit 103 may be changed. ROM
In the part, a program with high use frequency and high parallelism is written and used by a subroutine call from the main routine. Since the ROM portion may have a small capacity, an optimum program can be created by an assembler without a compiler.

FIG. 34 is a diagram for explaining FIG. 33 (a).
FIG. 1 shows the configuration of the instruction unit 103. 2
900 is a cache, 2901 is a 4K ROM, 29
03 is a mask circuit, and 2902 is a mask circuit control circuit. The mask circuit control circuit constantly monitors the address 113, and asserts the valid signal 2904 only when the upper 12 to 31 bits of the address are all zero. The mask circuit 2903 outputs the ROM output 2905 to the second instruction register 1 only when the valid signal 2904 is asserted.
It is transmitted as 17. At other times, a NOP command is sent.

In order to realize FIG. 33 (c), FIG.
The mask circuit control circuit 2902 may be as shown in FIG. 3000 is a comparator and 3001 is a base register. The upper 12 to 31 bits of the base register;
When the upper 12 to 31 bits of the address 113 match, the comparator 3000 asserts a valid signal 2904.

In order to realize FIG. 33 (b), the instruction unit 103 in FIG. 1 may be configured as shown in FIG. 2
The functions 901, 902, and 2903 are the same as those of the same numbers described in FIG. 3100 is a cache,
3101 is a 4K word ROM, 3102 is a selector control circuit, and 3107 is a selector. Selector control circuit 31
02 always monitors the upper 12 to 31 bits of the address 113, and only when they are all zero, the ROM selection signal 3
Assert 105. The selector 3107 sends out the ROM output signal 3104 as the output 115 to the first instruction register only when the ROM selection signal 3105 is asserted. At other times, the cache output 3103 is sent.

As described with reference to FIG. 33 to FIG. 36, hardware can be reduced by partially performing simultaneous processing of a plurality of instructions and converting the part to a ROM. Also, ROM
Since only the part can be optimally designed by the assembler, there is an advantage that it is not necessary to develop a compiler that is aware of simultaneous processing of a plurality of instructions. Further, by rewriting the ROM portion, it is possible to realize a high speed suitable for each application.

[0070]

According to the present invention, a complicated instruction is decomposed into basic instructions, and a plurality of instructions are simultaneously read and executed in one machine cycle. Processing capacity can be increased. Also, since the function of the instruction is simple and the number of pipeline stages can be shortened,
The overhead at the time of branching can be reduced.

Further, since a plurality of arithmetic units operate in parallel, the processing time of complicated processing can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall block of an embodiment of the present invention.

FIG. 2 is a diagram showing an entire block of a conventional example.

FIG. 3 is a timing chart illustrating the operation of FIG. 2;

FIG. 4 is a diagram showing a timing chart for explaining the operation of FIG. 2;

FIG. 5 is a diagram showing a timing chart for explaining the operation of FIG. 2;

FIG. 6 is a diagram showing an overall block of another conventional example.

FIG. 7 is a timing chart illustrating the operation of FIG. 6;

FIG. 8 is a diagram showing a timing chart for explaining the operation of FIG. 6;

FIG. 9 is a diagram showing a list of instructions according to an embodiment of the present invention.

FIG. 10 is a diagram showing an instruction format according to an embodiment of the present invention.

FIG. 11 is a diagram showing a timing chart for explaining the operation of one embodiment of the present invention.

FIG. 12 is a diagram showing a timing chart for explaining the operation of one embodiment of the present invention.

FIG. 13 is a diagram showing a timing chart for explaining the operation of one embodiment of the present invention.

FIG. 14 is a diagram showing a timing chart for explaining the operation of one embodiment of the present invention.

FIG. 15 is a diagram showing a timing chart for explaining the operation of the conventional example.

FIG. 16 is a timing chart illustrating the operation of one embodiment of the present invention.

FIG. 17 is a timing chart for explaining the operation of one embodiment of the present invention.

FIG. 18 is a diagram showing a timing chart for explaining the operation of one embodiment of the present invention.

FIG. 19 is a diagram illustrating a configuration of a first arithmetic unit 110 of FIG. 1;

FIG. 20 is a diagram showing a configuration of a second arithmetic unit 112 in FIG. 1;

FIG. 21 is a diagram showing a configuration of a register file 111 of FIG. 1;

FIG. 22 is a diagram for explaining the operation of the embodiment of the present invention shown in FIG. 1;

FIG. 23 is a diagram for explaining the operation of the embodiment of the present invention shown in FIG. 1;

FIG. 24 is a diagram for explaining the operation of the embodiment of the present invention shown in FIG. 1;

FIG. 25 is a diagram for explaining the operation of the embodiment of the present invention shown in FIG. 1;

FIG. 26 is a diagram showing a configuration of an instruction unit 103 of FIG. 1;

FIG. 27 is a diagram for explaining the operation.

FIG. 28 is a diagram showing a configuration of a cache 2301 in FIG. 26;

FIG. 29 is a diagram showing another configuration of the instruction unit 103 of FIG. 1;

FIG. 30 is a diagram showing a timing chart for explaining the operation of one embodiment of the present invention.

FIG. 31 is a diagram showing an instruction configuration.

FIG. 32 is a diagram showing an entire block of another embodiment of the present invention.

FIG. 33 is a diagram illustrating another embodiment of the present invention in which a plurality of instructions are simultaneously processed.

FIG. 34 is a diagram for explaining another embodiment of the present invention in which a plurality of instructions are simultaneously processed.

FIG. 35 is a diagram for explaining another embodiment of the present invention in which a plurality of instructions are simultaneously processed.

FIG. 36 is a diagram for explaining another embodiment of the present invention in which a plurality of instructions are simultaneously processed.

[Explanation of symbols]

103: instruction unit, 104: first instruction register, 1
05: second instruction register, 110: first arithmetic unit,
111: register file, 112: second operation unit.

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-62-70938 (JP, A) JP-A-2-127773 (JP, A) JP-A-63-136138 (JP, A) JP-A-63-136138 86033 (JP, A) JP-A-63-47834 (JP, A) JP-A-63-148330 (JP, A) JP-A-2-128223 (JP, A) Naohiko Irie (three outsiders) 1 High-speed Technique and Performance Prediction of “Shinpu” Processor Based on Instruction Flow / Multiple Instruction Pipeline) ”, Information Processing Society of Japan, Vol. 88, No. 79 (ARC-73), October 31, 1988, p. 77-84 (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 9/38

Claims (20)

(57) [Claims] A memory for storing a plurality of instructions; a register for storing data; a plurality of arithmetic units capable of executing the plurality of instructions stored in the memory in parallel; A plurality of first signal lines for sending the obtained data to each of the computing units; a plurality of second signal lines for storing data, which is the computation result of each of the computing units, in the register; possess a bypass circuit for connecting the plurality of the first signal lines and a plurality of said second signal line in order to use the data is a result calculated by the arithmetic unit in the calculation of the next cycle , The bypass circuit executes instructions executed by the plurality of arithmetic units.
Data processing device controlled by . 2. A memory for storing a plurality of instructions, a plurality of registers for storing data, and different instructions stored in the memory can be executed in parallel.
A plurality of computing units, an output unit of each of the registers, a plurality of first signal lines connected to an input unit of each of the computing units, an output unit of each of the computing units, and a A plurality of second signal lines connected to the input unit; a plurality of the first signal lines and a plurality of the second signal lines in order to use data obtained as a result of the operation in the operation in the next cycle; instruction possess a bypass circuit for connecting the signal line, the bypass circuit is to be executed by a plurality of said arithmetic unit
Data processing device controlled by . 3. The data processing device according to claim 1, wherein said bypass circuit is constituted by a switch for connecting said first signal line and said second signal line. 4. A memory for storing a plurality of instructions; a register for storing data; a plurality of arithmetic units capable of executing a plurality of instructions stored in the memory in parallel; has been a plurality of first signal lines for sending the data to the arithmetic unit, a plurality of second signal lines for storing data in the register is a result calculated by the arithmetic unit, one A data processing device comprising: a plurality of switches for connecting a plurality of the first signal lines and a plurality of the second signal lines so that an operation result of an operation unit is used in an operation of another operation unit. 5. A memory for storing a plurality of instructions, a plurality of registers for storing data, and different instructions stored in the memory can be executed in parallel.
A plurality of arithmetic units; a plurality of first signal lines connected to each of the registers and each of the arithmetic units for transferring data from the register to the arithmetic units; In order to transfer data to the above, the plurality of second signal lines connected to each of the arithmetic units and the respective registers, and the operation result of one of the arithmetic units is used for the operation of another arithmetic unit. A data processing device having a plurality of switches for connecting the plurality of first signal lines and the plurality of second signal lines. 6. A memory for storing instructions, a register file for storing data, and a plurality of arithmetic units for executing operations based on the instructions stored in the memory. In the first operation and the second operation executed by the first operation unit, the data output from the first operation unit is converted into the second operation so that the operation result of the first operation can be used in the second operation. A data processing device having a bypass circuit for transferring to an input of a device. 7. A data processing apparatus according to claim 6, wherein said register file has a plurality of registers. 8. The arithmetic unit according to claim 7, wherein the plurality of registers and the plurality of arithmetic units are a plurality of first signal lines for transmitting data stored in the registers to the arithmetic unit, and a plurality of arithmetic units. A plurality of second signal lines for storing certain data in the register, wherein the bypass circuit is a switch for connecting the plurality of first signal lines and the plurality of second signal lines; Processing equipment. 9. A data processing apparatus according to claim 6, wherein said first operation and said second operation are executed by different arithmetic units. 10. A memory for storing a plurality of instructions, a register for storing data, a plurality of arithmetic units for executing an operation based on the instructions stored in the memory, and a plurality of data for storing the data stored in the register. A plurality of first signal lines for sending to the above-mentioned computing units, a plurality of second signal lines for storing the data as the computation results of the respective computing units in the above-mentioned registers , When the address of the register indicated by the instruction to be executed matches, the address of the register is
A data processing device having a bypass circuit capable of transferring data between the specified computing units . 11. A memory for storing a plurality of instructions, a plurality of registers for storing data, a plurality of arithmetic units for executing operations based on the instructions stored in the memory, and A plurality of first signal lines connected to the respective registers and the respective arithmetic units for transmitting data; and the respective arithmetic units and respective respective first and second lines for transmitting data from the arithmetic units to the registers. When the plurality of second signal lines connected to the register and the address of the register indicated by the instruction executed between different arithmetic units match, the arithmetic unit whose register address matches
And a bypass circuit capable of transferring data between the data processing devices. 12. The data processing device according to claim 10, wherein the continuous instructions are executed by different arithmetic units. 13. A memory for storing a plurality of instructions, a register for storing data, a plurality of arithmetic units for performing operations in accordance with the instructions stored in the memory, and a plurality of arithmetic units for storing the data stored in the registers. A plurality of first signal lines for sending, a plurality of second signal lines for storing data obtained as a result of the arithmetic operation in the register, and an instruction executed between different arithmetic units The arithmetic unit whose register address matches when the register address indicated by
A data processing device having a switch for connecting the first signal line and the second signal line so that data can be transferred between the first signal line and the second signal line. 14. A memory for storing a plurality of instructions, a plurality of registers for storing data, a plurality of arithmetic units for executing operations according to the instructions stored in the memory, and data from the registers to the arithmetic unit. Send multiple first
And a plurality of second lines for transmitting data from the arithmetic unit to the register.
And a signal line, when the address of the register indicated by the instruction to be executed between different calculator match, computing unit address register matches
A data processing device having a switch for connecting the first signal line and the second signal line so that data can be transferred between the first signal line and the second signal line. 15. A data processing apparatus according to claim 13, wherein said two consecutive instructions are executed by different arithmetic units. 16. A memory for storing a plurality of instructions, a register for storing data, a plurality of arithmetic units capable of executing the instructions stored in the memory in parallel, and a plurality of arithmetic units for storing the data stored in the register. A first signal line group for sending to the arithmetic unit, a second signal line group for storing data as an operation result of each arithmetic unit in the register, and a first signal line group. A data processing device comprising: a bypass circuit for connecting to the second signal line group; storing data as a calculation result of the arithmetic unit in the register; and transmitting the data to another arithmetic unit through the bypass circuit. 17. A memory for storing a plurality of instructions, a plurality of registers for storing data, a plurality of arithmetic units capable of executing the instructions stored in the memory in parallel, and data from the registers to the arithmetic unit. And a plurality of first signal lines connected to each of the registers and each of the arithmetic units, and each of the arithmetic units to transfer data from the arithmetic unit to the registers. A plurality of second signal lines connected to the register, and a bypass circuit for transferring data from the second signal line to the first signal line. A data processing device for storing data in the register and transferring the data to another arithmetic unit in the same cycle. 18. A memory for storing a plurality of instructions, a plurality of registers for storing data, and executing an operation based on the instructions stored in the memory.
Transferring data from the first and second arithmetic units and the register to the first arithmetic unit
Signal line for transferring data from the register to the second computing unit
Signal line for transferring data from the first arithmetic unit to the register
Signal line for transferring data from the second arithmetic unit to the register
A fourth signal line, a data the third signal line to said second signal line transfers for
A first bypass circuit for transferring data from the fourth signal line to the first signal line
Data processing apparatus having a second bypass circuit for
Place. 19. A data processing apparatus according to claim 16, 17 or 18, wherein said bypass circuit is constituted by a switch. 20. The method of claim 1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 11, 12, 13, 14, 15, 16,
In any one of 17, 18, and 19, the data processing device has a decoder for decoding an instruction stored in the memory, and the arithmetic unit performs an operation based on the instruction decoded by the decoder.