JP2012150589A - Arithmetic unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a processing unit improving use efficiency of computing resources and being able to prevent an increase in time required for processing of orders.SOLUTION: An arithmetic unit 100 of this embodiment comprises a program memory 21, an instruction fetch part 22 and a decode part 24. The program memory 21 memorizes an instruction A and an instruction B performing memory access processing to retrieve appointed data from a data memory 40 in stages mutually different of pipe line treatment. The instruction fetch part 22 fetches the instruction A and the instruction B at one time. The decode part 24 decodes the fetched instruction A and instruction B at one time.

Description

  Embodiments described herein relate generally to an arithmetic device.

  2. Description of the Related Art Conventionally, there has been known an arithmetic device (for example, a microprocessor) adopting a pipeline system in which processing of one instruction is divided into a plurality of processing units and each processing is executed by a separate hardware circuit.

JP 2003-99248 A

  In an arithmetic device adopting a pipeline system, for example, it is required to efficiently use arithmetic resources such as a memory. The problem to be solved by the present invention is to provide a computing device capable of improving the utilization efficiency of computing resources.

  The arithmetic device according to the embodiment includes an instruction storage unit, a fetch unit, and a decoding unit. The instruction storage unit stores a first instruction and a second instruction that execute arithmetic processing using arithmetic resources at different stages of pipeline processing. The fetch unit fetches the first instruction and the second instruction at the same time. The decoding unit simultaneously decodes the fetched first instruction and second instruction.

The block diagram of the arithmetic unit which concerns on this embodiment. The block diagram of the load store unit which concerns on embodiment. The figure for demonstrating each process of the command A and the command B. FIG. The timing chart which shows operation | movement of the arithmetic unit of embodiment. The timing chart which shows operation | movement of the arithmetic unit of a comparison. The timing chart which shows operation | movement of the arithmetic unit of a comparison. The block diagram of the arithmetic unit of a modification. The figure for demonstrating the process of the command C. FIG. The timing chart which shows operation | movement of the arithmetic unit of a modification.

  FIG. 1 is a block diagram illustrating an example of a schematic configuration of the arithmetic device 100 according to the present embodiment. As shown in FIG. 1, the arithmetic device 100 includes a control unit 10, a load / store unit 20, a data register 30, and a data memory 40. Various data are stored in the data memory 40, which is an example of a computing resource.

  The control unit 10 controls the arithmetic device 100 as a whole. In response to an instruction from the control unit 10, the load / store unit 20 executes fetching of an instruction and decoding of the fetched instruction. Then, the load store unit 20 executes a process of reading data from the data memory 40 (referred to as “memory access process”) in accordance with the decoded instruction. Details of the memory access process will be described later. The data register 30 stores data read by the memory access process and a correction value (offset) used for calculating address information described later.

  FIG. 2 is a block diagram illustrating an example of a detailed configuration of the load store unit 20. As shown in FIG. 2, the load / store unit 20 includes a program memory 21, an instruction fetch unit 22, registers 23 a to 23 f, a decode unit 24, an address information calculation unit 25, a selection unit 26, and a reading unit 27. And a writing unit 28.

  The program memory 21 stores two types of instructions (instruction A and instruction B) described in a predetermined program code. In the present embodiment, each of the instruction A and the instruction B is an instruction for causing the load / store unit 20 to read data from the data memory 40. Each process of the instruction A and the instruction B is divided into a plurality of stages (processes), and the above-described memory access process is performed at different stages. More specifically, as shown in FIG. 3, the processing of the instruction A is divided into a stage T1, a stage T2, a stage T3, and a stage T4. Then, the fetch process IF is performed at stage T1, the decode process ID is performed at stage T2 immediately after stage T1, the memory access process MEM is performed at stage T3 immediately after stage T2, and stage T4 immediately after stage T3. Then, the write back processing WB is performed. That is, in the process of the instruction A, the memory access process MEM is performed in the third stage.

  Further, as shown in FIG. 3, the processing of instruction B is divided into stage T1, stage T2, stage T3, stage T4, and stage T5. Then, a fetch process IF is performed at stage T1, a decode process ID is performed at stage T2, an address calculation process EX is performed at stage T3, a memory access process MEM is performed at stage T4, and a write back process is performed at stage T5. WB is performed. That is, in the process of the instruction B, the memory access process MEM is performed in the fourth stage, so that the number of stages until the memory access process MEM is performed is one more than the process of the instruction A. Detailed contents of each process will be described later. In the present embodiment, the time length of each stage (T1 to T5) is the same. That is, the number of clock cycles required for the processing of each stage is the same.

  Returning to FIG. 2 again, the description will be continued. The instruction fetch unit 22 is configured to be able to fetch two instructions simultaneously from the program memory 21. For example, the instruction fetch unit 22 may be configured by two fetch circuits, or may be configured by employing a VLIW (Very Long Instruction Word) method. The instruction fetch unit 22 fetches the instruction A and the instruction B stored in the program memory 21 at the same time in accordance with an instruction from the control unit 10. More specifically, it is as follows. The control unit 10 supplies the instruction fetch unit 22 with instruction address information indicating areas in the program memory 21 in which the instruction A and the instruction B to be read are stored. Then, the instruction fetch unit 22 refers to the instruction address information from the control unit 10, reads each of the instruction A and the instruction B from the program memory 21, writes the read instruction A into the register 23a, and reads the read instruction B. Write to register 23b.

  The decoding unit 24 is configured to be able to decode two instructions simultaneously. For example, the decoding unit 24 may be configured by two decoding circuits, or may be configured by adopting the VLIW method. The decode unit 24 simultaneously decodes the instruction A written in the register 23a and the instruction B written in the register 23b. In the present embodiment, address information indicating an area where data to be read out is stored in the data memory 40 is described in the program code constituting the instruction A. Therefore, the decoding unit 24 decodes the decoded instruction A. From this, address information can be identified immediately. Then, the decoding unit 24 writes the address information specified from the decoded instruction A to the register 23c, and the address information written to the register 23c is supplied to the selection unit 26 at the subsequent stage.

  On the other hand, in the program code constituting the instruction B, the above address information is not described, but calculation information for calculating the address information is described. In the present embodiment, the calculation information includes reference information indicating the reference value I at the time of calculating the address information, and register information indicating a region in the data register 30 in which the correction value R to be added to the reference value I is stored. It consists of. The decoding unit 24 writes the reference value I specified from the decoded instruction B to the register 23d, and the reference value I written to the register 23d is supplied to the subsequent address information calculation unit 25. In addition, the decoding unit 24 supplies the register information specified from the decoded instruction B to the data register 30. The data register 30 receives the register information from the decoding unit 24 and reads the correction value R stored in the area indicated by the received register information. Then, the data register 30 supplies the read correction value R to the register 23f.

  The address information calculation unit 25 calculates address information from the reference value I supplied from the register 23d and the correction value R supplied from the register 23f. The address information calculation unit 25 is configured by an adder, for example, and a value indicating the addition result of the reference value I supplied from the register 23d and the correction value R supplied from the register 23f is address information. The address information calculated by the address information calculation unit 25 is written in the register 23e. The address information written in the register 23e is supplied to the selection unit 26 at the subsequent stage.

  The selection unit 26 has address information written in the register 23c (that is, address information specified by the instruction A) and address information written in the register 23e (that is, address information specified by the instruction B). Any one of them is selected and supplied to the subsequent reading unit 27. The selection unit 26 includes a selection circuit such as a multiplexer, for example. Address information (address information specified by the instruction A) written in the register 23c is supplied to one input end, and the other input end receives The address information (address information specified by the instruction B) written in the register 23e is supplied. The selection unit 26 is supplied with a selection control signal (not shown) from the decoding unit 24. The selection unit 26 supplies data (address information) supplied to one of the one input terminal and the other input terminal to the subsequent reading unit 27 in accordance with the selection control signal from the decoding unit 24. .

  The reading unit 27 reads data stored in the area indicated by the address information supplied from the selection unit 26 in the data memory 40. The reading unit 27 supplies the read data to the writing unit 28. The writing unit 28 writes the data supplied from the reading unit 27 in a predetermined area of the data register 30.

  FIG. 4 is a timing chart for explaining the operation of the arithmetic device 100. Hereinafter, a specific operation of the arithmetic device 100 will be described with reference to FIG. In the present embodiment, the arithmetic unit 100 executes the instruction A and the instruction B simultaneously in a pipeline manner. Details will be described below. Here, the time length of each period (T11 to T55) in FIG. 4 is the same as the time length of each stage (T1 to T5) described above.

  As shown in FIG. 4, the first period T11 is stage T1 (see FIG. 3) in the processing of instruction A and instruction B, and the fetch processing IF of instruction A and the fetch processing IF of instruction B are executed. . More specifically, the instruction fetch unit 22 simultaneously reads the instruction A and the instruction B from the respective areas indicated by the instruction address information supplied from the control unit 10 in the program memory 21 and registers the read instruction A in the register. Write to the register 23b and write the read instruction B to the register 23b.

  As shown in FIG. 4, a period T22 immediately after the period T11 is a stage T2 (see FIG. 3) in each process of the instruction A and the instruction B, and the decoding process ID of the instruction A and the decoding process ID of the instruction B are Executed. More specifically, the decoding unit 24 simultaneously decodes the instruction A written in the register 23a and the instruction B written in the register 23b. Then, the decoding unit 24 writes the address information specified from the decoded instruction A to the register 23c. The decoding unit 24 writes the reference value I specified from the decoded instruction B to the register 23 d and supplies the register information specified from the content of the decoded instruction B to the data register 30.

  As shown in FIG. 4, a period T33 immediately after the period T22 is a stage T3 (see FIG. 3) in each processing of the instruction A and the instruction B, and the memory access process MEM of the instruction A is executed while the instruction B The address calculation process EX is executed. More specifically, it is as follows. In the period T33, the selection unit 26 in FIG. 2 receives a selection control signal for instructing selection of data supplied to one input terminal (that is, address information specified by the instruction A written in the register 23c). Supplied from the decoding unit 24. As a result, the address information specified by the instruction A is supplied to the reading unit 27. Then, the reading unit 27 reads the data stored in the area indicated by the address information supplied from the selection unit 26 in the data memory 40. The above is the contents of the memory access processing MEM of the instruction A.

  In the period T33, the data register 30 reads the correction value R stored in the area indicated by the register information from the decoding unit 24, and supplies the read correction value R to the register 23f. Then, the address information calculation unit 25 calculates the address information specified by the instruction B by adding the reference value I written in the register 23d and the correction value R supplied from the register 23f. Address information is written to the register 23e. The above is the content of the instruction B address calculation processing EX.

  As shown in FIG. 4, a period T44 immediately after the period T33 is a stage T4 (see FIG. 3) in each process of the instruction A and the instruction B, and the write-back process WB of the instruction A is executed, while the instruction B The memory access process MEM is executed. More specifically, it is as follows. In the period T44, the writing unit 28 receives the data read by the reading unit 27 in step T3 (data instructed to be read by the instruction A) from the reading unit 27, and receives the received data in a predetermined register of the data register 30. Write to the area. The above is the content of the write-back process WB of the instruction A, and the process of the instruction A ends with the end of the period T44.

  Further, in the period T44, the selection control instructing the selection unit 26 in FIG. 2 to select the data supplied to the other input terminal (that is, the address information specified by the instruction B written in the register 23e). A signal is supplied from the decoding unit 24. As a result, the address information specified by the instruction B is supplied to the reading unit 27. Then, the reading unit 27 reads the data stored in the area indicated by the address information supplied from the selection unit 26 in the data memory 40. The above is the contents of the memory access processing MEM of the instruction B.

  As shown in FIG. 4, a period T55 immediately after the period T44 is a stage T5 (see FIG. 3) in the process of the instruction B, and only the write back process WB of the instruction B is executed. More specifically, in the period T55, the writing unit 28 receives the data read by the reading unit 27 in the period T44 (data instructed to be read by the instruction B) from the reading unit 27, and receives the received data. Write to a predetermined area of the data register 30. The above is the content of the write-back process WB of the instruction B, and the process of the instruction B ends with the end of the period T55.

  As described above, according to the present embodiment, since the instruction A and the instruction B that are different from each other in the stage in which the memory access process MEM is performed are executed at the same time, the utilization efficiency of the data memory 40 can be improved. . More specifically, as shown in FIG. 4, in the present embodiment, since the instruction A and the instruction B that are different from each other by “1” are executed simultaneously, the data memory 40 is stored in the memory access process MEM. The operation can be continued over the period T33 and the period T44. Thereby, the utilization efficiency of the data memory 40 can be improved. In addition, according to the present embodiment, it is possible to prevent the memory access process MEM of the instruction A and the memory access process MEM of the instruction B from being performed at the same timing, and thus it is possible to prevent an increase in time required for the instruction process. You can also.

  Here, it is assumed that two instructions for performing the memory access process MEM are executed in order at different stages of the pipeline process. Of the two instructions, an instruction having a smaller number of stages until the memory access process MEM is performed is a first instruction, and an instruction having a larger number of stages until the memory access process is performed is a second instruction. When each instruction is executed in the order of the instruction → the second instruction, since the period from the memory access process of the first instruction until the memory access process of the second instruction is performed becomes longer, The period during which the apparatus is in a standby state without operating is also lengthened. This causes a problem that the use efficiency of the memory is lowered.

  For example, as shown in FIG. 5A, when the instructions A are executed in the order of the instruction B, the memory access process MEM of the instruction A is performed in the period T33, and the memory access process MEM of the instruction B is performed in the period T55. . That is, since the data memory 40 is not operated in the period T44 and is in a standby state, the utilization efficiency of the data memory 40 is lowered.

  On the other hand, when the respective instructions are executed in the order of the second instruction → the first instruction, the memory access process MEM for the first instruction and the memory access process MEM for the second instruction may be performed at the same timing. In this case, since the memory access process MEM for the first instruction cannot be executed until the memory access process MEM for the second instruction is completed, there arises a problem that the time required for the instruction process increases as a result.

  For example, as shown in FIG. 5B, when the instruction B is executed in the order of the instruction A, both the period during which the memory access process MEM for the instruction B is performed and the period during which the memory access process MEM for the instruction A is performed Since the period T44 is reached, the memory access process MEM of the other instruction A cannot be performed until the memory access process MEM of the instruction B is completed, and as a result, the time required for the instruction process increases.

  As described above, when two instructions for which the memory access process MEM is performed at different stages of the pipeline process are executed in order, the use efficiency of the data memory 40 is lowered or the time required for the instruction process is increased. Problem occurs.

  On the other hand, according to the present embodiment, the data memory 40 can be operated continuously over the period T33 and the period T44, so that the utilization efficiency of the data memory is improved as compared with the case of FIG. It becomes possible to make it. Further, according to the present embodiment, the period during which the memory access process MEM for the instruction A is performed and the period during which the memory access process MEM for the instruction B are performed can be prevented from being the same as in the case of FIG. Unlike this, it is possible to prevent an increase in the time required for processing an instruction. That is, according to the present embodiment, it is possible to improve the utilization efficiency of the data memory 40 and to prevent an increase in time required for instruction processing.

(Modification)
As mentioned above, although embodiment of this invention was described, this embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  For example, in the above-described embodiment, two instructions (instruction A and instruction B) that are different from each other by “1” are executed at the same time. However, the present invention is not limited to this. Two instructions that are different from each other by “2” may be executed simultaneously. In short, it is only necessary that two instructions having different stages in which memory access processing is performed are executed simultaneously.

  In the above embodiment, the data register 30 stores the correction value R and the data read by the memory access process. For example, the data register 30 stores the correction value R and the data read by the memory access process. The configuration may be such that the output data is stored in separate registers.

  In the above-described embodiment, a data memory has been described as an example of an operation resource that cannot be multiplexed, and a memory access process has been described as an example of an operation process using the operation resource. The contents of the calculation processing using the calculation resources and the calculation resources are arbitrary.

  In the above-described embodiment, the address information is calculated by adding the reference value I and the correction value R. However, the present invention is not limited to this, and the address information calculation method is arbitrary. For example, the data register 30 stores various parameter values used for calculating the address information, and the address information is calculated based on a plurality (for example, two) of parameter values specified by the instruction B. Also good.

  In the above-described embodiment, two instructions are fetched and decoded at the same time. However, the present invention is not limited to this. For example, fetching and decoding three or more instructions at different stages in which the memory access processing MEM is performed is simultaneously performed. Is also possible. Hereinafter, an example will be described. FIG. 6 is a block diagram illustrating an example of the configuration of the arithmetic device 200 that simultaneously executes the instruction A, the instruction B, and the instruction C that are different from each other by “1” in the stage where the memory access process MEM is performed. As shown in FIG. 6, in addition to the contents described in the above-described embodiment, the load / store unit 20 includes registers 23g, 23h, 23i, 23j, and 23k, an address information calculation unit 50, an address information calculation unit 51, Is further provided. The instruction fetch unit 22 is configured to be able to fetch three instructions simultaneously from the program memory 21. Further, the decoding unit 24 is configured to be able to decode three instructions simultaneously.

  In the configuration example of FIG. 6, the program memory 21 stores three types of instructions (instruction A, instruction B, and instruction C) described in a predetermined program code. As shown in FIG. 7, the processing of instruction C is divided into stage T1, stage T2, stage T3, stage T4, stage T5, and stage T6.

  As shown in FIG. 7, a fetch process IF is performed at stage T1. More specifically, the instruction fetch unit 22 reads the instruction C with reference to the instruction address information supplied from the control unit 10 in the program memory 21. The instruction fetch unit 22 writes the read instruction C into the register 23g shown in FIG.

  As shown in FIG. 7, a decoding process ID is performed at stage T2. More specifically, it is as follows. The decoding unit 24 decodes the instruction C written in the register 23g. Here, in the program code constituting the instruction C, the above address information is not described directly, but calculation information for calculating the address information is described. The calculation information includes reference information indicating the reference value I when calculating the address information, and register information indicating an area in the data register 30 in which the correction value R2 to be read is stored. Then, the decoding unit 24 writes the reference value I specified from the decoded instruction C to the register 23 h shown in FIG. 6 and supplies the register information specified from the content of the decoded instruction C to the data register 30.

  As shown in FIG. 7, in the stage T3, an address calculation process EX1 is performed. More specifically, it is as follows. The data register 30 shown in FIG. 6 reads the correction value R2 stored in the area indicated by the register information from the decoding unit 24, and supplies the read correction value R2 to the register 23i shown in FIG. Then, the address information calculation unit 50 shown in FIG. 6 calculates the offset value X by multiplying the eigenvalue M possessed by itself and the correction value R2 written in the register 23i. The address information calculation unit 50 writes the calculated offset value X and the reference value I supplied from the register 23h in the register 23j shown in FIG. The above is the content of the instruction C address calculation processing EX1.

  As shown in FIG. 7, in the stage T4, an address calculation process EX2 is performed. More specifically, the address information calculation unit 51 shown in FIG. 6 adds the offset value X supplied from the register 23j and the reference value I to calculate the address information specified by the instruction C. The address information calculation unit 51 writes the calculated address information in the register 23k. The above is the content of the instruction C address calculation processing EX2.

  As shown in FIG. 7, at stage T5, a memory access process MEM is performed. More specifically, it is as follows. Here, the selection unit 26 shown in FIG. 6 has a first input terminal to which the address information (address information specified by the instruction A) written in the register 23c is supplied, and the address information (command) written in the register 23e. The second input terminal to which the address information specified by B) is supplied, and the third input terminal to which the address information (address information specified by the instruction C) written in the register 23k is supplied. In response to a selection control signal (not shown) supplied from the decoding unit 24, the selection unit 26 supplies address information supplied to one of the input terminals to the subsequent reading unit 27. In stage T5, the selection unit 26 is supplied with a selection control signal for instructing selection of the address information designated by the instruction C from the decoding unit 24. As a result, the address information specified by the instruction C is supplied to the reading unit 27. Then, the reading unit 27 reads the data stored in the area indicated by the address information supplied from the selection unit 26 in the data memory 40. The above is the contents of the memory access processing MEM of the instruction C.

  As shown in FIG. 7, at the stage T6, the write-back process WB is performed. More specifically, the writing unit 28 receives data read by the reading unit 27 (data instructed to be read by the instruction C) from the reading unit 27, and receives the received data in a predetermined area of the data register 30. Write to. The above is the content of the write-back process WB of the instruction C.

  As described above, in the processing of the instruction C, the memory access processing MEM is performed in the fifth stage T5. Therefore, the number of stages until the memory access processing MEM is performed as compared with the processing of the instruction A. And the number of stages until the memory access process MEM is performed is one more than the process of the instruction B. The instruction A, the instruction B, and the instruction C are simultaneously executed, so that the data memory 40 can be operated continuously, and the memory access processes MEM of the instruction A, the instruction B, and the instruction C are the same. This can be done at the timing. In short, an instruction for performing the memory access process MEM in the Nth stage, an instruction for performing the memory access process MEM in the (N + 1) th stage, and a memory access process MEM in the (N + 2) th stage. By executing the instructions at the same time, the data memory 40 can be operated continuously, and the memory access processing MEM of each instruction can be prevented from being performed at the same timing.

  As a modification of the above-described embodiment, the arithmetic device 100 may further include an execution unit that executes a predetermined operation using data read by the memory access process. Further, as shown in FIG. 8, the arithmetic unit 100 starts processing of the instruction A and the instruction B simultaneously, waits for two stages, and then starts processing of another instruction A and the instruction B simultaneously. You can also. Furthermore, the time length of each stage (T1-T5) is arbitrary. For example, the time length of the stage where the address calculation processing is performed may be longer than the time length of the stage where the fetch processing or decoding processing is performed, and a larger number of clock cycles may be required.

DESCRIPTION OF SYMBOLS 10 Control unit 20 Load store unit 21 Program memory 22 Instruction fetch part 24 Decoding part 27 Reading part 40 Data memory 100 Arithmetic unit

Claims (5)

An instruction storage unit for storing a first instruction and a second instruction for executing arithmetic processing using arithmetic resources at mutually different stages of pipeline processing;
A fetch unit for simultaneously fetching the first instruction and the second instruction;
A decoding unit for simultaneously decoding the fetched first instruction and the second instruction;
An arithmetic device comprising: An arithmetic processing unit that executes the arithmetic processing according to the decoded first instruction, and executes the arithmetic processing according to the decoded second instruction after the arithmetic processing according to the decoded first instruction. In addition,
The arithmetic unit according to claim 1. The first instruction executes the arithmetic processing at an Nth stage of pipeline processing, while the second instruction executes the arithmetic processing at an N + 1th stage of pipeline processing.
The arithmetic unit according to claim 1 or claim 2, wherein The computing resource is a data memory for storing data.
The arithmetic unit according to any one of claims 1 to 3, characterized in that: The first instruction describes address information indicating an area of the data memory in which the data to be read is stored, while the second instruction includes calculation information for calculating the address information. Described,
The address information is calculated using the calculation information between the time when the decoding unit decodes the first instruction and the second instruction and before the start of the arithmetic processing according to the second instruction. An address information calculation unit;
The arithmetic processing executed by the arithmetic processing unit is a process of reading the data stored in an area indicated by the address information in the data memory.
The arithmetic unit according to claim 4, wherein:

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